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regulator: qcom_spmi: Add support for HFSMPS regulator type
[linux-block.git] / drivers / regulator / qcom_spmi-regulator.c
CommitLineData
97fb5e8d 1// SPDX-License-Identifier: GPL-2.0-only
e92a4047
SB		 2/*
3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
e92a4047
SB		 4 */
5
6#include <linux/module.h>
7#include <linux/delay.h>
b6688015 8#include <linux/devm-helpers.h>
e92a4047
SB		 9#include <linux/err.h>
10#include <linux/kernel.h>
11#include <linux/interrupt.h>
12#include <linux/bitops.h>
13#include <linux/slab.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include <linux/ktime.h>
18#include <linux/regulator/driver.h>
19#include <linux/regmap.h>
20#include <linux/list.h>
0caecaa8
IL		 21#include <linux/mfd/syscon.h>
22#include <linux/io.h>
e92a4047 23
e2adfacd
SB		 24/* Pin control enable input pins. */
25#define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30#define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
31
32/* Pin control high power mode input pins. */
33#define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34#define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35#define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36#define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
37#define SPMI_REGULATOR_PIN_CTRL_HPM_EN3 0x08
38#define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10
39#define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20
40
41/*
42 * Used with enable parameters to specify that hardware default register values
43 * should be left unaltered.
44 */
45#define SPMI_REGULATOR_USE_HW_DEFAULT 2
46
47/* Soft start strength of a voltage switch type regulator */
48enum spmi_vs_soft_start_str {
49 SPMI_VS_SOFT_START_STR_0P05_UA = 0,
50 SPMI_VS_SOFT_START_STR_0P25_UA,
51 SPMI_VS_SOFT_START_STR_0P55_UA,
52 SPMI_VS_SOFT_START_STR_0P75_UA,
53 SPMI_VS_SOFT_START_STR_HW_DEFAULT,
54};
55
56/**
57 * struct spmi_regulator_init_data - spmi-regulator initialization data
58 * @pin_ctrl_enable: Bit mask specifying which hardware pins should be
59 * used to enable the regulator, if any
60 * Value should be an ORing of
61 * SPMI_REGULATOR_PIN_CTRL_ENABLE_* constants. If
62 * the bit specified by
63 * SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is
64 * set, then pin control enable hardware registers
65 * will not be modified.
66 * @pin_ctrl_hpm: Bit mask specifying which hardware pins should be
67 * used to force the regulator into high power
68 * mode, if any
69 * Value should be an ORing of
70 * SPMI_REGULATOR_PIN_CTRL_HPM_* constants. If
71 * the bit specified by
72 * SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is
73 * set, then pin control mode hardware registers
74 * will not be modified.
75 * @vs_soft_start_strength: This parameter sets the soft start strength for
76 * voltage switch type regulators. Its value
77 * should be one of SPMI_VS_SOFT_START_STR_*. If
78 * its value is SPMI_VS_SOFT_START_STR_HW_DEFAULT,
79 * then the soft start strength will be left at its
80 * default hardware value.
81 */
82struct spmi_regulator_init_data {
83 unsigned pin_ctrl_enable;
84 unsigned pin_ctrl_hpm;
85 enum spmi_vs_soft_start_str vs_soft_start_strength;
86};
87
e92a4047
SB		 88/* These types correspond to unique register layouts. */
89enum spmi_regulator_logical_type {
90 SPMI_REGULATOR_LOGICAL_TYPE_SMPS,
91 SPMI_REGULATOR_LOGICAL_TYPE_LDO,
92 SPMI_REGULATOR_LOGICAL_TYPE_VS,
93 SPMI_REGULATOR_LOGICAL_TYPE_BOOST,
94 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS,
95 SPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP,
96 SPMI_REGULATOR_LOGICAL_TYPE_LN_LDO,
97 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS,
98 SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS,
99 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO,
42ba89c8 100 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426,
0211f68e 101 SPMI_REGULATOR_LOGICAL_TYPE_HFS430,
27850254 102 SPMI_REGULATOR_LOGICAL_TYPE_HFSMPS,
e92a4047
SB		 103};
104
105enum spmi_regulator_type {
106 SPMI_REGULATOR_TYPE_BUCK = 0x03,
107 SPMI_REGULATOR_TYPE_LDO = 0x04,
108 SPMI_REGULATOR_TYPE_VS = 0x05,
109 SPMI_REGULATOR_TYPE_BOOST = 0x1b,
110 SPMI_REGULATOR_TYPE_FTS = 0x1c,
111 SPMI_REGULATOR_TYPE_BOOST_BYP = 0x1f,
112 SPMI_REGULATOR_TYPE_ULT_LDO = 0x21,
113 SPMI_REGULATOR_TYPE_ULT_BUCK = 0x22,
114};
115
116enum spmi_regulator_subtype {
117 SPMI_REGULATOR_SUBTYPE_GP_CTL = 0x08,
118 SPMI_REGULATOR_SUBTYPE_RF_CTL = 0x09,
119 SPMI_REGULATOR_SUBTYPE_N50 = 0x01,
120 SPMI_REGULATOR_SUBTYPE_N150 = 0x02,
121 SPMI_REGULATOR_SUBTYPE_N300 = 0x03,
122 SPMI_REGULATOR_SUBTYPE_N600 = 0x04,
123 SPMI_REGULATOR_SUBTYPE_N1200 = 0x05,
124 SPMI_REGULATOR_SUBTYPE_N600_ST = 0x06,
125 SPMI_REGULATOR_SUBTYPE_N1200_ST = 0x07,
126 SPMI_REGULATOR_SUBTYPE_N900_ST = 0x14,
127 SPMI_REGULATOR_SUBTYPE_N300_ST = 0x15,
128 SPMI_REGULATOR_SUBTYPE_P50 = 0x08,
129 SPMI_REGULATOR_SUBTYPE_P150 = 0x09,
130 SPMI_REGULATOR_SUBTYPE_P300 = 0x0a,
131 SPMI_REGULATOR_SUBTYPE_P600 = 0x0b,
132 SPMI_REGULATOR_SUBTYPE_P1200 = 0x0c,
133 SPMI_REGULATOR_SUBTYPE_LN = 0x10,
134 SPMI_REGULATOR_SUBTYPE_LV_P50 = 0x28,
135 SPMI_REGULATOR_SUBTYPE_LV_P150 = 0x29,
136 SPMI_REGULATOR_SUBTYPE_LV_P300 = 0x2a,
137 SPMI_REGULATOR_SUBTYPE_LV_P600 = 0x2b,
138 SPMI_REGULATOR_SUBTYPE_LV_P1200 = 0x2c,
139 SPMI_REGULATOR_SUBTYPE_LV_P450 = 0x2d,
328816c2
ADR		 140 SPMI_REGULATOR_SUBTYPE_HT_N300_ST = 0x30,
141 SPMI_REGULATOR_SUBTYPE_HT_N600_ST = 0x31,
142 SPMI_REGULATOR_SUBTYPE_HT_N1200_ST = 0x32,
143 SPMI_REGULATOR_SUBTYPE_HT_LVP150 = 0x3b,
144 SPMI_REGULATOR_SUBTYPE_HT_LVP300 = 0x3c,
145 SPMI_REGULATOR_SUBTYPE_L660_N300_ST = 0x42,
146 SPMI_REGULATOR_SUBTYPE_L660_N600_ST = 0x43,
147 SPMI_REGULATOR_SUBTYPE_L660_P50 = 0x46,
148 SPMI_REGULATOR_SUBTYPE_L660_P150 = 0x47,
149 SPMI_REGULATOR_SUBTYPE_L660_P600 = 0x49,
150 SPMI_REGULATOR_SUBTYPE_L660_LVP150 = 0x4d,
151 SPMI_REGULATOR_SUBTYPE_L660_LVP600 = 0x4f,
e92a4047
SB		 152 SPMI_REGULATOR_SUBTYPE_LV100 = 0x01,
153 SPMI_REGULATOR_SUBTYPE_LV300 = 0x02,
154 SPMI_REGULATOR_SUBTYPE_MV300 = 0x08,
155 SPMI_REGULATOR_SUBTYPE_MV500 = 0x09,
156 SPMI_REGULATOR_SUBTYPE_HDMI = 0x10,
157 SPMI_REGULATOR_SUBTYPE_OTG = 0x11,
158 SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01,
159 SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08,
160 SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09,
42ba89c8 161 SPMI_REGULATOR_SUBTYPE_FTS426_CTL = 0x0a,
e92a4047
SB		 162 SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01,
163 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d,
164 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e,
165 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f,
166 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
0211f68e 167 SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
00f6ebbd 168 SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35,
3d04ae8e 169 SPMI_REGULATOR_SUBTYPE_HT_P600 = 0x3d,
27850254 170 SPMI_REGULATOR_SUBTYPE_HFSMPS_510 = 0x0a,
e92a4047
SB		 171};
172
173enum spmi_common_regulator_registers {
174 SPMI_COMMON_REG_DIG_MAJOR_REV = 0x01,
175 SPMI_COMMON_REG_TYPE = 0x04,
176 SPMI_COMMON_REG_SUBTYPE = 0x05,
177 SPMI_COMMON_REG_VOLTAGE_RANGE = 0x40,
178 SPMI_COMMON_REG_VOLTAGE_SET = 0x41,
179 SPMI_COMMON_REG_MODE = 0x45,
180 SPMI_COMMON_REG_ENABLE = 0x46,
181 SPMI_COMMON_REG_PULL_DOWN = 0x48,
182 SPMI_COMMON_REG_SOFT_START = 0x4c,
183 SPMI_COMMON_REG_STEP_CTRL = 0x61,
184};
185
42ba89c8
JH		 186/*
187 * Second common register layout used by newer devices starting with ftsmps426
188 * Note that some of the registers from the first common layout remain
189 * unchanged and their definition is not duplicated.
190 */
191enum spmi_ftsmps426_regulator_registers {
192 SPMI_FTSMPS426_REG_VOLTAGE_LSB = 0x40,
193 SPMI_FTSMPS426_REG_VOLTAGE_MSB = 0x41,
194 SPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 0x68,
195 SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 0x69,
196};
197
27850254
IC		 198/*
199 * Third common register layout
200 */
201enum spmi_hfsmps_regulator_registers {
202 SPMI_HFSMPS_REG_STEP_CTRL = 0x3c,
203 SPMI_HFSMPS_REG_PULL_DOWN = 0xa0,
204};
205
e92a4047
SB		 206enum spmi_vs_registers {
207 SPMI_VS_REG_OCP = 0x4a,
208 SPMI_VS_REG_SOFT_START = 0x4c,
209};
210
211enum spmi_boost_registers {
212 SPMI_BOOST_REG_CURRENT_LIMIT = 0x4a,
213};
214
215enum spmi_boost_byp_registers {
216 SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b,
217};
218
0caecaa8
IL		 219enum spmi_saw3_registers {
220 SAW3_SECURE = 0x00,
221 SAW3_ID = 0x04,
222 SAW3_SPM_STS = 0x0C,
223 SAW3_AVS_STS = 0x10,
224 SAW3_PMIC_STS = 0x14,
225 SAW3_RST = 0x18,
226 SAW3_VCTL = 0x1C,
227 SAW3_AVS_CTL = 0x20,
228 SAW3_AVS_LIMIT = 0x24,
229 SAW3_AVS_DLY = 0x28,
230 SAW3_AVS_HYSTERESIS = 0x2C,
231 SAW3_SPM_STS2 = 0x38,
232 SAW3_SPM_PMIC_DATA_3 = 0x4C,
233 SAW3_VERSION = 0xFD0,
234};
235
e92a4047
SB		 236/* Used for indexing into ctrl_reg. These are offets from 0x40 */
237enum spmi_common_control_register_index {
238 SPMI_COMMON_IDX_VOLTAGE_RANGE = 0,
239 SPMI_COMMON_IDX_VOLTAGE_SET = 1,
240 SPMI_COMMON_IDX_MODE = 5,
241 SPMI_COMMON_IDX_ENABLE = 6,
242};
243
244/* Common regulator control register layout */
245#define SPMI_COMMON_ENABLE_MASK 0x80
246#define SPMI_COMMON_ENABLE 0x80
247#define SPMI_COMMON_DISABLE 0x00
248#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK 0x08
249#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK 0x04
250#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK 0x02
251#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK 0x01
252#define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK 0x0f
253
254/* Common regulator mode register layout */
255#define SPMI_COMMON_MODE_HPM_MASK 0x80
256#define SPMI_COMMON_MODE_AUTO_MASK 0x40
257#define SPMI_COMMON_MODE_BYPASS_MASK 0x20
258#define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK 0x10
259#define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK 0x08
260#define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK 0x04
261#define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK 0x02
262#define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01
263#define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f
264
42ba89c8
JH		 265#define SPMI_FTSMPS426_MODE_BYPASS_MASK 3
266#define SPMI_FTSMPS426_MODE_RETENTION_MASK 4
267#define SPMI_FTSMPS426_MODE_LPM_MASK 5
268#define SPMI_FTSMPS426_MODE_AUTO_MASK 6
269#define SPMI_FTSMPS426_MODE_HPM_MASK 7
270
271#define SPMI_FTSMPS426_MODE_MASK 0x07
272
27850254
IC		 273/* Third common regulator mode register values */
274#define SPMI_HFSMPS_MODE_BYPASS_MASK 2
275#define SPMI_HFSMPS_MODE_RETENTION_MASK 3
276#define SPMI_HFSMPS_MODE_LPM_MASK 4
277#define SPMI_HFSMPS_MODE_AUTO_MASK 6
278#define SPMI_HFSMPS_MODE_HPM_MASK 7
279
280#define SPMI_HFSMPS_MODE_MASK 0x07
281
e92a4047
SB		 282/* Common regulator pull down control register layout */
283#define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80
284
285/* LDO regulator current limit control register layout */
286#define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK 0x80
287
288/* LDO regulator soft start control register layout */
289#define SPMI_LDO_SOFT_START_ENABLE_MASK 0x80
290
291/* VS regulator over current protection control register layout */
292#define SPMI_VS_OCP_OVERRIDE 0x01
293#define SPMI_VS_OCP_NO_OVERRIDE 0x00
294
295/* VS regulator soft start control register layout */
296#define SPMI_VS_SOFT_START_ENABLE_MASK 0x80
297#define SPMI_VS_SOFT_START_SEL_MASK 0x03
298
299/* Boost regulator current limit control register layout */
300#define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK 0x80
301#define SPMI_BOOST_CURRENT_LIMIT_MASK 0x07
302
303#define SPMI_VS_OCP_DEFAULT_MAX_RETRIES 10
304#define SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS 30
305#define SPMI_VS_OCP_FALL_DELAY_US 90
306#define SPMI_VS_OCP_FAULT_DELAY_US 20000
307
308#define SPMI_FTSMPS_STEP_CTRL_STEP_MASK 0x18
309#define SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT 3
310#define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07
311#define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0
312
313/* Clock rate in kHz of the FTSMPS regulator reference clock. */
314#define SPMI_FTSMPS_CLOCK_RATE 19200
315
316/* Minimum voltage stepper delay for each step. */
317#define SPMI_FTSMPS_STEP_DELAY 8
2cf7b99c 318#define SPMI_DEFAULT_STEP_DELAY 20
e92a4047
SB		 319
320/*
321 * The ratio SPMI_FTSMPS_STEP_MARGIN_NUM/SPMI_FTSMPS_STEP_MARGIN_DEN is used to
322 * adjust the step rate in order to account for oscillator variance.
323 */
324#define SPMI_FTSMPS_STEP_MARGIN_NUM 4
325#define SPMI_FTSMPS_STEP_MARGIN_DEN 5
326
27850254
IC		 327/* slew_rate has units of uV/us. */
328#define SPMI_HFSMPS_SLEW_RATE_38p4 38400
329
42ba89c8
JH		 330#define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK 0x03
331#define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT 0
332
333/* Clock rate in kHz of the FTSMPS426 regulator reference clock. */
334#define SPMI_FTSMPS426_CLOCK_RATE 4800
335
0211f68e
JR		 336#define SPMI_HFS430_CLOCK_RATE 1600
337
42ba89c8
JH		 338/* Minimum voltage stepper delay for each step. */
339#define SPMI_FTSMPS426_STEP_DELAY 2
340
341/*
342 * The ratio SPMI_FTSMPS426_STEP_MARGIN_NUM/SPMI_FTSMPS426_STEP_MARGIN_DEN is
343 * used to adjust the step rate in order to account for oscillator variance.
344 */
345#define SPMI_FTSMPS426_STEP_MARGIN_NUM 10
346#define SPMI_FTSMPS426_STEP_MARGIN_DEN 11
347
348
e92a4047
SB		 349/* VSET value to decide the range of ULT SMPS */
350#define ULT_SMPS_RANGE_SPLIT 0x60
351
352/**
353 * struct spmi_voltage_range - regulator set point voltage mapping description
354 * @min_uV: Minimum programmable output voltage resulting from
355 * set point register value 0x00
356 * @max_uV: Maximum programmable output voltage
357 * @step_uV: Output voltage increase resulting from the set point
358 * register value increasing by 1
359 * @set_point_min_uV: Minimum allowed voltage
360 * @set_point_max_uV: Maximum allowed voltage. This may be tweaked in order
361 * to pick which range should be used in the case of
362 * overlapping set points.
363 * @n_voltages: Number of preferred voltage set points present in this
364 * range
365 * @range_sel: Voltage range register value corresponding to this range
366 *
367 * The following relationships must be true for the values used in this struct:
368 * (max_uV - min_uV) % step_uV == 0
369 * (set_point_min_uV - min_uV) % step_uV == 0*
370 * (set_point_max_uV - min_uV) % step_uV == 0*
371 * n_voltages = (set_point_max_uV - set_point_min_uV) / step_uV + 1
372 *
373 * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to
374 * specify that the voltage range has meaning, but is not preferred.
375 */
376struct spmi_voltage_range {
377 int min_uV;
378 int max_uV;
379 int step_uV;
380 int set_point_min_uV;
381 int set_point_max_uV;
382 unsigned n_voltages;
383 u8 range_sel;
384};
385
386/*
387 * The ranges specified in the spmi_voltage_set_points struct must be listed
388 * so that range[i].set_point_max_uV < range[i+1].set_point_min_uV.
389 */
390struct spmi_voltage_set_points {
391 struct spmi_voltage_range *range;
392 int count;
393 unsigned n_voltages;
394};
395
396struct spmi_regulator {
397 struct regulator_desc desc;
398 struct device *dev;
399 struct delayed_work ocp_work;
400 struct regmap *regmap;
401 struct spmi_voltage_set_points *set_points;
402 enum spmi_regulator_logical_type logical_type;
403 int ocp_irq;
404 int ocp_count;
405 int ocp_max_retries;
406 int ocp_retry_delay_ms;
407 int hpm_min_load;
408 int slew_rate;
409 ktime_t vs_enable_time;
410 u16 base;
411 struct list_head node;
412};
413
414struct spmi_regulator_mapping {
415 enum spmi_regulator_type type;
416 enum spmi_regulator_subtype subtype;
417 enum spmi_regulator_logical_type logical_type;
418 u32 revision_min;
419 u32 revision_max;
3b619e3e 420 const struct regulator_ops *ops;
e92a4047
SB		 421 struct spmi_voltage_set_points *set_points;
422 int hpm_min_load;
423};
424
425struct spmi_regulator_data {
426 const char *name;
427 u16 base;
428 const char *supply;
429 const char *ocp;
430 u16 force_type;
431};
432
433#define SPMI_VREG(_type, _subtype, _dig_major_min, _dig_major_max, \
434 _logical_type, _ops_val, _set_points_val, _hpm_min_load) \
435 { \
436 .type = SPMI_REGULATOR_TYPE_##_type, \
437 .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \
438 .revision_min = _dig_major_min, \
439 .revision_max = _dig_major_max, \
440 .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_##_logical_type, \
441 .ops = &spmi_##_ops_val##_ops, \
442 .set_points = &_set_points_val##_set_points, \
443 .hpm_min_load = _hpm_min_load, \
444 }
445
446#define SPMI_VREG_VS(_subtype, _dig_major_min, _dig_major_max) \
447 { \
448 .type = SPMI_REGULATOR_TYPE_VS, \
449 .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \
450 .revision_min = _dig_major_min, \
451 .revision_max = _dig_major_max, \
452 .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_VS, \
453 .ops = &spmi_vs_ops, \
454 }
455
456#define SPMI_VOLTAGE_RANGE(_range_sel, _min_uV, _set_point_min_uV, \
457 _set_point_max_uV, _max_uV, _step_uV) \
458 { \
459 .min_uV = _min_uV, \
460 .max_uV = _max_uV, \
461 .set_point_min_uV = _set_point_min_uV, \
462 .set_point_max_uV = _set_point_max_uV, \
463 .step_uV = _step_uV, \
464 .range_sel = _range_sel, \
465 }
466
467#define DEFINE_SPMI_SET_POINTS(name) \
468struct spmi_voltage_set_points name##_set_points = { \
469 .range = name##_ranges, \
470 .count = ARRAY_SIZE(name##_ranges), \
471}
472
473/*
474 * These tables contain the physically available PMIC regulator voltage setpoint
475 * ranges. Where two ranges overlap in hardware, one of the ranges is trimmed
476 * to ensure that the setpoints available to software are monotonically
477 * increasing and unique. The set_voltage callback functions expect these
478 * properties to hold.
479 */
480static struct spmi_voltage_range pldo_ranges[] = {
481 SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500),
482 SPMI_VOLTAGE_RANGE(3, 1500000, 1550000, 3075000, 3075000, 25000),
483 SPMI_VOLTAGE_RANGE(4, 1750000, 3100000, 4900000, 4900000, 50000),
484};
485
486static struct spmi_voltage_range nldo1_ranges[] = {
487 SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500),
488};
489
490static struct spmi_voltage_range nldo2_ranges[] = {
491 SPMI_VOLTAGE_RANGE(0, 375000, 0, 0, 1537500, 12500),
492 SPMI_VOLTAGE_RANGE(1, 375000, 375000, 768750, 768750, 6250),
493 SPMI_VOLTAGE_RANGE(2, 750000, 775000, 1537500, 1537500, 12500),
494};
495
496static struct spmi_voltage_range nldo3_ranges[] = {
497 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500),
498 SPMI_VOLTAGE_RANGE(1, 375000, 0, 0, 1537500, 12500),
499 SPMI_VOLTAGE_RANGE(2, 750000, 0, 0, 1537500, 12500),
500};
501
502static struct spmi_voltage_range ln_ldo_ranges[] = {
503 SPMI_VOLTAGE_RANGE(1, 690000, 690000, 1110000, 1110000, 60000),
504 SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000),
505};
506
507static struct spmi_voltage_range smps_ranges[] = {
508 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
509 SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000),
510};
511
512static struct spmi_voltage_range ftsmps_ranges[] = {
513 SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000),
514 SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000),
515};
516
517static struct spmi_voltage_range ftsmps2p5_ranges[] = {
518 SPMI_VOLTAGE_RANGE(0, 80000, 350000, 1355000, 1355000, 5000),
519 SPMI_VOLTAGE_RANGE(1, 160000, 1360000, 2200000, 2200000, 10000),
520};
521
42ba89c8
JH		 522static struct spmi_voltage_range ftsmps426_ranges[] = {
523 SPMI_VOLTAGE_RANGE(0, 0, 320000, 1352000, 1352000, 4000),
524};
525
e92a4047
SB		 526static struct spmi_voltage_range boost_ranges[] = {
527 SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000),
528};
529
530static struct spmi_voltage_range boost_byp_ranges[] = {
531 SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000),
532};
533
534static struct spmi_voltage_range ult_lo_smps_ranges[] = {
535 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
536 SPMI_VOLTAGE_RANGE(1, 750000, 0, 0, 1525000, 25000),
537};
538
539static struct spmi_voltage_range ult_ho_smps_ranges[] = {
540 SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000),
541};
542
543static struct spmi_voltage_range ult_nldo_ranges[] = {
544 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500),
545};
546
547static struct spmi_voltage_range ult_pldo_ranges[] = {
548 SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500),
549};
550
328816c2
ADR		 551static struct spmi_voltage_range pldo660_ranges[] = {
552 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 3544000, 3544000, 8000),
553};
554
555static struct spmi_voltage_range nldo660_ranges[] = {
556 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000),
557};
558
559static struct spmi_voltage_range ht_lvpldo_ranges[] = {
560 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 2000000, 2000000, 8000),
561};
562
563static struct spmi_voltage_range ht_nldo_ranges[] = {
564 SPMI_VOLTAGE_RANGE(0, 312000, 312000, 1304000, 1304000, 8000),
565};
566
0211f68e
JR		 567static struct spmi_voltage_range hfs430_ranges[] = {
568 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000),
569};
570
00f6ebbd
RM		 571static struct spmi_voltage_range ht_p150_ranges[] = {
572 SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000),
573};
574
3d04ae8e
RM		 575static struct spmi_voltage_range ht_p600_ranges[] = {
576 SPMI_VOLTAGE_RANGE(0, 1704000, 1704000, 1896000, 1896000, 8000),
577};
578
e92a4047
SB		 579static DEFINE_SPMI_SET_POINTS(pldo);
580static DEFINE_SPMI_SET_POINTS(nldo1);
581static DEFINE_SPMI_SET_POINTS(nldo2);
582static DEFINE_SPMI_SET_POINTS(nldo3);
583static DEFINE_SPMI_SET_POINTS(ln_ldo);
584static DEFINE_SPMI_SET_POINTS(smps);
585static DEFINE_SPMI_SET_POINTS(ftsmps);
586static DEFINE_SPMI_SET_POINTS(ftsmps2p5);
42ba89c8 587static DEFINE_SPMI_SET_POINTS(ftsmps426);
e92a4047
SB		 588static DEFINE_SPMI_SET_POINTS(boost);
589static DEFINE_SPMI_SET_POINTS(boost_byp);
590static DEFINE_SPMI_SET_POINTS(ult_lo_smps);
591static DEFINE_SPMI_SET_POINTS(ult_ho_smps);
592static DEFINE_SPMI_SET_POINTS(ult_nldo);
593static DEFINE_SPMI_SET_POINTS(ult_pldo);
328816c2
ADR		 594static DEFINE_SPMI_SET_POINTS(pldo660);
595static DEFINE_SPMI_SET_POINTS(nldo660);
596static DEFINE_SPMI_SET_POINTS(ht_lvpldo);
597static DEFINE_SPMI_SET_POINTS(ht_nldo);
0211f68e 598static DEFINE_SPMI_SET_POINTS(hfs430);
00f6ebbd 599static DEFINE_SPMI_SET_POINTS(ht_p150);
3d04ae8e 600static DEFINE_SPMI_SET_POINTS(ht_p600);
e92a4047
SB		 601
602static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
603 int len)
604{
605 return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len);
606}
607
608static inline int spmi_vreg_write(struct spmi_regulator *vreg, u16 addr,
609 u8 *buf, int len)
610{
611 return regmap_bulk_write(vreg->regmap, vreg->base + addr, buf, len);
612}
613
614static int spmi_vreg_update_bits(struct spmi_regulator *vreg, u16 addr, u8 val,
615 u8 mask)
616{
617 return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val);
618}
619
e92a4047
SB		 620static int spmi_regulator_vs_enable(struct regulator_dev *rdev)
621{
622 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
623
624 if (vreg->ocp_irq) {
625 vreg->ocp_count = 0;
626 vreg->vs_enable_time = ktime_get();
627 }
628
9d485332 629 return regulator_enable_regmap(rdev);
e92a4047
SB		 630}
631
89a6a5e5
MV		 632static int spmi_regulator_vs_ocp(struct regulator_dev *rdev, int lim_uA,
633 int severity, bool enable)
e2adfacd
SB		 634{
635 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
636 u8 reg = SPMI_VS_OCP_OVERRIDE;
637
89a6a5e5
MV		 638 if (lim_uA || !enable || severity != REGULATOR_SEVERITY_PROT)
639 return -EINVAL;
640
e2adfacd
SB		 641 return spmi_vreg_write(vreg, SPMI_VS_REG_OCP, &reg, 1);
642}
643
e92a4047 644static int spmi_regulator_select_voltage(struct spmi_regulator *vreg,
1b5b1968 645 int min_uV, int max_uV)
e92a4047
SB		 646{
647 const struct spmi_voltage_range *range;
648 int uV = min_uV;
649 int lim_min_uV, lim_max_uV, i, range_id, range_max_uV;
1b5b1968 650 int selector, voltage_sel;
e92a4047
SB		 651
652 /* Check if request voltage is outside of physically settable range. */
653 lim_min_uV = vreg->set_points->range[0].set_point_min_uV;
654 lim_max_uV =
655 vreg->set_points->range[vreg->set_points->count - 1].set_point_max_uV;
656
657 if (uV < lim_min_uV && max_uV >= lim_min_uV)
658 uV = lim_min_uV;
659
660 if (uV < lim_min_uV || uV > lim_max_uV) {
661 dev_err(vreg->dev,
662 "request v=[%d, %d] is outside possible v=[%d, %d]\n",
663 min_uV, max_uV, lim_min_uV, lim_max_uV);
664 return -EINVAL;
665 }
666
667 /* Find the range which uV is inside of. */
668 for (i = vreg->set_points->count - 1; i > 0; i--) {
669 range_max_uV = vreg->set_points->range[i - 1].set_point_max_uV;
670 if (uV > range_max_uV && range_max_uV > 0)
671 break;
672 }
673
674 range_id = i;
675 range = &vreg->set_points->range[range_id];
e92a4047
SB		 676
677 /*
678 * Force uV to be an allowed set point by applying a ceiling function to
679 * the uV value.
680 */
1b5b1968
SB		 681 voltage_sel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
682 uV = voltage_sel * range->step_uV + range->min_uV;
e92a4047
SB		 683
684 if (uV > max_uV) {
685 dev_err(vreg->dev,
686 "request v=[%d, %d] cannot be met by any set point; "
687 "next set point: %d\n",
688 min_uV, max_uV, uV);
689 return -EINVAL;
690 }
691
1b5b1968 692 selector = 0;
e92a4047 693 for (i = 0; i < range_id; i++)
1b5b1968
SB		 694 selector += vreg->set_points->range[i].n_voltages;
695 selector += (uV - range->set_point_min_uV) / range->step_uV;
e92a4047 696
1b5b1968
SB		 697 return selector;
698}
699
700static int spmi_sw_selector_to_hw(struct spmi_regulator *vreg,
701 unsigned selector, u8 *range_sel,
702 u8 *voltage_sel)
703{
704 const struct spmi_voltage_range *range, *end;
ab953b9d 705 unsigned offset;
1b5b1968
SB		 706
707 range = vreg->set_points->range;
708 end = range + vreg->set_points->count;
709
710 for (; range < end; range++) {
711 if (selector < range->n_voltages) {
ab953b9d
SB		 712 /*
713 * hardware selectors between set point min and real
714 * min are invalid so we ignore them
715 */
716 offset = range->set_point_min_uV - range->min_uV;
717 offset /= range->step_uV;
718 *voltage_sel = selector + offset;
1b5b1968
SB		 719 *range_sel = range->range_sel;
720 return 0;
721 }
722
723 selector -= range->n_voltages;
724 }
725
726 return -EINVAL;
727}
728
729static int spmi_hw_selector_to_sw(struct spmi_regulator *vreg, u8 hw_sel,
730 const struct spmi_voltage_range *range)
731{
ab953b9d
SB		 732 unsigned sw_sel = 0;
733 unsigned offset, max_hw_sel;
1b5b1968 734 const struct spmi_voltage_range *r = vreg->set_points->range;
ab953b9d
SB		 735 const struct spmi_voltage_range *end = r + vreg->set_points->count;
736
737 for (; r < end; r++) {
738 if (r == range && range->n_voltages) {
739 /*
740 * hardware selectors between set point min and real
741 * min and between set point max and real max are
742 * invalid so we return an error if they're
743 * programmed into the hardware
744 */
745 offset = range->set_point_min_uV - range->min_uV;
746 offset /= range->step_uV;
747 if (hw_sel < offset)
748 return -EINVAL;
749
750 max_hw_sel = range->set_point_max_uV - range->min_uV;
751 max_hw_sel /= range->step_uV;
752 if (hw_sel > max_hw_sel)
753 return -EINVAL;
754
755 return sw_sel + hw_sel - offset;
756 }
1b5b1968 757 sw_sel += r->n_voltages;
1b5b1968
SB		 758 }
759
ab953b9d 760 return -EINVAL;
e92a4047
SB		 761}
762
763static const struct spmi_voltage_range *
764spmi_regulator_find_range(struct spmi_regulator *vreg)
765{
766 u8 range_sel;
767 const struct spmi_voltage_range *range, *end;
768
769 range = vreg->set_points->range;
770 end = range + vreg->set_points->count;
771
772 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, &range_sel, 1);
773
774 for (; range < end; range++)
775 if (range->range_sel == range_sel)
776 return range;
777
778 return NULL;
779}
780
781static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg,
1b5b1968 782 int min_uV, int max_uV)
e92a4047
SB		 783{
784 const struct spmi_voltage_range *range;
785 int uV = min_uV;
1b5b1968 786 int i, selector;
e92a4047
SB		 787
788 range = spmi_regulator_find_range(vreg);
789 if (!range)
790 goto different_range;
791
792 if (uV < range->min_uV && max_uV >= range->min_uV)
793 uV = range->min_uV;
794
795 if (uV < range->min_uV || uV > range->max_uV) {
796 /* Current range doesn't support the requested voltage. */
797 goto different_range;
798 }
799
800 /*
801 * Force uV to be an allowed set point by applying a ceiling function to
802 * the uV value.
803 */
1b5b1968
SB		 804 uV = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
805 uV = uV * range->step_uV + range->min_uV;
e92a4047
SB		 806
807 if (uV > max_uV) {
808 /*
809 * No set point in the current voltage range is within the
810 * requested min_uV to max_uV range.
811 */
812 goto different_range;
813 }
814
1b5b1968 815 selector = 0;
e92a4047
SB		 816 for (i = 0; i < vreg->set_points->count; i++) {
817 if (uV >= vreg->set_points->range[i].set_point_min_uV
9b2dfee3 818 && uV <= vreg->set_points->range[i].set_point_max_uV) {
1b5b1968 819 selector +=
e92a4047
SB		 820 (uV - vreg->set_points->range[i].set_point_min_uV)
821 / vreg->set_points->range[i].step_uV;
822 break;
9b2dfee3 823 }
e92a4047 824
1b5b1968 825 selector += vreg->set_points->range[i].n_voltages;
e92a4047
SB		 826 }
827
1b5b1968 828 if (selector >= vreg->set_points->n_voltages)
e92a4047
SB		 829 goto different_range;
830
b1d21a24 831 return selector;
e92a4047
SB		 832
833different_range:
1b5b1968 834 return spmi_regulator_select_voltage(vreg, min_uV, max_uV);
e92a4047
SB		 835}
836
1b5b1968
SB		 837static int spmi_regulator_common_map_voltage(struct regulator_dev *rdev,
838 int min_uV, int max_uV)
e92a4047
SB		 839{
840 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
e92a4047
SB		 841
842 /*
843 * Favor staying in the current voltage range if possible. This avoids
844 * voltage spikes that occur when changing the voltage range.
845 */
1b5b1968
SB		 846 return spmi_regulator_select_voltage_same_range(vreg, min_uV, max_uV);
847}
848
849static int
850spmi_regulator_common_set_voltage(struct regulator_dev *rdev, unsigned selector)
851{
852 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
853 int ret;
854 u8 buf[2];
855 u8 range_sel, voltage_sel;
856
857 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
e92a4047
SB		 858 if (ret)
859 return ret;
860
861 buf[0] = range_sel;
862 buf[1] = voltage_sel;
863 return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, buf, 2);
864}
865
42ba89c8
JH		 866static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev,
867 unsigned selector);
868
869static int spmi_regulator_ftsmps426_set_voltage(struct regulator_dev *rdev,
870 unsigned selector)
871{
872 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
873 u8 buf[2];
874 int mV;
875
876 mV = spmi_regulator_common_list_voltage(rdev, selector) / 1000;
877
878 buf[0] = mV & 0xff;
879 buf[1] = mV >> 8;
880 return spmi_vreg_write(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2);
881}
882
e92a4047
SB		 883static int spmi_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
884 unsigned int old_selector, unsigned int new_selector)
885{
886 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
e92a4047
SB		 887 int diff_uV;
888
61d7fdc4
JH		 889 diff_uV = abs(spmi_regulator_common_list_voltage(rdev, new_selector) -
890 spmi_regulator_common_list_voltage(rdev, old_selector));
e92a4047
SB		 891
892 return DIV_ROUND_UP(diff_uV, vreg->slew_rate);
893}
894
895static int spmi_regulator_common_get_voltage(struct regulator_dev *rdev)
896{
897 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
898 const struct spmi_voltage_range *range;
899 u8 voltage_sel;
900
901 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1);
902
903 range = spmi_regulator_find_range(vreg);
904 if (!range)
1b5b1968 905 return -EINVAL;
e92a4047 906
1b5b1968 907 return spmi_hw_selector_to_sw(vreg, voltage_sel, range);
e92a4047
SB		 908}
909
42ba89c8
JH		 910static int spmi_regulator_ftsmps426_get_voltage(struct regulator_dev *rdev)
911{
912 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
913 const struct spmi_voltage_range *range;
914 u8 buf[2];
915 int uV;
916
917 spmi_vreg_read(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2);
918
919 uV = (((unsigned int)buf[1] << 8) | (unsigned int)buf[0]) * 1000;
920 range = vreg->set_points->range;
921
922 return (uV - range->set_point_min_uV) / range->step_uV;
923}
924
1b5b1968
SB		 925static int spmi_regulator_single_map_voltage(struct regulator_dev *rdev,
926 int min_uV, int max_uV)
e92a4047
SB		 927{
928 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
e92a4047 929
1b5b1968
SB		 930 return spmi_regulator_select_voltage(vreg, min_uV, max_uV);
931}
932
933static int spmi_regulator_single_range_set_voltage(struct regulator_dev *rdev,
934 unsigned selector)
935{
936 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
937 u8 sel = selector;
e92a4047
SB		 938
939 /*
940 * Certain types of regulators do not have a range select register so
941 * only voltage set register needs to be written.
942 */
943 return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &sel, 1);
944}
945
946static int spmi_regulator_single_range_get_voltage(struct regulator_dev *rdev)
947{
948 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1b5b1968
SB		 949 u8 selector;
950 int ret;
e92a4047 951
1b5b1968
SB		 952 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &selector, 1);
953 if (ret)
954 return ret;
e92a4047 955
1b5b1968 956 return selector;
e92a4047
SB		 957}
958
959static int spmi_regulator_ult_lo_smps_set_voltage(struct regulator_dev *rdev,
1b5b1968 960 unsigned selector)
e92a4047
SB		 961{
962 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
963 int ret;
964 u8 range_sel, voltage_sel;
965
1b5b1968 966 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
e92a4047
SB		 967 if (ret)
968 return ret;
969
970 /*
971 * Calculate VSET based on range
972 * In case of range 0: voltage_sel is a 7 bit value, can be written
973 * witout any modification.
974 * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to
975 * [011].
976 */
977 if (range_sel == 1)
978 voltage_sel |= ULT_SMPS_RANGE_SPLIT;
979
0f94bffa 980 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_VOLTAGE_SET,
1b5b1968 981 voltage_sel, 0xff);
e92a4047
SB		 982}
983
984static int spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev *rdev)
985{
986 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
987 const struct spmi_voltage_range *range;
988 u8 voltage_sel;
989
990 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1);
991
992 range = spmi_regulator_find_range(vreg);
993 if (!range)
1b5b1968 994 return -EINVAL;
e92a4047
SB		 995
996 if (range->range_sel == 1)
997 voltage_sel &= ~ULT_SMPS_RANGE_SPLIT;
998
1b5b1968 999 return spmi_hw_selector_to_sw(vreg, voltage_sel, range);
e92a4047
SB		 1000}
1001
1002static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev,
1003 unsigned selector)
1004{
1005 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1006 int uV = 0;
1007 int i;
1008
1009 if (selector >= vreg->set_points->n_voltages)
1010 return 0;
1011
1012 for (i = 0; i < vreg->set_points->count; i++) {
9b2dfee3 1013 if (selector < vreg->set_points->range[i].n_voltages) {
e92a4047
SB		 1014 uV = selector * vreg->set_points->range[i].step_uV
1015 + vreg->set_points->range[i].set_point_min_uV;
1016 break;
9b2dfee3 1017 }
e92a4047
SB		 1018
1019 selector -= vreg->set_points->range[i].n_voltages;
1020 }
1021
1022 return uV;
1023}
1024
1025static int
1026spmi_regulator_common_set_bypass(struct regulator_dev *rdev, bool enable)
1027{
1028 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1029 u8 mask = SPMI_COMMON_MODE_BYPASS_MASK;
1030 u8 val = 0;
1031
1032 if (enable)
1033 val = mask;
1034
1035 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
1036}
1037
1038static int
1039spmi_regulator_common_get_bypass(struct regulator_dev *rdev, bool *enable)
1040{
1041 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1042 u8 val;
1043 int ret;
1044
1045 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &val, 1);
1046 *enable = val & SPMI_COMMON_MODE_BYPASS_MASK;
1047
1048 return ret;
1049}
1050
1051static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev)
1052{
1053 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1054 u8 reg;
1055
1056 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &reg, 1);
1057
ba576a62 1058 reg &= SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK;
e92a4047 1059
ba576a62
JH		 1060 switch (reg) {
1061 case SPMI_COMMON_MODE_HPM_MASK:
1062 return REGULATOR_MODE_NORMAL;
1063 case SPMI_COMMON_MODE_AUTO_MASK:
e2adfacd 1064 return REGULATOR_MODE_FAST;
ba576a62
JH		 1065 default:
1066 return REGULATOR_MODE_IDLE;
1067 }
e92a4047
SB		 1068}
1069
42ba89c8
JH		 1070static unsigned int spmi_regulator_ftsmps426_get_mode(struct regulator_dev *rdev)
1071{
1072 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1073 u8 reg;
1074
1075 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &reg, 1);
1076
1077 switch (reg) {
1078 case SPMI_FTSMPS426_MODE_HPM_MASK:
1079 return REGULATOR_MODE_NORMAL;
1080 case SPMI_FTSMPS426_MODE_AUTO_MASK:
1081 return REGULATOR_MODE_FAST;
1082 default:
1083 return REGULATOR_MODE_IDLE;
1084 }
1085}
1086
27850254
IC		 1087static unsigned int spmi_regulator_hfsmps_get_mode(struct regulator_dev *rdev)
1088{
1089 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1090 u8 reg;
1091
1092 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &reg, 1);
1093
1094 switch (reg) {
1095 case SPMI_HFSMPS_MODE_HPM_MASK:
1096 return REGULATOR_MODE_NORMAL;
1097 case SPMI_HFSMPS_MODE_AUTO_MASK:
1098 return REGULATOR_MODE_FAST;
1099 default:
1100 return REGULATOR_MODE_IDLE;
1101 }
1102}
1103
e92a4047
SB		 1104static int
1105spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode)
1106{
1107 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
e2adfacd 1108 u8 mask = SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK;
ba576a62 1109 u8 val;
e92a4047 1110
ba576a62
JH		 1111 switch (mode) {
1112 case REGULATOR_MODE_NORMAL:
e2adfacd 1113 val = SPMI_COMMON_MODE_HPM_MASK;
ba576a62
JH		 1114 break;
1115 case REGULATOR_MODE_FAST:
e2adfacd 1116 val = SPMI_COMMON_MODE_AUTO_MASK;
ba576a62
JH		 1117 break;
1118 default:
1119 val = 0;
1120 break;
1121 }
e92a4047
SB		 1122
1123 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
1124}
1125
42ba89c8
JH		 1126static int
1127spmi_regulator_ftsmps426_set_mode(struct regulator_dev *rdev, unsigned int mode)
1128{
1129 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1130 u8 mask = SPMI_FTSMPS426_MODE_MASK;
1131 u8 val;
1132
1133 switch (mode) {
1134 case REGULATOR_MODE_NORMAL:
1135 val = SPMI_FTSMPS426_MODE_HPM_MASK;
1136 break;
1137 case REGULATOR_MODE_FAST:
1138 val = SPMI_FTSMPS426_MODE_AUTO_MASK;
1139 break;
1140 case REGULATOR_MODE_IDLE:
1141 val = SPMI_FTSMPS426_MODE_LPM_MASK;
1142 break;
1143 default:
1144 return -EINVAL;
1145 }
1146
1147 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
1148}
1149
27850254
IC		 1150static int
1151spmi_regulator_hfsmps_set_mode(struct regulator_dev *rdev, unsigned int mode)
1152{
1153 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1154 u8 mask = SPMI_HFSMPS_MODE_MASK;
1155 u8 val;
1156
1157 switch (mode) {
1158 case REGULATOR_MODE_NORMAL:
1159 val = SPMI_HFSMPS_MODE_HPM_MASK;
1160 break;
1161 case REGULATOR_MODE_FAST:
1162 val = SPMI_HFSMPS_MODE_AUTO_MASK;
1163 break;
1164 case REGULATOR_MODE_IDLE:
1165 val = SPMI_HFSMPS_MODE_LPM_MASK;
1166 break;
1167 default:
1168 return -EINVAL;
1169 }
1170
1171 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
1172}
1173
e92a4047
SB		 1174static int
1175spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA)
1176{
1177 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1178 unsigned int mode;
1179
1180 if (load_uA >= vreg->hpm_min_load)
1181 mode = REGULATOR_MODE_NORMAL;
1182 else
1183 mode = REGULATOR_MODE_IDLE;
1184
1185 return spmi_regulator_common_set_mode(rdev, mode);
1186}
1187
1188static int spmi_regulator_common_set_pull_down(struct regulator_dev *rdev)
1189{
1190 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1191 unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK;
1192
1193 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_PULL_DOWN,
1194 mask, mask);
1195}
1196
27850254
IC		 1197static int spmi_regulator_hfsmps_set_pull_down(struct regulator_dev *rdev)
1198{
1199 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1200 unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK;
1201
1202 return spmi_vreg_update_bits(vreg, SPMI_HFSMPS_REG_PULL_DOWN,
1203 mask, mask);
1204}
1205
e92a4047
SB		 1206static int spmi_regulator_common_set_soft_start(struct regulator_dev *rdev)
1207{
1208 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1209 unsigned int mask = SPMI_LDO_SOFT_START_ENABLE_MASK;
1210
1211 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_SOFT_START,
1212 mask, mask);
1213}
1214
1215static int spmi_regulator_set_ilim(struct regulator_dev *rdev, int ilim_uA)
1216{
1217 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1218 enum spmi_regulator_logical_type type = vreg->logical_type;
1219 unsigned int current_reg;
1220 u8 reg;
1221 u8 mask = SPMI_BOOST_CURRENT_LIMIT_MASK |
1222 SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK;
1223 int max = (SPMI_BOOST_CURRENT_LIMIT_MASK + 1) * 500;
1224
1225 if (type == SPMI_REGULATOR_LOGICAL_TYPE_BOOST)
1226 current_reg = SPMI_BOOST_REG_CURRENT_LIMIT;
1227 else
1228 current_reg = SPMI_BOOST_BYP_REG_CURRENT_LIMIT;
1229
1230 if (ilim_uA > max || ilim_uA <= 0)
1231 return -EINVAL;
1232
1233 reg = (ilim_uA - 1) / 500;
1234 reg |= SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK;
1235
1236 return spmi_vreg_update_bits(vreg, current_reg, reg, mask);
1237}
1238
1239static int spmi_regulator_vs_clear_ocp(struct spmi_regulator *vreg)
1240{
1241 int ret;
1242
1243 ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE,
1244 SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK);
1245
1246 vreg->vs_enable_time = ktime_get();
1247
1248 ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE,
1249 SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK);
1250
1251 return ret;
1252}
1253
1254static void spmi_regulator_vs_ocp_work(struct work_struct *work)
1255{
1256 struct delayed_work *dwork = to_delayed_work(work);
1257 struct spmi_regulator *vreg
1258 = container_of(dwork, struct spmi_regulator, ocp_work);
1259
1260 spmi_regulator_vs_clear_ocp(vreg);
1261}
1262
1263static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data)
1264{
1265 struct spmi_regulator *vreg = data;
1266 ktime_t ocp_irq_time;
1267 s64 ocp_trigger_delay_us;
1268
1269 ocp_irq_time = ktime_get();
1270 ocp_trigger_delay_us = ktime_us_delta(ocp_irq_time,
1271 vreg->vs_enable_time);
1272
1273 /*
1274 * Reset the OCP count if there is a large delay between switch enable
1275 * and when OCP triggers. This is indicative of a hotplug event as
1276 * opposed to a fault.
1277 */
1278 if (ocp_trigger_delay_us > SPMI_VS_OCP_FAULT_DELAY_US)
1279 vreg->ocp_count = 0;
1280
1281 /* Wait for switch output to settle back to 0 V after OCP triggered. */
1282 udelay(SPMI_VS_OCP_FALL_DELAY_US);
1283
1284 vreg->ocp_count++;
1285
1286 if (vreg->ocp_count == 1) {
1287 /* Immediately clear the over current condition. */
1288 spmi_regulator_vs_clear_ocp(vreg);
1289 } else if (vreg->ocp_count <= vreg->ocp_max_retries) {
1290 /* Schedule the over current clear task to run later. */
1291 schedule_delayed_work(&vreg->ocp_work,
1292 msecs_to_jiffies(vreg->ocp_retry_delay_ms) + 1);
1293 } else {
1294 dev_err(vreg->dev,
1295 "OCP triggered %d times; no further retries\n",
1296 vreg->ocp_count);
1297 }
1298
1299 return IRQ_HANDLED;
1300}
1301
0caecaa8
IL		 1302#define SAW3_VCTL_DATA_MASK 0xFF
1303#define SAW3_VCTL_CLEAR_MASK 0x700FF
1304#define SAW3_AVS_CTL_EN_MASK 0x1
1305#define SAW3_AVS_CTL_TGGL_MASK 0x8000000
1306#define SAW3_AVS_CTL_CLEAR_MASK 0x7efc00
1307
9689ca0a 1308static struct regmap *saw_regmap;
0caecaa8
IL		 1309
1310static void spmi_saw_set_vdd(void *data)
1311{
1312 u32 vctl, data3, avs_ctl, pmic_sts;
1313 bool avs_enabled = false;
1314 unsigned long timeout;
1315 u8 voltage_sel = *(u8 *)data;
1316
1317 regmap_read(saw_regmap, SAW3_AVS_CTL, &avs_ctl);
1318 regmap_read(saw_regmap, SAW3_VCTL, &vctl);
1319 regmap_read(saw_regmap, SAW3_SPM_PMIC_DATA_3, &data3);
1320
1321 /* select the band */
1322 vctl &= ~SAW3_VCTL_CLEAR_MASK;
1323 vctl |= (u32)voltage_sel;
1324
1325 data3 &= ~SAW3_VCTL_CLEAR_MASK;
1326 data3 |= (u32)voltage_sel;
1327
1328 /* If AVS is enabled, switch it off during the voltage change */
1329 avs_enabled = SAW3_AVS_CTL_EN_MASK & avs_ctl;
1330 if (avs_enabled) {
1331 avs_ctl &= ~SAW3_AVS_CTL_TGGL_MASK;
1332 regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl);
1333 }
1334
1335 regmap_write(saw_regmap, SAW3_RST, 1);
1336 regmap_write(saw_regmap, SAW3_VCTL, vctl);
1337 regmap_write(saw_regmap, SAW3_SPM_PMIC_DATA_3, data3);
1338
1339 timeout = jiffies + usecs_to_jiffies(100);
1340 do {
1341 regmap_read(saw_regmap, SAW3_PMIC_STS, &pmic_sts);
1342 pmic_sts &= SAW3_VCTL_DATA_MASK;
1343 if (pmic_sts == (u32)voltage_sel)
1344 break;
1345
1346 cpu_relax();
1347
1348 } while (time_before(jiffies, timeout));
1349
1350 /* After successful voltage change, switch the AVS back on */
1351 if (avs_enabled) {
1352 pmic_sts &= 0x3f;
1353 avs_ctl &= ~SAW3_AVS_CTL_CLEAR_MASK;
1354 avs_ctl |= ((pmic_sts - 4) << 10);
1355 avs_ctl |= (pmic_sts << 17);
1356 avs_ctl |= SAW3_AVS_CTL_TGGL_MASK;
1357 regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl);
1358 }
1359}
1360
1361static int
1362spmi_regulator_saw_set_voltage(struct regulator_dev *rdev, unsigned selector)
1363{
1364 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1365 int ret;
1366 u8 range_sel, voltage_sel;
1367
1368 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
1369 if (ret)
1370 return ret;
1371
1372 if (0 != range_sel) {
1373 dev_dbg(&rdev->dev, "range_sel = %02X voltage_sel = %02X", \
1374 range_sel, voltage_sel);
1375 return -EINVAL;
1376 }
1377
1378 /* Always do the SAW register writes on the first CPU */
1379 return smp_call_function_single(0, spmi_saw_set_vdd, \
1380 &voltage_sel, true);
1381}
1382
1383static struct regulator_ops spmi_saw_ops = {};
1384
3b619e3e 1385static const struct regulator_ops spmi_smps_ops = {
9d485332
AL		 1386 .enable = regulator_enable_regmap,
1387 .disable = regulator_disable_regmap,
1388 .is_enabled = regulator_is_enabled_regmap,
1b5b1968 1389 .set_voltage_sel = spmi_regulator_common_set_voltage,
2cf7b99c 1390 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1b5b1968
SB		 1391 .get_voltage_sel = spmi_regulator_common_get_voltage,
1392 .map_voltage = spmi_regulator_common_map_voltage,
e92a4047
SB		 1393 .list_voltage = spmi_regulator_common_list_voltage,
1394 .set_mode = spmi_regulator_common_set_mode,
1395 .get_mode = spmi_regulator_common_get_mode,
1396 .set_load = spmi_regulator_common_set_load,
1397 .set_pull_down = spmi_regulator_common_set_pull_down,
1398};
1399
3b619e3e 1400static const struct regulator_ops spmi_ldo_ops = {
9d485332
AL		 1401 .enable = regulator_enable_regmap,
1402 .disable = regulator_disable_regmap,
1403 .is_enabled = regulator_is_enabled_regmap,
1b5b1968
SB		 1404 .set_voltage_sel = spmi_regulator_common_set_voltage,
1405 .get_voltage_sel = spmi_regulator_common_get_voltage,
1406 .map_voltage = spmi_regulator_common_map_voltage,
e92a4047
SB		 1407 .list_voltage = spmi_regulator_common_list_voltage,
1408 .set_mode = spmi_regulator_common_set_mode,
1409 .get_mode = spmi_regulator_common_get_mode,
1410 .set_load = spmi_regulator_common_set_load,
1411 .set_bypass = spmi_regulator_common_set_bypass,
1412 .get_bypass = spmi_regulator_common_get_bypass,
1413 .set_pull_down = spmi_regulator_common_set_pull_down,
1414 .set_soft_start = spmi_regulator_common_set_soft_start,
1415};
1416
3b619e3e 1417static const struct regulator_ops spmi_ln_ldo_ops = {
9d485332
AL		 1418 .enable = regulator_enable_regmap,
1419 .disable = regulator_disable_regmap,
1420 .is_enabled = regulator_is_enabled_regmap,
1b5b1968
SB		 1421 .set_voltage_sel = spmi_regulator_common_set_voltage,
1422 .get_voltage_sel = spmi_regulator_common_get_voltage,
1423 .map_voltage = spmi_regulator_common_map_voltage,
e92a4047
SB		 1424 .list_voltage = spmi_regulator_common_list_voltage,
1425 .set_bypass = spmi_regulator_common_set_bypass,
1426 .get_bypass = spmi_regulator_common_get_bypass,
1427};
1428
3b619e3e 1429static const struct regulator_ops spmi_vs_ops = {
e92a4047 1430 .enable = spmi_regulator_vs_enable,
9d485332
AL		 1431 .disable = regulator_disable_regmap,
1432 .is_enabled = regulator_is_enabled_regmap,
e92a4047
SB		 1433 .set_pull_down = spmi_regulator_common_set_pull_down,
1434 .set_soft_start = spmi_regulator_common_set_soft_start,
e2adfacd 1435 .set_over_current_protection = spmi_regulator_vs_ocp,
919163f6
SB		 1436 .set_mode = spmi_regulator_common_set_mode,
1437 .get_mode = spmi_regulator_common_get_mode,
e92a4047
SB		 1438};
1439
3b619e3e 1440static const struct regulator_ops spmi_boost_ops = {
9d485332
AL		 1441 .enable = regulator_enable_regmap,
1442 .disable = regulator_disable_regmap,
1443 .is_enabled = regulator_is_enabled_regmap,
1b5b1968
SB		 1444 .set_voltage_sel = spmi_regulator_single_range_set_voltage,
1445 .get_voltage_sel = spmi_regulator_single_range_get_voltage,
1446 .map_voltage = spmi_regulator_single_map_voltage,
e92a4047
SB		 1447 .list_voltage = spmi_regulator_common_list_voltage,
1448 .set_input_current_limit = spmi_regulator_set_ilim,
1449};
1450
3b619e3e 1451static const struct regulator_ops spmi_ftsmps_ops = {
9d485332
AL		 1452 .enable = regulator_enable_regmap,
1453 .disable = regulator_disable_regmap,
1454 .is_enabled = regulator_is_enabled_regmap,
1b5b1968 1455 .set_voltage_sel = spmi_regulator_common_set_voltage,
e92a4047 1456 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1b5b1968
SB		 1457 .get_voltage_sel = spmi_regulator_common_get_voltage,
1458 .map_voltage = spmi_regulator_common_map_voltage,
e92a4047
SB		 1459 .list_voltage = spmi_regulator_common_list_voltage,
1460 .set_mode = spmi_regulator_common_set_mode,
1461 .get_mode = spmi_regulator_common_get_mode,
1462 .set_load = spmi_regulator_common_set_load,
1463 .set_pull_down = spmi_regulator_common_set_pull_down,
1464};
1465
3b619e3e 1466static const struct regulator_ops spmi_ult_lo_smps_ops = {
9d485332
AL		 1467 .enable = regulator_enable_regmap,
1468 .disable = regulator_disable_regmap,
1469 .is_enabled = regulator_is_enabled_regmap,
1b5b1968 1470 .set_voltage_sel = spmi_regulator_ult_lo_smps_set_voltage,
2cf7b99c 1471 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1b5b1968 1472 .get_voltage_sel = spmi_regulator_ult_lo_smps_get_voltage,
e92a4047
SB		 1473 .list_voltage = spmi_regulator_common_list_voltage,
1474 .set_mode = spmi_regulator_common_set_mode,
1475 .get_mode = spmi_regulator_common_get_mode,
1476 .set_load = spmi_regulator_common_set_load,
1477 .set_pull_down = spmi_regulator_common_set_pull_down,
1478};
1479
3b619e3e 1480static const struct regulator_ops spmi_ult_ho_smps_ops = {
9d485332
AL		 1481 .enable = regulator_enable_regmap,
1482 .disable = regulator_disable_regmap,
1483 .is_enabled = regulator_is_enabled_regmap,
1b5b1968 1484 .set_voltage_sel = spmi_regulator_single_range_set_voltage,
2cf7b99c 1485 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1b5b1968
SB		 1486 .get_voltage_sel = spmi_regulator_single_range_get_voltage,
1487 .map_voltage = spmi_regulator_single_map_voltage,
e92a4047
SB		 1488 .list_voltage = spmi_regulator_common_list_voltage,
1489 .set_mode = spmi_regulator_common_set_mode,
1490 .get_mode = spmi_regulator_common_get_mode,
1491 .set_load = spmi_regulator_common_set_load,
1492 .set_pull_down = spmi_regulator_common_set_pull_down,
1493};
1494
3b619e3e 1495static const struct regulator_ops spmi_ult_ldo_ops = {
9d485332
AL		 1496 .enable = regulator_enable_regmap,
1497 .disable = regulator_disable_regmap,
1498 .is_enabled = regulator_is_enabled_regmap,
1b5b1968
SB		 1499 .set_voltage_sel = spmi_regulator_single_range_set_voltage,
1500 .get_voltage_sel = spmi_regulator_single_range_get_voltage,
1501 .map_voltage = spmi_regulator_single_map_voltage,
e92a4047
SB		 1502 .list_voltage = spmi_regulator_common_list_voltage,
1503 .set_mode = spmi_regulator_common_set_mode,
1504 .get_mode = spmi_regulator_common_get_mode,
1505 .set_load = spmi_regulator_common_set_load,
1506 .set_bypass = spmi_regulator_common_set_bypass,
1507 .get_bypass = spmi_regulator_common_get_bypass,
1508 .set_pull_down = spmi_regulator_common_set_pull_down,
1509 .set_soft_start = spmi_regulator_common_set_soft_start,
1510};
1511
3b619e3e 1512static const struct regulator_ops spmi_ftsmps426_ops = {
42ba89c8
JH		 1513 .enable = regulator_enable_regmap,
1514 .disable = regulator_disable_regmap,
1515 .is_enabled = regulator_is_enabled_regmap,
1516 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage,
1517 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1518 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage,
1519 .map_voltage = spmi_regulator_single_map_voltage,
1520 .list_voltage = spmi_regulator_common_list_voltage,
1521 .set_mode = spmi_regulator_ftsmps426_set_mode,
1522 .get_mode = spmi_regulator_ftsmps426_get_mode,
1523 .set_load = spmi_regulator_common_set_load,
1524 .set_pull_down = spmi_regulator_common_set_pull_down,
1525};
1526
3b619e3e 1527static const struct regulator_ops spmi_hfs430_ops = {
0211f68e
JR		 1528 .enable = regulator_enable_regmap,
1529 .disable = regulator_disable_regmap,
1530 .is_enabled = regulator_is_enabled_regmap,
1531 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage,
1532 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1533 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage,
1534 .map_voltage = spmi_regulator_single_map_voltage,
1535 .list_voltage = spmi_regulator_common_list_voltage,
1536 .set_mode = spmi_regulator_ftsmps426_set_mode,
1537 .get_mode = spmi_regulator_ftsmps426_get_mode,
1538};
1539
27850254
IC		 1540static const struct regulator_ops spmi_hfsmps_ops = {
1541 .enable = regulator_enable_regmap,
1542 .disable = regulator_disable_regmap,
1543 .is_enabled = regulator_is_enabled_regmap,
1544 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage,
1545 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1546 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage,
1547 .map_voltage = spmi_regulator_single_map_voltage,
1548 .list_voltage = spmi_regulator_common_list_voltage,
1549 .set_mode = spmi_regulator_hfsmps_set_mode,
1550 .get_mode = spmi_regulator_hfsmps_get_mode,
1551 .set_load = spmi_regulator_common_set_load,
1552 .set_pull_down = spmi_regulator_hfsmps_set_pull_down,
1553};
1554
e92a4047
SB		 1555/* Maximum possible digital major revision value */
1556#define INF 0xFF
1557
1558static const struct spmi_regulator_mapping supported_regulators[] = {
1559 /* type subtype dig_min dig_max ltype ops setpoints hpm_min */
3d04ae8e 1560 SPMI_VREG(LDO, HT_P600, 0, INF, HFS430, hfs430, ht_p600, 10000),
00f6ebbd 1561 SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000),
e92a4047 1562 SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
27850254
IC		 1563 SPMI_VREG(BUCK, HFS430, 0, 3, HFS430, hfs430, hfs430, 10000),
1564 SPMI_VREG(BUCK, HFSMPS_510, 4, INF, HFSMPS, hfsmps, hfs430, 100000),
e92a4047
SB		 1565 SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000),
1566 SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000),
1567 SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000),
1568 SPMI_VREG(LDO, N600, 1, INF, LDO, ldo, nldo3, 10000),
1569 SPMI_VREG(LDO, N1200, 1, INF, LDO, ldo, nldo3, 10000),
1570 SPMI_VREG(LDO, N600_ST, 0, 0, LDO, ldo, nldo2, 10000),
1571 SPMI_VREG(LDO, N1200_ST, 0, 0, LDO, ldo, nldo2, 10000),
1572 SPMI_VREG(LDO, N600_ST, 1, INF, LDO, ldo, nldo3, 10000),
1573 SPMI_VREG(LDO, N1200_ST, 1, INF, LDO, ldo, nldo3, 10000),
1574 SPMI_VREG(LDO, P50, 0, INF, LDO, ldo, pldo, 5000),
1575 SPMI_VREG(LDO, P150, 0, INF, LDO, ldo, pldo, 10000),
1576 SPMI_VREG(LDO, P300, 0, INF, LDO, ldo, pldo, 10000),
1577 SPMI_VREG(LDO, P600, 0, INF, LDO, ldo, pldo, 10000),
1578 SPMI_VREG(LDO, P1200, 0, INF, LDO, ldo, pldo, 10000),
1579 SPMI_VREG(LDO, LN, 0, INF, LN_LDO, ln_ldo, ln_ldo, 0),
1580 SPMI_VREG(LDO, LV_P50, 0, INF, LDO, ldo, pldo, 5000),
1581 SPMI_VREG(LDO, LV_P150, 0, INF, LDO, ldo, pldo, 10000),
1582 SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000),
1583 SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000),
1584 SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000),
328816c2
ADR		 1585 SPMI_VREG(LDO, HT_N300_ST, 0, INF, FTSMPS426, ftsmps426,
1586 ht_nldo, 30000),
1587 SPMI_VREG(LDO, HT_N600_ST, 0, INF, FTSMPS426, ftsmps426,
1588 ht_nldo, 30000),
1589 SPMI_VREG(LDO, HT_N1200_ST, 0, INF, FTSMPS426, ftsmps426,
1590 ht_nldo, 30000),
1591 SPMI_VREG(LDO, HT_LVP150, 0, INF, FTSMPS426, ftsmps426,
1592 ht_lvpldo, 10000),
1593 SPMI_VREG(LDO, HT_LVP300, 0, INF, FTSMPS426, ftsmps426,
1594 ht_lvpldo, 10000),
1595 SPMI_VREG(LDO, L660_N300_ST, 0, INF, FTSMPS426, ftsmps426,
1596 nldo660, 10000),
1597 SPMI_VREG(LDO, L660_N600_ST, 0, INF, FTSMPS426, ftsmps426,
1598 nldo660, 10000),
1599 SPMI_VREG(LDO, L660_P50, 0, INF, FTSMPS426, ftsmps426,
1600 pldo660, 10000),
1601 SPMI_VREG(LDO, L660_P150, 0, INF, FTSMPS426, ftsmps426,
1602 pldo660, 10000),
1603 SPMI_VREG(LDO, L660_P600, 0, INF, FTSMPS426, ftsmps426,
1604 pldo660, 10000),
1605 SPMI_VREG(LDO, L660_LVP150, 0, INF, FTSMPS426, ftsmps426,
1606 ht_lvpldo, 10000),
1607 SPMI_VREG(LDO, L660_LVP600, 0, INF, FTSMPS426, ftsmps426,
1608 ht_lvpldo, 10000),
e92a4047
SB		 1609 SPMI_VREG_VS(LV100, 0, INF),
1610 SPMI_VREG_VS(LV300, 0, INF),
1611 SPMI_VREG_VS(MV300, 0, INF),
1612 SPMI_VREG_VS(MV500, 0, INF),
1613 SPMI_VREG_VS(HDMI, 0, INF),
1614 SPMI_VREG_VS(OTG, 0, INF),
1615 SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0),
1616 SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000),
1617 SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000),
42ba89c8 1618 SPMI_VREG(FTS, FTS426_CTL, 0, INF, FTSMPS426, ftsmps426, ftsmps426, 100000),
e92a4047
SB		 1619 SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0),
1620 SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1621 ult_lo_smps, 100000),
1622 SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1623 ult_lo_smps, 100000),
1624 SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1625 ult_lo_smps, 100000),
1626 SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps,
1627 ult_ho_smps, 100000),
1628 SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1629 SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1630 SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1631 SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
438421b0 1632 SPMI_VREG(ULT_LDO, LV_P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
e92a4047
SB		 1633 SPMI_VREG(ULT_LDO, LV_P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1634 SPMI_VREG(ULT_LDO, LV_P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1635 SPMI_VREG(ULT_LDO, LV_P450, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1636 SPMI_VREG(ULT_LDO, P600, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
438421b0 1637 SPMI_VREG(ULT_LDO, P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
e92a4047
SB		 1638 SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1639 SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000),
1640};
1641
1642static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points)
1643{
1644 unsigned int n;
1645 struct spmi_voltage_range *range = points->range;
1646
1647 for (; range < points->range + points->count; range++) {
1648 n = 0;
1649 if (range->set_point_max_uV) {
1650 n = range->set_point_max_uV - range->set_point_min_uV;
419d06a1 1651 n = (n / range->step_uV) + 1;
e92a4047
SB		 1652 }
1653 range->n_voltages = n;
1654 points->n_voltages += n;
1655 }
1656}
1657
1658static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type)
1659{
1660 const struct spmi_regulator_mapping *mapping;
1661 int ret, i;
1662 u32 dig_major_rev;
1663 u8 version[SPMI_COMMON_REG_SUBTYPE - SPMI_COMMON_REG_DIG_MAJOR_REV + 1];
1664 u8 type, subtype;
1665
1666 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_DIG_MAJOR_REV, version,
1667 ARRAY_SIZE(version));
1668 if (ret) {
6ee5c044 1669 dev_dbg(vreg->dev, "could not read version registers\n");
e92a4047
SB		 1670 return ret;
1671 }
1672 dig_major_rev = version[SPMI_COMMON_REG_DIG_MAJOR_REV
1673 - SPMI_COMMON_REG_DIG_MAJOR_REV];
0caecaa8 1674
e92a4047
SB		 1675 if (!force_type) {
1676 type = version[SPMI_COMMON_REG_TYPE -
1677 SPMI_COMMON_REG_DIG_MAJOR_REV];
1678 subtype = version[SPMI_COMMON_REG_SUBTYPE -
1679 SPMI_COMMON_REG_DIG_MAJOR_REV];
1680 } else {
1681 type = force_type >> 8;
1682 subtype = force_type;
1683 }
1684
1685 for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) {
1686 mapping = &supported_regulators[i];
1687 if (mapping->type == type && mapping->subtype == subtype
1688 && mapping->revision_min <= dig_major_rev
1689 && mapping->revision_max >= dig_major_rev)
1690 goto found;
1691 }
1692
1693 dev_err(vreg->dev,
1694 "unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n",
1695 vreg->desc.name, type, subtype, dig_major_rev);
1696
1697 return -ENODEV;
1698
1699found:
1700 vreg->logical_type = mapping->logical_type;
1701 vreg->set_points = mapping->set_points;
1702 vreg->hpm_min_load = mapping->hpm_min_load;
1703 vreg->desc.ops = mapping->ops;
1704
1705 if (mapping->set_points) {
1706 if (!mapping->set_points->n_voltages)
1707 spmi_calculate_num_voltages(mapping->set_points);
1708 vreg->desc.n_voltages = mapping->set_points->n_voltages;
1709 }
1710
1711 return 0;
1712}
1713
2cf7b99c 1714static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg)
e92a4047
SB		 1715{
1716 int ret;
1717 u8 reg = 0;
2cf7b99c 1718 int step, delay, slew_rate, step_delay;
e92a4047
SB		 1719 const struct spmi_voltage_range *range;
1720
1721 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, &reg, 1);
1722 if (ret) {
1723 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret);
1724 return ret;
1725 }
1726
1727 range = spmi_regulator_find_range(vreg);
1728 if (!range)
1729 return -EINVAL;
1730
2cf7b99c
SB		 1731 switch (vreg->logical_type) {
1732 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS:
1733 step_delay = SPMI_FTSMPS_STEP_DELAY;
1734 break;
1735 default:
1736 step_delay = SPMI_DEFAULT_STEP_DELAY;
1737 break;
1738 }
1739
e92a4047
SB		 1740 step = reg & SPMI_FTSMPS_STEP_CTRL_STEP_MASK;
1741 step >>= SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT;
1742
1743 delay = reg & SPMI_FTSMPS_STEP_CTRL_DELAY_MASK;
1744 delay >>= SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT;
1745
1746 /* slew_rate has units of uV/us */
1747 slew_rate = SPMI_FTSMPS_CLOCK_RATE * range->step_uV * (1 << step);
2cf7b99c 1748 slew_rate /= 1000 * (step_delay << delay);
e92a4047
SB		 1749 slew_rate *= SPMI_FTSMPS_STEP_MARGIN_NUM;
1750 slew_rate /= SPMI_FTSMPS_STEP_MARGIN_DEN;
1751
1752 /* Ensure that the slew rate is greater than 0 */
1753 vreg->slew_rate = max(slew_rate, 1);
1754
1755 return ret;
1756}
1757
0211f68e
JR		 1758static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg,
1759 int clock_rate)
42ba89c8
JH		 1760{
1761 int ret;
1762 u8 reg = 0;
1763 int delay, slew_rate;
1764 const struct spmi_voltage_range *range = &vreg->set_points->range[0];
1765
1766 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, &reg, 1);
1767 if (ret) {
1768 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret);
1769 return ret;
1770 }
1771
1772 delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK;
1773 delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT;
1774
1775 /* slew_rate has units of uV/us */
0211f68e 1776 slew_rate = clock_rate * range->step_uV;
42ba89c8
JH		 1777 slew_rate /= 1000 * (SPMI_FTSMPS426_STEP_DELAY << delay);
1778 slew_rate *= SPMI_FTSMPS426_STEP_MARGIN_NUM;
1779 slew_rate /= SPMI_FTSMPS426_STEP_MARGIN_DEN;
1780
1781 /* Ensure that the slew rate is greater than 0 */
1782 vreg->slew_rate = max(slew_rate, 1);
1783
1784 return ret;
1785}
1786
27850254
IC		 1787static int spmi_regulator_init_slew_rate_hfsmps(struct spmi_regulator *vreg)
1788{
1789 int ret;
1790 u8 reg = 0;
1791 int delay;
1792
1793 ret = spmi_vreg_read(vreg, SPMI_HFSMPS_REG_STEP_CTRL, &reg, 1);
1794 if (ret) {
1795 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret);
1796 return ret;
1797 }
1798
1799 delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK;
1800 delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT;
1801
1802 vreg->slew_rate = SPMI_HFSMPS_SLEW_RATE_38p4 >> delay;
1803
1804 return ret;
1805}
1806
e2adfacd
SB		 1807static int spmi_regulator_init_registers(struct spmi_regulator *vreg,
1808 const struct spmi_regulator_init_data *data)
1809{
1810 int ret;
1811 enum spmi_regulator_logical_type type;
1812 u8 ctrl_reg[8], reg, mask;
1813
1814 type = vreg->logical_type;
1815
1816 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
1817 if (ret)
1818 return ret;
1819
1820 /* Set up enable pin control. */
6a1fe83b
AL		 1821 if (!(data->pin_ctrl_enable & SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT)) {
1822 switch (type) {
1823 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
1824 case SPMI_REGULATOR_LOGICAL_TYPE_LDO:
1825 case SPMI_REGULATOR_LOGICAL_TYPE_VS:
1826 ctrl_reg[SPMI_COMMON_IDX_ENABLE] &=
1827 ~SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK;
1828 ctrl_reg[SPMI_COMMON_IDX_ENABLE] |=
1829 data->pin_ctrl_enable & SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK;
1830 break;
1831 default:
1832 break;
1833 }
e2adfacd
SB		 1834 }
1835
1836 /* Set up mode pin control. */
6a1fe83b
AL		 1837 if (!(data->pin_ctrl_hpm & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) {
1838 switch (type) {
1839 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
1840 case SPMI_REGULATOR_LOGICAL_TYPE_LDO:
1841 ctrl_reg[SPMI_COMMON_IDX_MODE] &=
1842 ~SPMI_COMMON_MODE_FOLLOW_ALL_MASK;
1843 ctrl_reg[SPMI_COMMON_IDX_MODE] |=
1844 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_ALL_MASK;
1845 break;
1846 case SPMI_REGULATOR_LOGICAL_TYPE_VS:
1847 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS:
1848 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS:
1849 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO:
1850 ctrl_reg[SPMI_COMMON_IDX_MODE] &=
1851 ~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
1852 ctrl_reg[SPMI_COMMON_IDX_MODE] |=
1853 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
1854 break;
1855 default:
1856 break;
1857 }
e2adfacd
SB		 1858 }
1859
1860 /* Write back any control register values that were modified. */
1861 ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
1862 if (ret)
1863 return ret;
1864
1865 /* Set soft start strength and over current protection for VS. */
1866 if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS) {
1867 if (data->vs_soft_start_strength
1868 != SPMI_VS_SOFT_START_STR_HW_DEFAULT) {
1869 reg = data->vs_soft_start_strength
1870 & SPMI_VS_SOFT_START_SEL_MASK;
1871 mask = SPMI_VS_SOFT_START_SEL_MASK;
1872 return spmi_vreg_update_bits(vreg,
1873 SPMI_VS_REG_SOFT_START,
1874 reg, mask);
1875 }
1876 }
1877
1878 return 0;
1879}
1880
1881static void spmi_regulator_get_dt_config(struct spmi_regulator *vreg,
1882 struct device_node *node, struct spmi_regulator_init_data *data)
1883{
1884 /*
1885 * Initialize configuration parameters to use hardware default in case
1886 * no value is specified via device tree.
1887 */
1888 data->pin_ctrl_enable = SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT;
1889 data->pin_ctrl_hpm = SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT;
1890 data->vs_soft_start_strength = SPMI_VS_SOFT_START_STR_HW_DEFAULT;
1891
1892 /* These bindings are optional, so it is okay if they aren't found. */
1893 of_property_read_u32(node, "qcom,ocp-max-retries",
1894 &vreg->ocp_max_retries);
1895 of_property_read_u32(node, "qcom,ocp-retry-delay",
1896 &vreg->ocp_retry_delay_ms);
1897 of_property_read_u32(node, "qcom,pin-ctrl-enable",
1898 &data->pin_ctrl_enable);
1899 of_property_read_u32(node, "qcom,pin-ctrl-hpm", &data->pin_ctrl_hpm);
1900 of_property_read_u32(node, "qcom,vs-soft-start-strength",
1901 &data->vs_soft_start_strength);
1902}
1903
e92a4047
SB		 1904static unsigned int spmi_regulator_of_map_mode(unsigned int mode)
1905{
e2adfacd 1906 if (mode == 1)
e92a4047 1907 return REGULATOR_MODE_NORMAL;
e2adfacd
SB		 1908 if (mode == 2)
1909 return REGULATOR_MODE_FAST;
e92a4047
SB		 1910
1911 return REGULATOR_MODE_IDLE;
1912}
1913
1914static int spmi_regulator_of_parse(struct device_node *node,
1915 const struct regulator_desc *desc,
1916 struct regulator_config *config)
1917{
e2adfacd 1918 struct spmi_regulator_init_data data = { };
e92a4047
SB		 1919 struct spmi_regulator *vreg = config->driver_data;
1920 struct device *dev = config->dev;
1921 int ret;
1922
e2adfacd
SB		 1923 spmi_regulator_get_dt_config(vreg, node, &data);
1924
1925 if (!vreg->ocp_max_retries)
1926 vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES;
1927 if (!vreg->ocp_retry_delay_ms)
1928 vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS;
1929
1930 ret = spmi_regulator_init_registers(vreg, &data);
1931 if (ret) {
1932 dev_err(dev, "common initialization failed, ret=%d\n", ret);
1933 return ret;
1934 }
e92a4047 1935
2cf7b99c
SB		 1936 switch (vreg->logical_type) {
1937 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS:
1938 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS:
1939 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS:
1940 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
1941 ret = spmi_regulator_init_slew_rate(vreg);
e92a4047
SB		 1942 if (ret)
1943 return ret;
42ba89c8
JH		 1944 break;
1945 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426:
0211f68e
JR		 1946 ret = spmi_regulator_init_slew_rate_ftsmps426(vreg,
1947 SPMI_FTSMPS426_CLOCK_RATE);
1948 if (ret)
1949 return ret;
1950 break;
1951 case SPMI_REGULATOR_LOGICAL_TYPE_HFS430:
1952 ret = spmi_regulator_init_slew_rate_ftsmps426(vreg,
1953 SPMI_HFS430_CLOCK_RATE);
42ba89c8
JH		 1954 if (ret)
1955 return ret;
1956 break;
27850254
IC		 1957 case SPMI_REGULATOR_LOGICAL_TYPE_HFSMPS:
1958 ret = spmi_regulator_init_slew_rate_hfsmps(vreg);
1959 if (ret)
1960 return ret;
1961 break;
2cf7b99c
SB		 1962 default:
1963 break;
e92a4047
SB		 1964 }
1965
1966 if (vreg->logical_type != SPMI_REGULATOR_LOGICAL_TYPE_VS)
1967 vreg->ocp_irq = 0;
1968
1969 if (vreg->ocp_irq) {
1970 ret = devm_request_irq(dev, vreg->ocp_irq,
1971 spmi_regulator_vs_ocp_isr, IRQF_TRIGGER_RISING, "ocp",
1972 vreg);
1973 if (ret < 0) {
1974 dev_err(dev, "failed to request irq %d, ret=%d\n",
1975 vreg->ocp_irq, ret);
1976 return ret;
1977 }
1978
b6688015
MV		 1979 ret = devm_delayed_work_autocancel(dev, &vreg->ocp_work,
1980 spmi_regulator_vs_ocp_work);
1981 if (ret)
1982 return ret;
e92a4047
SB		 1983 }
1984
1985 return 0;
1986}
1987
1988static const struct spmi_regulator_data pm8941_regulators[] = {
1989 { "s1", 0x1400, "vdd_s1", },
1990 { "s2", 0x1700, "vdd_s2", },
1991 { "s3", 0x1a00, "vdd_s3", },
c333dfe8 1992 { "s4", 0xa000, },
e92a4047
SB		 1993 { "l1", 0x4000, "vdd_l1_l3", },
1994 { "l2", 0x4100, "vdd_l2_lvs_1_2_3", },
1995 { "l3", 0x4200, "vdd_l1_l3", },
1996 { "l4", 0x4300, "vdd_l4_l11", },
1997 { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 },
1998 { "l6", 0x4500, "vdd_l6_l12_l14_l15", },
1999 { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 },
2000 { "l8", 0x4700, "vdd_l8_l16_l18_19", },
2001 { "l9", 0x4800, "vdd_l9_l10_l17_l22", },
2002 { "l10", 0x4900, "vdd_l9_l10_l17_l22", },
2003 { "l11", 0x4a00, "vdd_l4_l11", },
2004 { "l12", 0x4b00, "vdd_l6_l12_l14_l15", },
2005 { "l13", 0x4c00, "vdd_l13_l20_l23_l24", },
2006 { "l14", 0x4d00, "vdd_l6_l12_l14_l15", },
2007 { "l15", 0x4e00, "vdd_l6_l12_l14_l15", },
2008 { "l16", 0x4f00, "vdd_l8_l16_l18_19", },
2009 { "l17", 0x5000, "vdd_l9_l10_l17_l22", },
2010 { "l18", 0x5100, "vdd_l8_l16_l18_19", },
2011 { "l19", 0x5200, "vdd_l8_l16_l18_19", },
2012 { "l20", 0x5300, "vdd_l13_l20_l23_l24", },
2013 { "l21", 0x5400, "vdd_l21", },
2014 { "l22", 0x5500, "vdd_l9_l10_l17_l22", },
2015 { "l23", 0x5600, "vdd_l13_l20_l23_l24", },
2016 { "l24", 0x5700, "vdd_l13_l20_l23_l24", },
2017 { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", },
2018 { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", },
2019 { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", },
93bfe79b
SB		 2020 { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", },
2021 { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", },
e92a4047
SB		 2022 { }
2023};
2024
f8843e5e
DK		 2025static const struct spmi_regulator_data pm8226_regulators[] = {
2026 { "s1", 0x1400, "vdd_s1", },
2027 { "s2", 0x1700, "vdd_s2", },
2028 { "s3", 0x1a00, "vdd_s3", },
2029 { "s4", 0x1d00, "vdd_s4", },
2030 { "s5", 0x2000, "vdd_s5", },
2031 { "l1", 0x4000, "vdd_l1_l2_l4_l5", },
2032 { "l2", 0x4100, "vdd_l1_l2_l4_l5", },
2033 { "l3", 0x4200, "vdd_l3_l24_l26", },
2034 { "l4", 0x4300, "vdd_l1_l2_l4_l5", },
2035 { "l5", 0x4400, "vdd_l1_l2_l4_l5", },
2036 { "l6", 0x4500, "vdd_l6_l7_l8_l9_l27", },
2037 { "l7", 0x4600, "vdd_l6_l7_l8_l9_l27", },
2038 { "l8", 0x4700, "vdd_l6_l7_l8_l9_l27", },
2039 { "l9", 0x4800, "vdd_l6_l7_l8_l9_l27", },
2040 { "l10", 0x4900, "vdd_l10_l11_l13", },
2041 { "l11", 0x4a00, "vdd_l10_l11_l13", },
2042 { "l12", 0x4b00, "vdd_l12_l14", },
2043 { "l13", 0x4c00, "vdd_l10_l11_l13", },
2044 { "l14", 0x4d00, "vdd_l12_l14", },
2045 { "l15", 0x4e00, "vdd_l15_l16_l17_l18", },
2046 { "l16", 0x4f00, "vdd_l15_l16_l17_l18", },
2047 { "l17", 0x5000, "vdd_l15_l16_l17_l18", },
2048 { "l18", 0x5100, "vdd_l15_l16_l17_l18", },
2049 { "l19", 0x5200, "vdd_l19_l20_l21_l22_l23_l28", },
2050 { "l20", 0x5300, "vdd_l19_l20_l21_l22_l23_l28", },
2051 { "l21", 0x5400, "vdd_l19_l20_l21_l22_l23_l28", },
2052 { "l22", 0x5500, "vdd_l19_l20_l21_l22_l23_l28", },
2053 { "l23", 0x5600, "vdd_l19_l20_l21_l22_l23_l28", },
2054 { "l24", 0x5700, "vdd_l3_l24_l26", },
2055 { "l25", 0x5800, "vdd_l25", },
2056 { "l26", 0x5900, "vdd_l3_l24_l26", },
2057 { "l27", 0x5a00, "vdd_l6_l7_l8_l9_l27", },
2058 { "l28", 0x5b00, "vdd_l19_l20_l21_l22_l23_l28", },
2059 { "lvs1", 0x8000, "vdd_lvs1", },
2060 { }
2061};
2062
e92a4047
SB		 2063static const struct spmi_regulator_data pm8841_regulators[] = {
2064 { "s1", 0x1400, "vdd_s1", },
2065 { "s2", 0x1700, "vdd_s2", NULL, 0x1c08 },
2066 { "s3", 0x1a00, "vdd_s3", },
2067 { "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 },
2068 { "s5", 0x2000, "vdd_s5", NULL, 0x1c08 },
2069 { "s6", 0x2300, "vdd_s6", NULL, 0x1c08 },
2070 { "s7", 0x2600, "vdd_s7", NULL, 0x1c08 },
2071 { "s8", 0x2900, "vdd_s8", NULL, 0x1c08 },
2072 { }
2073};
2074
2075static const struct spmi_regulator_data pm8916_regulators[] = {
2076 { "s1", 0x1400, "vdd_s1", },
2077 { "s2", 0x1700, "vdd_s2", },
2078 { "s3", 0x1a00, "vdd_s3", },
2079 { "s4", 0x1d00, "vdd_s4", },
2080 { "l1", 0x4000, "vdd_l1_l3", },
2081 { "l2", 0x4100, "vdd_l2", },
2082 { "l3", 0x4200, "vdd_l1_l3", },
2083 { "l4", 0x4300, "vdd_l4_l5_l6", },
2084 { "l5", 0x4400, "vdd_l4_l5_l6", },
2085 { "l6", 0x4500, "vdd_l4_l5_l6", },
2086 { "l7", 0x4600, "vdd_l7", },
2087 { "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", },
2088 { "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", },
2089 { "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", },
2090 { "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", },
2091 { "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", },
2092 { "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", },
2093 { "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", },
2094 { "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", },
2095 { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", },
2096 { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", },
2097 { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", },
2098 { }
2099};
2100
e4ff1710
ADR		 2101static const struct spmi_regulator_data pm8950_regulators[] = {
2102 { "s1", 0x1400, "vdd_s1", },
2103 { "s2", 0x1700, "vdd_s2", },
2104 { "s3", 0x1a00, "vdd_s3", },
2105 { "s4", 0x1d00, "vdd_s4", },
2106 { "s5", 0x2000, "vdd_s5", },
2107 { "s6", 0x2300, "vdd_s6", },
2108 { "l1", 0x4000, "vdd_l1_l19", },
2109 { "l2", 0x4100, "vdd_l2_l23", },
2110 { "l3", 0x4200, "vdd_l3", },
2111 { "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", },
2112 { "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", },
2113 { "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", },
2114 { "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", },
2115 { "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", },
2116 { "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", },
2117 { "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", },
2118 { "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", },
2119 { "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", },
2120 { "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", },
2121 { "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", },
2122 { "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", },
2123 { "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", },
2124 { "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", },
2125 { "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", },
2126 { "l19", 0x5200, "vdd_l1_l19", },
2127 { "l20", 0x5300, "vdd_l20", },
2128 { "l21", 0x5400, "vdd_l21", },
2129 { "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", },
2130 { "l23", 0x5600, "vdd_l2_l23", },
2131 { }
2132};
2133
50314e55
SB		 2134static const struct spmi_regulator_data pm8994_regulators[] = {
2135 { "s1", 0x1400, "vdd_s1", },
2136 { "s2", 0x1700, "vdd_s2", },
2137 { "s3", 0x1a00, "vdd_s3", },
2138 { "s4", 0x1d00, "vdd_s4", },
2139 { "s5", 0x2000, "vdd_s5", },
2140 { "s6", 0x2300, "vdd_s6", },
2141 { "s7", 0x2600, "vdd_s7", },
2142 { "s8", 0x2900, "vdd_s8", },
2143 { "s9", 0x2c00, "vdd_s9", },
2144 { "s10", 0x2f00, "vdd_s10", },
2145 { "s11", 0x3200, "vdd_s11", },
2146 { "s12", 0x3500, "vdd_s12", },
2147 { "l1", 0x4000, "vdd_l1", },
2148 { "l2", 0x4100, "vdd_l2_l26_l28", },
2149 { "l3", 0x4200, "vdd_l3_l11", },
2150 { "l4", 0x4300, "vdd_l4_l27_l31", },
2151 { "l5", 0x4400, "vdd_l5_l7", },
2152 { "l6", 0x4500, "vdd_l6_l12_l32", },
2153 { "l7", 0x4600, "vdd_l5_l7", },
2154 { "l8", 0x4700, "vdd_l8_l16_l30", },
2155 { "l9", 0x4800, "vdd_l9_l10_l18_l22", },
2156 { "l10", 0x4900, "vdd_l9_l10_l18_l22", },
2157 { "l11", 0x4a00, "vdd_l3_l11", },
2158 { "l12", 0x4b00, "vdd_l6_l12_l32", },
2159 { "l13", 0x4c00, "vdd_l13_l19_l23_l24", },
2160 { "l14", 0x4d00, "vdd_l14_l15", },
2161 { "l15", 0x4e00, "vdd_l14_l15", },
2162 { "l16", 0x4f00, "vdd_l8_l16_l30", },
2163 { "l17", 0x5000, "vdd_l17_l29", },
2164 { "l18", 0x5100, "vdd_l9_l10_l18_l22", },
2165 { "l19", 0x5200, "vdd_l13_l19_l23_l24", },
2166 { "l20", 0x5300, "vdd_l20_l21", },
2167 { "l21", 0x5400, "vdd_l20_l21", },
2168 { "l22", 0x5500, "vdd_l9_l10_l18_l22", },
2169 { "l23", 0x5600, "vdd_l13_l19_l23_l24", },
2170 { "l24", 0x5700, "vdd_l13_l19_l23_l24", },
2171 { "l25", 0x5800, "vdd_l25", },
2172 { "l26", 0x5900, "vdd_l2_l26_l28", },
2173 { "l27", 0x5a00, "vdd_l4_l27_l31", },
2174 { "l28", 0x5b00, "vdd_l2_l26_l28", },
2175 { "l29", 0x5c00, "vdd_l17_l29", },
2176 { "l30", 0x5d00, "vdd_l8_l16_l30", },
2177 { "l31", 0x5e00, "vdd_l4_l27_l31", },
2178 { "l32", 0x5f00, "vdd_l6_l12_l32", },
2179 { "lvs1", 0x8000, "vdd_lvs_1_2", },
2180 { "lvs2", 0x8100, "vdd_lvs_1_2", },
2181 { }
2182};
2183
ca5cd8c9
RN		 2184static const struct spmi_regulator_data pmi8994_regulators[] = {
2185 { "s1", 0x1400, "vdd_s1", },
2186 { "s2", 0x1700, "vdd_s2", },
2187 { "s3", 0x1a00, "vdd_s3", },
2188 { "l1", 0x4000, "vdd_l1", },
37164571 2189 { }
ca5cd8c9
RN		 2190};
2191
0074c447
ADR		 2192static const struct spmi_regulator_data pm660_regulators[] = {
2193 { "s1", 0x1400, "vdd_s1", },
2194 { "s2", 0x1700, "vdd_s2", },
2195 { "s3", 0x1a00, "vdd_s3", },
2196 { "s4", 0x1d00, "vdd_s3", },
2197 { "s5", 0x2000, "vdd_s5", },
2198 { "s6", 0x2300, "vdd_s6", },
2199 { "l1", 0x4000, "vdd_l1_l6_l7", },
2200 { "l2", 0x4100, "vdd_l2_l3", },
2201 { "l3", 0x4200, "vdd_l2_l3", },
2202 /* l4 is unaccessible on PM660 */
2203 { "l5", 0x4400, "vdd_l5", },
2204 { "l6", 0x4500, "vdd_l1_l6_l7", },
2205 { "l7", 0x4600, "vdd_l1_l6_l7", },
2206 { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2207 { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2208 { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2209 { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2210 { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2211 { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2212 { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2213 { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", },
2214 { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", },
2215 { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", },
2216 { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", },
2217 { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", },
2218 { }
2219};
2220
2221static const struct spmi_regulator_data pm660l_regulators[] = {
2222 { "s1", 0x1400, "vdd_s1", },
2223 { "s2", 0x1700, "vdd_s2", },
2224 { "s3", 0x1a00, "vdd_s3", },
2225 { "s4", 0x1d00, "vdd_s4", },
2226 { "s5", 0x2000, "vdd_s5", },
2227 { "l1", 0x4000, "vdd_l1_l9_l10", },
2228 { "l2", 0x4100, "vdd_l2", },
2229 { "l3", 0x4200, "vdd_l3_l5_l7_l8", },
2230 { "l4", 0x4300, "vdd_l4_l6", },
2231 { "l5", 0x4400, "vdd_l3_l5_l7_l8", },
2232 { "l6", 0x4500, "vdd_l4_l6", },
2233 { "l7", 0x4600, "vdd_l3_l5_l7_l8", },
2234 { "l8", 0x4700, "vdd_l3_l5_l7_l8", },
2235 { "l9", 0x4800, "vdd_l1_l9_l10", },
2236 { "l10", 0x4900, "vdd_l1_l9_l10", },
2237 { }
2238};
2239
2240
2e36e140
ADR		 2241static const struct spmi_regulator_data pm8004_regulators[] = {
2242 { "s2", 0x1700, "vdd_s2", },
2243 { "s5", 0x2000, "vdd_s5", },
2244 { }
2245};
2246
42ba89c8
JH		 2247static const struct spmi_regulator_data pm8005_regulators[] = {
2248 { "s1", 0x1400, "vdd_s1", },
2249 { "s2", 0x1700, "vdd_s2", },
2250 { "s3", 0x1a00, "vdd_s3", },
2251 { "s4", 0x1d00, "vdd_s4", },
2252 { }
2253};
2254
34ceb6a6
RM		 2255static const struct spmi_regulator_data pmp8074_regulators[] = {
2256 { "s1", 0x1400, "vdd_s1"},
2257 { "s2", 0x1700, "vdd_s2"},
2258 { "s3", 0x1a00, "vdd_s3"},
2259 { "s4", 0x1d00, "vdd_s4"},
2260 { "s5", 0x2000, "vdd_s5"},
2261 { "l1", 0x4000, "vdd_l1_l2"},
2262 { "l2", 0x4100, "vdd_l1_l2"},
2263 { "l3", 0x4200, "vdd_l3_l8"},
2264 { "l4", 0x4300, "vdd_l4"},
2265 { "l5", 0x4400, "vdd_l5_l6_l15"},
2266 { "l6", 0x4500, "vdd_l5_l6_l15"},
2267 { "l7", 0x4600, "vdd_l7"},
2268 { "l8", 0x4700, "vdd_l3_l8"},
2269 { "l9", 0x4800, "vdd_l9"},
2270 /* l10 is currently unsupported HT_P50 */
2271 { "l11", 0x4a00, "vdd_l10_l11_l12_l13"},
2272 { "l12", 0x4b00, "vdd_l10_l11_l12_l13"},
2273 { "l13", 0x4c00, "vdd_l10_l11_l12_l13"},
2274 { }
2275};
2276
0211f68e
JR		 2277static const struct spmi_regulator_data pms405_regulators[] = {
2278 { "s3", 0x1a00, "vdd_s3"},
2279 { }
2280};
2281
e92a4047 2282static const struct of_device_id qcom_spmi_regulator_match[] = {
2e36e140 2283 { .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators },
42ba89c8 2284 { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators },
f8843e5e 2285 { .compatible = "qcom,pm8226-regulators", .data = &pm8226_regulators },
e92a4047
SB		 2286 { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators },
2287 { .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators },
2288 { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators },
e4ff1710 2289 { .compatible = "qcom,pm8950-regulators", .data = &pm8950_regulators },
50314e55 2290 { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators },
ca5cd8c9 2291 { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators },
0074c447
ADR		 2292 { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators },
2293 { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators },
34ceb6a6 2294 { .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators },
0211f68e 2295 { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators },
e92a4047
SB		 2296 { }
2297};
2298MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match);
2299
2300static int qcom_spmi_regulator_probe(struct platform_device *pdev)
2301{
2302 const struct spmi_regulator_data *reg;
86f4ff7a 2303 const struct spmi_voltage_range *range;
e92a4047
SB		 2304 const struct of_device_id *match;
2305 struct regulator_config config = { };
2306 struct regulator_dev *rdev;
2307 struct spmi_regulator *vreg;
2308 struct regmap *regmap;
2309 const char *name;
2310 struct device *dev = &pdev->dev;
0caecaa8 2311 struct device_node *node = pdev->dev.of_node;
fffe7f52
NC		 2312 struct device_node *syscon, *reg_node;
2313 struct property *reg_prop;
0caecaa8 2314 int ret, lenp;
e92a4047
SB		 2315 struct list_head *vreg_list;
2316
2317 vreg_list = devm_kzalloc(dev, sizeof(*vreg_list), GFP_KERNEL);
2318 if (!vreg_list)
2319 return -ENOMEM;
2320 INIT_LIST_HEAD(vreg_list);
2321 platform_set_drvdata(pdev, vreg_list);
2322
2323 regmap = dev_get_regmap(dev->parent, NULL);
2324 if (!regmap)
2325 return -ENODEV;
2326
2327 match = of_match_device(qcom_spmi_regulator_match, &pdev->dev);
2328 if (!match)
2329 return -ENODEV;
2330
0caecaa8
IL		 2331 if (of_find_property(node, "qcom,saw-reg", &lenp)) {
2332 syscon = of_parse_phandle(node, "qcom,saw-reg", 0);
2333 saw_regmap = syscon_node_to_regmap(syscon);
2334 of_node_put(syscon);
85046a15 2335 if (IS_ERR(saw_regmap))
0caecaa8
IL		 2336 dev_err(dev, "ERROR reading SAW regmap\n");
2337 }
2338
e92a4047 2339 for (reg = match->data; reg->name; reg++) {
0caecaa8 2340
fffe7f52
NC		 2341 if (saw_regmap) {
2342 reg_node = of_get_child_by_name(node, reg->name);
2343 reg_prop = of_find_property(reg_node, "qcom,saw-slave",
2344 &lenp);
2345 of_node_put(reg_node);
2346 if (reg_prop)
2347 continue;
0caecaa8
IL		 2348 }
2349
e92a4047
SB		 2350 vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
2351 if (!vreg)
2352 return -ENOMEM;
2353
2354 vreg->dev = dev;
2355 vreg->base = reg->base;
2356 vreg->regmap = regmap;
e92a4047
SB		 2357 if (reg->ocp) {
2358 vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp);
b6688015
MV		 2359 if (vreg->ocp_irq < 0)
2360 return vreg->ocp_irq;
e92a4047 2361 }
e92a4047
SB		 2362 vreg->desc.id = -1;
2363 vreg->desc.owner = THIS_MODULE;
2364 vreg->desc.type = REGULATOR_VOLTAGE;
9d485332
AL		 2365 vreg->desc.enable_reg = reg->base + SPMI_COMMON_REG_ENABLE;
2366 vreg->desc.enable_mask = SPMI_COMMON_ENABLE_MASK;
2367 vreg->desc.enable_val = SPMI_COMMON_ENABLE;
e92a4047
SB		 2368 vreg->desc.name = name = reg->name;
2369 vreg->desc.supply_name = reg->supply;
2370 vreg->desc.of_match = reg->name;
2371 vreg->desc.of_parse_cb = spmi_regulator_of_parse;
2372 vreg->desc.of_map_mode = spmi_regulator_of_map_mode;
2373
2374 ret = spmi_regulator_match(vreg, reg->force_type);
2375 if (ret)
6ee5c044 2376 continue;
e92a4047 2377
fffe7f52
NC		 2378 if (saw_regmap) {
2379 reg_node = of_get_child_by_name(node, reg->name);
2380 reg_prop = of_find_property(reg_node, "qcom,saw-leader",
2381 &lenp);
2382 of_node_put(reg_node);
2383 if (reg_prop) {
2384 spmi_saw_ops = *(vreg->desc.ops);
2385 spmi_saw_ops.set_voltage_sel =
2386 spmi_regulator_saw_set_voltage;
2387 vreg->desc.ops = &spmi_saw_ops;
2388 }
0caecaa8
IL		 2389 }
2390
b01d1823 2391 if (vreg->set_points && vreg->set_points->count == 1) {
86f4ff7a
JRO		 2392 /* since there is only one range */
2393 range = vreg->set_points->range;
2394 vreg->desc.uV_step = range->step_uV;
2395 }
2396
e92a4047
SB		 2397 config.dev = dev;
2398 config.driver_data = vreg;
9d485332 2399 config.regmap = regmap;
e92a4047
SB		 2400 rdev = devm_regulator_register(dev, &vreg->desc, &config);
2401 if (IS_ERR(rdev)) {
2402 dev_err(dev, "failed to register %s\n", name);
b6688015 2403 return PTR_ERR(rdev);
e92a4047
SB		 2404 }
2405
2406 INIT_LIST_HEAD(&vreg->node);
2407 list_add(&vreg->node, vreg_list);
2408 }
2409
2410 return 0;
e92a4047
SB		 2411}
2412
2413static struct platform_driver qcom_spmi_regulator_driver = {
2414 .driver = {
2415 .name = "qcom-spmi-regulator",
2416 .of_match_table = qcom_spmi_regulator_match,
2417 },
2418 .probe = qcom_spmi_regulator_probe,
e92a4047
SB		 2419};
2420module_platform_driver(qcom_spmi_regulator_driver);
2421
2422MODULE_DESCRIPTION("Qualcomm SPMI PMIC regulator driver");
2423MODULE_LICENSE("GPL v2");
2424MODULE_ALIAS("platform:qcom-spmi-regulator");
Linux 6.x block layer and io_uring tree(s)