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97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
e92a4047 SB |
2 | /* |
3 | * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. | |
e92a4047 SB |
4 | */ |
5 | ||
6 | #include <linux/module.h> | |
7 | #include <linux/delay.h> | |
b6688015 | 8 | #include <linux/devm-helpers.h> |
e92a4047 SB |
9 | #include <linux/err.h> |
10 | #include <linux/kernel.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/bitops.h> | |
13 | #include <linux/slab.h> | |
14 | #include <linux/of.h> | |
15 | #include <linux/of_device.h> | |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/ktime.h> | |
18 | #include <linux/regulator/driver.h> | |
19 | #include <linux/regmap.h> | |
20 | #include <linux/list.h> | |
0caecaa8 IL |
21 | #include <linux/mfd/syscon.h> |
22 | #include <linux/io.h> | |
e92a4047 | 23 | |
e2adfacd SB |
24 | /* Pin control enable input pins. */ |
25 | #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00 | |
26 | #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01 | |
27 | #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02 | |
28 | #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04 | |
29 | #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08 | |
30 | #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10 | |
31 | ||
32 | /* Pin control high power mode input pins. */ | |
33 | #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00 | |
34 | #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01 | |
35 | #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02 | |
36 | #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04 | |
37 | #define SPMI_REGULATOR_PIN_CTRL_HPM_EN3 0x08 | |
38 | #define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10 | |
39 | #define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20 | |
40 | ||
41 | /* | |
42 | * Used with enable parameters to specify that hardware default register values | |
43 | * should be left unaltered. | |
44 | */ | |
45 | #define SPMI_REGULATOR_USE_HW_DEFAULT 2 | |
46 | ||
47 | /* Soft start strength of a voltage switch type regulator */ | |
48 | enum spmi_vs_soft_start_str { | |
49 | SPMI_VS_SOFT_START_STR_0P05_UA = 0, | |
50 | SPMI_VS_SOFT_START_STR_0P25_UA, | |
51 | SPMI_VS_SOFT_START_STR_0P55_UA, | |
52 | SPMI_VS_SOFT_START_STR_0P75_UA, | |
53 | SPMI_VS_SOFT_START_STR_HW_DEFAULT, | |
54 | }; | |
55 | ||
56 | /** | |
57 | * struct spmi_regulator_init_data - spmi-regulator initialization data | |
58 | * @pin_ctrl_enable: Bit mask specifying which hardware pins should be | |
59 | * used to enable the regulator, if any | |
60 | * Value should be an ORing of | |
61 | * SPMI_REGULATOR_PIN_CTRL_ENABLE_* constants. If | |
62 | * the bit specified by | |
63 | * SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is | |
64 | * set, then pin control enable hardware registers | |
65 | * will not be modified. | |
66 | * @pin_ctrl_hpm: Bit mask specifying which hardware pins should be | |
67 | * used to force the regulator into high power | |
68 | * mode, if any | |
69 | * Value should be an ORing of | |
70 | * SPMI_REGULATOR_PIN_CTRL_HPM_* constants. If | |
71 | * the bit specified by | |
72 | * SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is | |
73 | * set, then pin control mode hardware registers | |
74 | * will not be modified. | |
75 | * @vs_soft_start_strength: This parameter sets the soft start strength for | |
76 | * voltage switch type regulators. Its value | |
77 | * should be one of SPMI_VS_SOFT_START_STR_*. If | |
78 | * its value is SPMI_VS_SOFT_START_STR_HW_DEFAULT, | |
79 | * then the soft start strength will be left at its | |
80 | * default hardware value. | |
81 | */ | |
82 | struct spmi_regulator_init_data { | |
83 | unsigned pin_ctrl_enable; | |
84 | unsigned pin_ctrl_hpm; | |
85 | enum spmi_vs_soft_start_str vs_soft_start_strength; | |
86 | }; | |
87 | ||
e92a4047 SB |
88 | /* These types correspond to unique register layouts. */ |
89 | enum spmi_regulator_logical_type { | |
90 | SPMI_REGULATOR_LOGICAL_TYPE_SMPS, | |
91 | SPMI_REGULATOR_LOGICAL_TYPE_LDO, | |
92 | SPMI_REGULATOR_LOGICAL_TYPE_VS, | |
93 | SPMI_REGULATOR_LOGICAL_TYPE_BOOST, | |
94 | SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS, | |
95 | SPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP, | |
96 | SPMI_REGULATOR_LOGICAL_TYPE_LN_LDO, | |
97 | SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS, | |
98 | SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS, | |
99 | SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO, | |
42ba89c8 | 100 | SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426, |
0211f68e | 101 | SPMI_REGULATOR_LOGICAL_TYPE_HFS430, |
0d1cf568 IC |
102 | SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3, |
103 | SPMI_REGULATOR_LOGICAL_TYPE_LDO_510, | |
27850254 | 104 | SPMI_REGULATOR_LOGICAL_TYPE_HFSMPS, |
e92a4047 SB |
105 | }; |
106 | ||
107 | enum spmi_regulator_type { | |
108 | SPMI_REGULATOR_TYPE_BUCK = 0x03, | |
109 | SPMI_REGULATOR_TYPE_LDO = 0x04, | |
110 | SPMI_REGULATOR_TYPE_VS = 0x05, | |
111 | SPMI_REGULATOR_TYPE_BOOST = 0x1b, | |
112 | SPMI_REGULATOR_TYPE_FTS = 0x1c, | |
113 | SPMI_REGULATOR_TYPE_BOOST_BYP = 0x1f, | |
114 | SPMI_REGULATOR_TYPE_ULT_LDO = 0x21, | |
115 | SPMI_REGULATOR_TYPE_ULT_BUCK = 0x22, | |
116 | }; | |
117 | ||
118 | enum spmi_regulator_subtype { | |
119 | SPMI_REGULATOR_SUBTYPE_GP_CTL = 0x08, | |
120 | SPMI_REGULATOR_SUBTYPE_RF_CTL = 0x09, | |
121 | SPMI_REGULATOR_SUBTYPE_N50 = 0x01, | |
122 | SPMI_REGULATOR_SUBTYPE_N150 = 0x02, | |
123 | SPMI_REGULATOR_SUBTYPE_N300 = 0x03, | |
124 | SPMI_REGULATOR_SUBTYPE_N600 = 0x04, | |
125 | SPMI_REGULATOR_SUBTYPE_N1200 = 0x05, | |
126 | SPMI_REGULATOR_SUBTYPE_N600_ST = 0x06, | |
127 | SPMI_REGULATOR_SUBTYPE_N1200_ST = 0x07, | |
128 | SPMI_REGULATOR_SUBTYPE_N900_ST = 0x14, | |
129 | SPMI_REGULATOR_SUBTYPE_N300_ST = 0x15, | |
130 | SPMI_REGULATOR_SUBTYPE_P50 = 0x08, | |
131 | SPMI_REGULATOR_SUBTYPE_P150 = 0x09, | |
132 | SPMI_REGULATOR_SUBTYPE_P300 = 0x0a, | |
133 | SPMI_REGULATOR_SUBTYPE_P600 = 0x0b, | |
134 | SPMI_REGULATOR_SUBTYPE_P1200 = 0x0c, | |
135 | SPMI_REGULATOR_SUBTYPE_LN = 0x10, | |
136 | SPMI_REGULATOR_SUBTYPE_LV_P50 = 0x28, | |
137 | SPMI_REGULATOR_SUBTYPE_LV_P150 = 0x29, | |
138 | SPMI_REGULATOR_SUBTYPE_LV_P300 = 0x2a, | |
139 | SPMI_REGULATOR_SUBTYPE_LV_P600 = 0x2b, | |
140 | SPMI_REGULATOR_SUBTYPE_LV_P1200 = 0x2c, | |
141 | SPMI_REGULATOR_SUBTYPE_LV_P450 = 0x2d, | |
328816c2 ADR |
142 | SPMI_REGULATOR_SUBTYPE_HT_N300_ST = 0x30, |
143 | SPMI_REGULATOR_SUBTYPE_HT_N600_ST = 0x31, | |
144 | SPMI_REGULATOR_SUBTYPE_HT_N1200_ST = 0x32, | |
145 | SPMI_REGULATOR_SUBTYPE_HT_LVP150 = 0x3b, | |
146 | SPMI_REGULATOR_SUBTYPE_HT_LVP300 = 0x3c, | |
147 | SPMI_REGULATOR_SUBTYPE_L660_N300_ST = 0x42, | |
148 | SPMI_REGULATOR_SUBTYPE_L660_N600_ST = 0x43, | |
149 | SPMI_REGULATOR_SUBTYPE_L660_P50 = 0x46, | |
150 | SPMI_REGULATOR_SUBTYPE_L660_P150 = 0x47, | |
151 | SPMI_REGULATOR_SUBTYPE_L660_P600 = 0x49, | |
152 | SPMI_REGULATOR_SUBTYPE_L660_LVP150 = 0x4d, | |
153 | SPMI_REGULATOR_SUBTYPE_L660_LVP600 = 0x4f, | |
e92a4047 SB |
154 | SPMI_REGULATOR_SUBTYPE_LV100 = 0x01, |
155 | SPMI_REGULATOR_SUBTYPE_LV300 = 0x02, | |
156 | SPMI_REGULATOR_SUBTYPE_MV300 = 0x08, | |
157 | SPMI_REGULATOR_SUBTYPE_MV500 = 0x09, | |
158 | SPMI_REGULATOR_SUBTYPE_HDMI = 0x10, | |
159 | SPMI_REGULATOR_SUBTYPE_OTG = 0x11, | |
160 | SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01, | |
161 | SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08, | |
162 | SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09, | |
42ba89c8 | 163 | SPMI_REGULATOR_SUBTYPE_FTS426_CTL = 0x0a, |
e92a4047 SB |
164 | SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01, |
165 | SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d, | |
166 | SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e, | |
167 | SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f, | |
168 | SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10, | |
0211f68e | 169 | SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a, |
00f6ebbd | 170 | SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35, |
3d04ae8e | 171 | SPMI_REGULATOR_SUBTYPE_HT_P600 = 0x3d, |
27850254 | 172 | SPMI_REGULATOR_SUBTYPE_HFSMPS_510 = 0x0a, |
0d1cf568 IC |
173 | SPMI_REGULATOR_SUBTYPE_FTSMPS_510 = 0x0b, |
174 | SPMI_REGULATOR_SUBTYPE_LV_P150_510 = 0x71, | |
175 | SPMI_REGULATOR_SUBTYPE_LV_P300_510 = 0x72, | |
176 | SPMI_REGULATOR_SUBTYPE_LV_P600_510 = 0x73, | |
177 | SPMI_REGULATOR_SUBTYPE_N300_510 = 0x6a, | |
178 | SPMI_REGULATOR_SUBTYPE_N600_510 = 0x6b, | |
179 | SPMI_REGULATOR_SUBTYPE_N1200_510 = 0x6c, | |
180 | SPMI_REGULATOR_SUBTYPE_MV_P50_510 = 0x7a, | |
181 | SPMI_REGULATOR_SUBTYPE_MV_P150_510 = 0x7b, | |
182 | SPMI_REGULATOR_SUBTYPE_MV_P600_510 = 0x7d, | |
e92a4047 SB |
183 | }; |
184 | ||
185 | enum spmi_common_regulator_registers { | |
186 | SPMI_COMMON_REG_DIG_MAJOR_REV = 0x01, | |
187 | SPMI_COMMON_REG_TYPE = 0x04, | |
188 | SPMI_COMMON_REG_SUBTYPE = 0x05, | |
189 | SPMI_COMMON_REG_VOLTAGE_RANGE = 0x40, | |
190 | SPMI_COMMON_REG_VOLTAGE_SET = 0x41, | |
191 | SPMI_COMMON_REG_MODE = 0x45, | |
192 | SPMI_COMMON_REG_ENABLE = 0x46, | |
193 | SPMI_COMMON_REG_PULL_DOWN = 0x48, | |
194 | SPMI_COMMON_REG_SOFT_START = 0x4c, | |
195 | SPMI_COMMON_REG_STEP_CTRL = 0x61, | |
196 | }; | |
197 | ||
42ba89c8 JH |
198 | /* |
199 | * Second common register layout used by newer devices starting with ftsmps426 | |
200 | * Note that some of the registers from the first common layout remain | |
201 | * unchanged and their definition is not duplicated. | |
202 | */ | |
203 | enum spmi_ftsmps426_regulator_registers { | |
204 | SPMI_FTSMPS426_REG_VOLTAGE_LSB = 0x40, | |
205 | SPMI_FTSMPS426_REG_VOLTAGE_MSB = 0x41, | |
206 | SPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 0x68, | |
207 | SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 0x69, | |
208 | }; | |
209 | ||
27850254 IC |
210 | /* |
211 | * Third common register layout | |
212 | */ | |
213 | enum spmi_hfsmps_regulator_registers { | |
214 | SPMI_HFSMPS_REG_STEP_CTRL = 0x3c, | |
215 | SPMI_HFSMPS_REG_PULL_DOWN = 0xa0, | |
216 | }; | |
217 | ||
e92a4047 SB |
218 | enum spmi_vs_registers { |
219 | SPMI_VS_REG_OCP = 0x4a, | |
220 | SPMI_VS_REG_SOFT_START = 0x4c, | |
221 | }; | |
222 | ||
223 | enum spmi_boost_registers { | |
224 | SPMI_BOOST_REG_CURRENT_LIMIT = 0x4a, | |
225 | }; | |
226 | ||
227 | enum spmi_boost_byp_registers { | |
228 | SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b, | |
229 | }; | |
230 | ||
0caecaa8 IL |
231 | enum spmi_saw3_registers { |
232 | SAW3_SECURE = 0x00, | |
233 | SAW3_ID = 0x04, | |
234 | SAW3_SPM_STS = 0x0C, | |
235 | SAW3_AVS_STS = 0x10, | |
236 | SAW3_PMIC_STS = 0x14, | |
237 | SAW3_RST = 0x18, | |
238 | SAW3_VCTL = 0x1C, | |
239 | SAW3_AVS_CTL = 0x20, | |
240 | SAW3_AVS_LIMIT = 0x24, | |
241 | SAW3_AVS_DLY = 0x28, | |
242 | SAW3_AVS_HYSTERESIS = 0x2C, | |
243 | SAW3_SPM_STS2 = 0x38, | |
244 | SAW3_SPM_PMIC_DATA_3 = 0x4C, | |
245 | SAW3_VERSION = 0xFD0, | |
246 | }; | |
247 | ||
e92a4047 SB |
248 | /* Used for indexing into ctrl_reg. These are offets from 0x40 */ |
249 | enum spmi_common_control_register_index { | |
250 | SPMI_COMMON_IDX_VOLTAGE_RANGE = 0, | |
251 | SPMI_COMMON_IDX_VOLTAGE_SET = 1, | |
252 | SPMI_COMMON_IDX_MODE = 5, | |
253 | SPMI_COMMON_IDX_ENABLE = 6, | |
254 | }; | |
255 | ||
256 | /* Common regulator control register layout */ | |
257 | #define SPMI_COMMON_ENABLE_MASK 0x80 | |
258 | #define SPMI_COMMON_ENABLE 0x80 | |
259 | #define SPMI_COMMON_DISABLE 0x00 | |
260 | #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK 0x08 | |
261 | #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK 0x04 | |
262 | #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK 0x02 | |
263 | #define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK 0x01 | |
264 | #define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK 0x0f | |
265 | ||
266 | /* Common regulator mode register layout */ | |
267 | #define SPMI_COMMON_MODE_HPM_MASK 0x80 | |
268 | #define SPMI_COMMON_MODE_AUTO_MASK 0x40 | |
269 | #define SPMI_COMMON_MODE_BYPASS_MASK 0x20 | |
270 | #define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK 0x10 | |
271 | #define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK 0x08 | |
272 | #define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK 0x04 | |
273 | #define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK 0x02 | |
274 | #define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01 | |
275 | #define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f | |
276 | ||
42ba89c8 JH |
277 | #define SPMI_FTSMPS426_MODE_BYPASS_MASK 3 |
278 | #define SPMI_FTSMPS426_MODE_RETENTION_MASK 4 | |
279 | #define SPMI_FTSMPS426_MODE_LPM_MASK 5 | |
280 | #define SPMI_FTSMPS426_MODE_AUTO_MASK 6 | |
281 | #define SPMI_FTSMPS426_MODE_HPM_MASK 7 | |
282 | ||
283 | #define SPMI_FTSMPS426_MODE_MASK 0x07 | |
284 | ||
27850254 IC |
285 | /* Third common regulator mode register values */ |
286 | #define SPMI_HFSMPS_MODE_BYPASS_MASK 2 | |
287 | #define SPMI_HFSMPS_MODE_RETENTION_MASK 3 | |
288 | #define SPMI_HFSMPS_MODE_LPM_MASK 4 | |
289 | #define SPMI_HFSMPS_MODE_AUTO_MASK 6 | |
290 | #define SPMI_HFSMPS_MODE_HPM_MASK 7 | |
291 | ||
292 | #define SPMI_HFSMPS_MODE_MASK 0x07 | |
293 | ||
e92a4047 SB |
294 | /* Common regulator pull down control register layout */ |
295 | #define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80 | |
296 | ||
297 | /* LDO regulator current limit control register layout */ | |
298 | #define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK 0x80 | |
299 | ||
300 | /* LDO regulator soft start control register layout */ | |
301 | #define SPMI_LDO_SOFT_START_ENABLE_MASK 0x80 | |
302 | ||
303 | /* VS regulator over current protection control register layout */ | |
304 | #define SPMI_VS_OCP_OVERRIDE 0x01 | |
305 | #define SPMI_VS_OCP_NO_OVERRIDE 0x00 | |
306 | ||
307 | /* VS regulator soft start control register layout */ | |
308 | #define SPMI_VS_SOFT_START_ENABLE_MASK 0x80 | |
309 | #define SPMI_VS_SOFT_START_SEL_MASK 0x03 | |
310 | ||
311 | /* Boost regulator current limit control register layout */ | |
312 | #define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK 0x80 | |
313 | #define SPMI_BOOST_CURRENT_LIMIT_MASK 0x07 | |
314 | ||
315 | #define SPMI_VS_OCP_DEFAULT_MAX_RETRIES 10 | |
316 | #define SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS 30 | |
317 | #define SPMI_VS_OCP_FALL_DELAY_US 90 | |
318 | #define SPMI_VS_OCP_FAULT_DELAY_US 20000 | |
319 | ||
320 | #define SPMI_FTSMPS_STEP_CTRL_STEP_MASK 0x18 | |
321 | #define SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT 3 | |
322 | #define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07 | |
323 | #define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0 | |
324 | ||
325 | /* Clock rate in kHz of the FTSMPS regulator reference clock. */ | |
326 | #define SPMI_FTSMPS_CLOCK_RATE 19200 | |
327 | ||
328 | /* Minimum voltage stepper delay for each step. */ | |
329 | #define SPMI_FTSMPS_STEP_DELAY 8 | |
2cf7b99c | 330 | #define SPMI_DEFAULT_STEP_DELAY 20 |
e92a4047 SB |
331 | |
332 | /* | |
333 | * The ratio SPMI_FTSMPS_STEP_MARGIN_NUM/SPMI_FTSMPS_STEP_MARGIN_DEN is used to | |
334 | * adjust the step rate in order to account for oscillator variance. | |
335 | */ | |
336 | #define SPMI_FTSMPS_STEP_MARGIN_NUM 4 | |
337 | #define SPMI_FTSMPS_STEP_MARGIN_DEN 5 | |
338 | ||
27850254 IC |
339 | /* slew_rate has units of uV/us. */ |
340 | #define SPMI_HFSMPS_SLEW_RATE_38p4 38400 | |
341 | ||
42ba89c8 JH |
342 | #define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK 0x03 |
343 | #define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT 0 | |
344 | ||
345 | /* Clock rate in kHz of the FTSMPS426 regulator reference clock. */ | |
346 | #define SPMI_FTSMPS426_CLOCK_RATE 4800 | |
347 | ||
0211f68e JR |
348 | #define SPMI_HFS430_CLOCK_RATE 1600 |
349 | ||
42ba89c8 JH |
350 | /* Minimum voltage stepper delay for each step. */ |
351 | #define SPMI_FTSMPS426_STEP_DELAY 2 | |
352 | ||
353 | /* | |
354 | * The ratio SPMI_FTSMPS426_STEP_MARGIN_NUM/SPMI_FTSMPS426_STEP_MARGIN_DEN is | |
355 | * used to adjust the step rate in order to account for oscillator variance. | |
356 | */ | |
357 | #define SPMI_FTSMPS426_STEP_MARGIN_NUM 10 | |
358 | #define SPMI_FTSMPS426_STEP_MARGIN_DEN 11 | |
359 | ||
360 | ||
e92a4047 SB |
361 | /* VSET value to decide the range of ULT SMPS */ |
362 | #define ULT_SMPS_RANGE_SPLIT 0x60 | |
363 | ||
364 | /** | |
365 | * struct spmi_voltage_range - regulator set point voltage mapping description | |
366 | * @min_uV: Minimum programmable output voltage resulting from | |
367 | * set point register value 0x00 | |
368 | * @max_uV: Maximum programmable output voltage | |
369 | * @step_uV: Output voltage increase resulting from the set point | |
370 | * register value increasing by 1 | |
371 | * @set_point_min_uV: Minimum allowed voltage | |
372 | * @set_point_max_uV: Maximum allowed voltage. This may be tweaked in order | |
373 | * to pick which range should be used in the case of | |
374 | * overlapping set points. | |
375 | * @n_voltages: Number of preferred voltage set points present in this | |
376 | * range | |
377 | * @range_sel: Voltage range register value corresponding to this range | |
378 | * | |
379 | * The following relationships must be true for the values used in this struct: | |
380 | * (max_uV - min_uV) % step_uV == 0 | |
381 | * (set_point_min_uV - min_uV) % step_uV == 0* | |
382 | * (set_point_max_uV - min_uV) % step_uV == 0* | |
383 | * n_voltages = (set_point_max_uV - set_point_min_uV) / step_uV + 1 | |
384 | * | |
385 | * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to | |
386 | * specify that the voltage range has meaning, but is not preferred. | |
387 | */ | |
388 | struct spmi_voltage_range { | |
389 | int min_uV; | |
390 | int max_uV; | |
391 | int step_uV; | |
392 | int set_point_min_uV; | |
393 | int set_point_max_uV; | |
394 | unsigned n_voltages; | |
395 | u8 range_sel; | |
396 | }; | |
397 | ||
398 | /* | |
399 | * The ranges specified in the spmi_voltage_set_points struct must be listed | |
400 | * so that range[i].set_point_max_uV < range[i+1].set_point_min_uV. | |
401 | */ | |
402 | struct spmi_voltage_set_points { | |
403 | struct spmi_voltage_range *range; | |
404 | int count; | |
405 | unsigned n_voltages; | |
406 | }; | |
407 | ||
408 | struct spmi_regulator { | |
409 | struct regulator_desc desc; | |
410 | struct device *dev; | |
411 | struct delayed_work ocp_work; | |
412 | struct regmap *regmap; | |
413 | struct spmi_voltage_set_points *set_points; | |
414 | enum spmi_regulator_logical_type logical_type; | |
415 | int ocp_irq; | |
416 | int ocp_count; | |
417 | int ocp_max_retries; | |
418 | int ocp_retry_delay_ms; | |
419 | int hpm_min_load; | |
420 | int slew_rate; | |
421 | ktime_t vs_enable_time; | |
422 | u16 base; | |
423 | struct list_head node; | |
424 | }; | |
425 | ||
426 | struct spmi_regulator_mapping { | |
427 | enum spmi_regulator_type type; | |
428 | enum spmi_regulator_subtype subtype; | |
429 | enum spmi_regulator_logical_type logical_type; | |
430 | u32 revision_min; | |
431 | u32 revision_max; | |
3b619e3e | 432 | const struct regulator_ops *ops; |
e92a4047 SB |
433 | struct spmi_voltage_set_points *set_points; |
434 | int hpm_min_load; | |
435 | }; | |
436 | ||
437 | struct spmi_regulator_data { | |
438 | const char *name; | |
439 | u16 base; | |
440 | const char *supply; | |
441 | const char *ocp; | |
442 | u16 force_type; | |
443 | }; | |
444 | ||
445 | #define SPMI_VREG(_type, _subtype, _dig_major_min, _dig_major_max, \ | |
446 | _logical_type, _ops_val, _set_points_val, _hpm_min_load) \ | |
447 | { \ | |
448 | .type = SPMI_REGULATOR_TYPE_##_type, \ | |
449 | .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \ | |
450 | .revision_min = _dig_major_min, \ | |
451 | .revision_max = _dig_major_max, \ | |
452 | .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_##_logical_type, \ | |
453 | .ops = &spmi_##_ops_val##_ops, \ | |
454 | .set_points = &_set_points_val##_set_points, \ | |
455 | .hpm_min_load = _hpm_min_load, \ | |
456 | } | |
457 | ||
458 | #define SPMI_VREG_VS(_subtype, _dig_major_min, _dig_major_max) \ | |
459 | { \ | |
460 | .type = SPMI_REGULATOR_TYPE_VS, \ | |
461 | .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \ | |
462 | .revision_min = _dig_major_min, \ | |
463 | .revision_max = _dig_major_max, \ | |
464 | .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_VS, \ | |
465 | .ops = &spmi_vs_ops, \ | |
466 | } | |
467 | ||
468 | #define SPMI_VOLTAGE_RANGE(_range_sel, _min_uV, _set_point_min_uV, \ | |
469 | _set_point_max_uV, _max_uV, _step_uV) \ | |
470 | { \ | |
471 | .min_uV = _min_uV, \ | |
472 | .max_uV = _max_uV, \ | |
473 | .set_point_min_uV = _set_point_min_uV, \ | |
474 | .set_point_max_uV = _set_point_max_uV, \ | |
475 | .step_uV = _step_uV, \ | |
476 | .range_sel = _range_sel, \ | |
477 | } | |
478 | ||
479 | #define DEFINE_SPMI_SET_POINTS(name) \ | |
480 | struct spmi_voltage_set_points name##_set_points = { \ | |
481 | .range = name##_ranges, \ | |
482 | .count = ARRAY_SIZE(name##_ranges), \ | |
483 | } | |
484 | ||
485 | /* | |
486 | * These tables contain the physically available PMIC regulator voltage setpoint | |
487 | * ranges. Where two ranges overlap in hardware, one of the ranges is trimmed | |
488 | * to ensure that the setpoints available to software are monotonically | |
489 | * increasing and unique. The set_voltage callback functions expect these | |
490 | * properties to hold. | |
491 | */ | |
492 | static struct spmi_voltage_range pldo_ranges[] = { | |
493 | SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500), | |
494 | SPMI_VOLTAGE_RANGE(3, 1500000, 1550000, 3075000, 3075000, 25000), | |
495 | SPMI_VOLTAGE_RANGE(4, 1750000, 3100000, 4900000, 4900000, 50000), | |
496 | }; | |
497 | ||
498 | static struct spmi_voltage_range nldo1_ranges[] = { | |
499 | SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500), | |
500 | }; | |
501 | ||
502 | static struct spmi_voltage_range nldo2_ranges[] = { | |
503 | SPMI_VOLTAGE_RANGE(0, 375000, 0, 0, 1537500, 12500), | |
504 | SPMI_VOLTAGE_RANGE(1, 375000, 375000, 768750, 768750, 6250), | |
505 | SPMI_VOLTAGE_RANGE(2, 750000, 775000, 1537500, 1537500, 12500), | |
506 | }; | |
507 | ||
508 | static struct spmi_voltage_range nldo3_ranges[] = { | |
509 | SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500), | |
510 | SPMI_VOLTAGE_RANGE(1, 375000, 0, 0, 1537500, 12500), | |
511 | SPMI_VOLTAGE_RANGE(2, 750000, 0, 0, 1537500, 12500), | |
512 | }; | |
513 | ||
514 | static struct spmi_voltage_range ln_ldo_ranges[] = { | |
515 | SPMI_VOLTAGE_RANGE(1, 690000, 690000, 1110000, 1110000, 60000), | |
516 | SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000), | |
517 | }; | |
518 | ||
519 | static struct spmi_voltage_range smps_ranges[] = { | |
520 | SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), | |
521 | SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000), | |
522 | }; | |
523 | ||
524 | static struct spmi_voltage_range ftsmps_ranges[] = { | |
525 | SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000), | |
526 | SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000), | |
527 | }; | |
528 | ||
529 | static struct spmi_voltage_range ftsmps2p5_ranges[] = { | |
530 | SPMI_VOLTAGE_RANGE(0, 80000, 350000, 1355000, 1355000, 5000), | |
531 | SPMI_VOLTAGE_RANGE(1, 160000, 1360000, 2200000, 2200000, 10000), | |
532 | }; | |
533 | ||
42ba89c8 JH |
534 | static struct spmi_voltage_range ftsmps426_ranges[] = { |
535 | SPMI_VOLTAGE_RANGE(0, 0, 320000, 1352000, 1352000, 4000), | |
536 | }; | |
537 | ||
e92a4047 SB |
538 | static struct spmi_voltage_range boost_ranges[] = { |
539 | SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000), | |
540 | }; | |
541 | ||
542 | static struct spmi_voltage_range boost_byp_ranges[] = { | |
543 | SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000), | |
544 | }; | |
545 | ||
546 | static struct spmi_voltage_range ult_lo_smps_ranges[] = { | |
547 | SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500), | |
548 | SPMI_VOLTAGE_RANGE(1, 750000, 0, 0, 1525000, 25000), | |
549 | }; | |
550 | ||
551 | static struct spmi_voltage_range ult_ho_smps_ranges[] = { | |
552 | SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000), | |
553 | }; | |
554 | ||
555 | static struct spmi_voltage_range ult_nldo_ranges[] = { | |
556 | SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500), | |
557 | }; | |
558 | ||
559 | static struct spmi_voltage_range ult_pldo_ranges[] = { | |
560 | SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500), | |
561 | }; | |
562 | ||
328816c2 ADR |
563 | static struct spmi_voltage_range pldo660_ranges[] = { |
564 | SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 3544000, 3544000, 8000), | |
565 | }; | |
566 | ||
567 | static struct spmi_voltage_range nldo660_ranges[] = { | |
568 | SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000), | |
569 | }; | |
570 | ||
571 | static struct spmi_voltage_range ht_lvpldo_ranges[] = { | |
572 | SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 2000000, 2000000, 8000), | |
573 | }; | |
574 | ||
575 | static struct spmi_voltage_range ht_nldo_ranges[] = { | |
576 | SPMI_VOLTAGE_RANGE(0, 312000, 312000, 1304000, 1304000, 8000), | |
577 | }; | |
578 | ||
0211f68e JR |
579 | static struct spmi_voltage_range hfs430_ranges[] = { |
580 | SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000), | |
581 | }; | |
582 | ||
00f6ebbd RM |
583 | static struct spmi_voltage_range ht_p150_ranges[] = { |
584 | SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000), | |
585 | }; | |
586 | ||
3d04ae8e RM |
587 | static struct spmi_voltage_range ht_p600_ranges[] = { |
588 | SPMI_VOLTAGE_RANGE(0, 1704000, 1704000, 1896000, 1896000, 8000), | |
589 | }; | |
590 | ||
0d1cf568 IC |
591 | static struct spmi_voltage_range nldo_510_ranges[] = { |
592 | SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000), | |
593 | }; | |
594 | ||
595 | static struct spmi_voltage_range ftsmps510_ranges[] = { | |
596 | SPMI_VOLTAGE_RANGE(0, 300000, 300000, 1372000, 1372000, 4000), | |
597 | }; | |
598 | ||
e92a4047 SB |
599 | static DEFINE_SPMI_SET_POINTS(pldo); |
600 | static DEFINE_SPMI_SET_POINTS(nldo1); | |
601 | static DEFINE_SPMI_SET_POINTS(nldo2); | |
602 | static DEFINE_SPMI_SET_POINTS(nldo3); | |
603 | static DEFINE_SPMI_SET_POINTS(ln_ldo); | |
604 | static DEFINE_SPMI_SET_POINTS(smps); | |
605 | static DEFINE_SPMI_SET_POINTS(ftsmps); | |
606 | static DEFINE_SPMI_SET_POINTS(ftsmps2p5); | |
42ba89c8 | 607 | static DEFINE_SPMI_SET_POINTS(ftsmps426); |
e92a4047 SB |
608 | static DEFINE_SPMI_SET_POINTS(boost); |
609 | static DEFINE_SPMI_SET_POINTS(boost_byp); | |
610 | static DEFINE_SPMI_SET_POINTS(ult_lo_smps); | |
611 | static DEFINE_SPMI_SET_POINTS(ult_ho_smps); | |
612 | static DEFINE_SPMI_SET_POINTS(ult_nldo); | |
613 | static DEFINE_SPMI_SET_POINTS(ult_pldo); | |
328816c2 ADR |
614 | static DEFINE_SPMI_SET_POINTS(pldo660); |
615 | static DEFINE_SPMI_SET_POINTS(nldo660); | |
616 | static DEFINE_SPMI_SET_POINTS(ht_lvpldo); | |
617 | static DEFINE_SPMI_SET_POINTS(ht_nldo); | |
0211f68e | 618 | static DEFINE_SPMI_SET_POINTS(hfs430); |
00f6ebbd | 619 | static DEFINE_SPMI_SET_POINTS(ht_p150); |
3d04ae8e | 620 | static DEFINE_SPMI_SET_POINTS(ht_p600); |
0d1cf568 IC |
621 | static DEFINE_SPMI_SET_POINTS(nldo_510); |
622 | static DEFINE_SPMI_SET_POINTS(ftsmps510); | |
e92a4047 SB |
623 | |
624 | static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf, | |
625 | int len) | |
626 | { | |
627 | return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len); | |
628 | } | |
629 | ||
630 | static inline int spmi_vreg_write(struct spmi_regulator *vreg, u16 addr, | |
631 | u8 *buf, int len) | |
632 | { | |
633 | return regmap_bulk_write(vreg->regmap, vreg->base + addr, buf, len); | |
634 | } | |
635 | ||
636 | static int spmi_vreg_update_bits(struct spmi_regulator *vreg, u16 addr, u8 val, | |
637 | u8 mask) | |
638 | { | |
639 | return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val); | |
640 | } | |
641 | ||
e92a4047 SB |
642 | static int spmi_regulator_vs_enable(struct regulator_dev *rdev) |
643 | { | |
644 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
645 | ||
646 | if (vreg->ocp_irq) { | |
647 | vreg->ocp_count = 0; | |
648 | vreg->vs_enable_time = ktime_get(); | |
649 | } | |
650 | ||
9d485332 | 651 | return regulator_enable_regmap(rdev); |
e92a4047 SB |
652 | } |
653 | ||
89a6a5e5 MV |
654 | static int spmi_regulator_vs_ocp(struct regulator_dev *rdev, int lim_uA, |
655 | int severity, bool enable) | |
e2adfacd SB |
656 | { |
657 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
658 | u8 reg = SPMI_VS_OCP_OVERRIDE; | |
659 | ||
89a6a5e5 MV |
660 | if (lim_uA || !enable || severity != REGULATOR_SEVERITY_PROT) |
661 | return -EINVAL; | |
662 | ||
e2adfacd SB |
663 | return spmi_vreg_write(vreg, SPMI_VS_REG_OCP, ®, 1); |
664 | } | |
665 | ||
e92a4047 | 666 | static int spmi_regulator_select_voltage(struct spmi_regulator *vreg, |
1b5b1968 | 667 | int min_uV, int max_uV) |
e92a4047 SB |
668 | { |
669 | const struct spmi_voltage_range *range; | |
670 | int uV = min_uV; | |
671 | int lim_min_uV, lim_max_uV, i, range_id, range_max_uV; | |
1b5b1968 | 672 | int selector, voltage_sel; |
e92a4047 SB |
673 | |
674 | /* Check if request voltage is outside of physically settable range. */ | |
675 | lim_min_uV = vreg->set_points->range[0].set_point_min_uV; | |
676 | lim_max_uV = | |
677 | vreg->set_points->range[vreg->set_points->count - 1].set_point_max_uV; | |
678 | ||
679 | if (uV < lim_min_uV && max_uV >= lim_min_uV) | |
680 | uV = lim_min_uV; | |
681 | ||
682 | if (uV < lim_min_uV || uV > lim_max_uV) { | |
683 | dev_err(vreg->dev, | |
684 | "request v=[%d, %d] is outside possible v=[%d, %d]\n", | |
685 | min_uV, max_uV, lim_min_uV, lim_max_uV); | |
686 | return -EINVAL; | |
687 | } | |
688 | ||
689 | /* Find the range which uV is inside of. */ | |
690 | for (i = vreg->set_points->count - 1; i > 0; i--) { | |
691 | range_max_uV = vreg->set_points->range[i - 1].set_point_max_uV; | |
692 | if (uV > range_max_uV && range_max_uV > 0) | |
693 | break; | |
694 | } | |
695 | ||
696 | range_id = i; | |
697 | range = &vreg->set_points->range[range_id]; | |
e92a4047 SB |
698 | |
699 | /* | |
700 | * Force uV to be an allowed set point by applying a ceiling function to | |
701 | * the uV value. | |
702 | */ | |
1b5b1968 SB |
703 | voltage_sel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV); |
704 | uV = voltage_sel * range->step_uV + range->min_uV; | |
e92a4047 SB |
705 | |
706 | if (uV > max_uV) { | |
707 | dev_err(vreg->dev, | |
708 | "request v=[%d, %d] cannot be met by any set point; " | |
709 | "next set point: %d\n", | |
710 | min_uV, max_uV, uV); | |
711 | return -EINVAL; | |
712 | } | |
713 | ||
1b5b1968 | 714 | selector = 0; |
e92a4047 | 715 | for (i = 0; i < range_id; i++) |
1b5b1968 SB |
716 | selector += vreg->set_points->range[i].n_voltages; |
717 | selector += (uV - range->set_point_min_uV) / range->step_uV; | |
e92a4047 | 718 | |
1b5b1968 SB |
719 | return selector; |
720 | } | |
721 | ||
722 | static int spmi_sw_selector_to_hw(struct spmi_regulator *vreg, | |
723 | unsigned selector, u8 *range_sel, | |
724 | u8 *voltage_sel) | |
725 | { | |
726 | const struct spmi_voltage_range *range, *end; | |
ab953b9d | 727 | unsigned offset; |
1b5b1968 SB |
728 | |
729 | range = vreg->set_points->range; | |
730 | end = range + vreg->set_points->count; | |
731 | ||
732 | for (; range < end; range++) { | |
733 | if (selector < range->n_voltages) { | |
ab953b9d SB |
734 | /* |
735 | * hardware selectors between set point min and real | |
736 | * min are invalid so we ignore them | |
737 | */ | |
738 | offset = range->set_point_min_uV - range->min_uV; | |
739 | offset /= range->step_uV; | |
740 | *voltage_sel = selector + offset; | |
1b5b1968 SB |
741 | *range_sel = range->range_sel; |
742 | return 0; | |
743 | } | |
744 | ||
745 | selector -= range->n_voltages; | |
746 | } | |
747 | ||
748 | return -EINVAL; | |
749 | } | |
750 | ||
751 | static int spmi_hw_selector_to_sw(struct spmi_regulator *vreg, u8 hw_sel, | |
752 | const struct spmi_voltage_range *range) | |
753 | { | |
ab953b9d SB |
754 | unsigned sw_sel = 0; |
755 | unsigned offset, max_hw_sel; | |
1b5b1968 | 756 | const struct spmi_voltage_range *r = vreg->set_points->range; |
ab953b9d SB |
757 | const struct spmi_voltage_range *end = r + vreg->set_points->count; |
758 | ||
759 | for (; r < end; r++) { | |
760 | if (r == range && range->n_voltages) { | |
761 | /* | |
762 | * hardware selectors between set point min and real | |
763 | * min and between set point max and real max are | |
764 | * invalid so we return an error if they're | |
765 | * programmed into the hardware | |
766 | */ | |
767 | offset = range->set_point_min_uV - range->min_uV; | |
768 | offset /= range->step_uV; | |
769 | if (hw_sel < offset) | |
770 | return -EINVAL; | |
771 | ||
772 | max_hw_sel = range->set_point_max_uV - range->min_uV; | |
773 | max_hw_sel /= range->step_uV; | |
774 | if (hw_sel > max_hw_sel) | |
775 | return -EINVAL; | |
776 | ||
777 | return sw_sel + hw_sel - offset; | |
778 | } | |
1b5b1968 | 779 | sw_sel += r->n_voltages; |
1b5b1968 SB |
780 | } |
781 | ||
ab953b9d | 782 | return -EINVAL; |
e92a4047 SB |
783 | } |
784 | ||
785 | static const struct spmi_voltage_range * | |
786 | spmi_regulator_find_range(struct spmi_regulator *vreg) | |
787 | { | |
788 | u8 range_sel; | |
789 | const struct spmi_voltage_range *range, *end; | |
790 | ||
791 | range = vreg->set_points->range; | |
792 | end = range + vreg->set_points->count; | |
793 | ||
794 | spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, &range_sel, 1); | |
795 | ||
796 | for (; range < end; range++) | |
797 | if (range->range_sel == range_sel) | |
798 | return range; | |
799 | ||
800 | return NULL; | |
801 | } | |
802 | ||
803 | static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg, | |
1b5b1968 | 804 | int min_uV, int max_uV) |
e92a4047 SB |
805 | { |
806 | const struct spmi_voltage_range *range; | |
807 | int uV = min_uV; | |
1b5b1968 | 808 | int i, selector; |
e92a4047 SB |
809 | |
810 | range = spmi_regulator_find_range(vreg); | |
811 | if (!range) | |
812 | goto different_range; | |
813 | ||
814 | if (uV < range->min_uV && max_uV >= range->min_uV) | |
815 | uV = range->min_uV; | |
816 | ||
817 | if (uV < range->min_uV || uV > range->max_uV) { | |
818 | /* Current range doesn't support the requested voltage. */ | |
819 | goto different_range; | |
820 | } | |
821 | ||
822 | /* | |
823 | * Force uV to be an allowed set point by applying a ceiling function to | |
824 | * the uV value. | |
825 | */ | |
1b5b1968 SB |
826 | uV = DIV_ROUND_UP(uV - range->min_uV, range->step_uV); |
827 | uV = uV * range->step_uV + range->min_uV; | |
e92a4047 SB |
828 | |
829 | if (uV > max_uV) { | |
830 | /* | |
831 | * No set point in the current voltage range is within the | |
832 | * requested min_uV to max_uV range. | |
833 | */ | |
834 | goto different_range; | |
835 | } | |
836 | ||
1b5b1968 | 837 | selector = 0; |
e92a4047 SB |
838 | for (i = 0; i < vreg->set_points->count; i++) { |
839 | if (uV >= vreg->set_points->range[i].set_point_min_uV | |
9b2dfee3 | 840 | && uV <= vreg->set_points->range[i].set_point_max_uV) { |
1b5b1968 | 841 | selector += |
e92a4047 SB |
842 | (uV - vreg->set_points->range[i].set_point_min_uV) |
843 | / vreg->set_points->range[i].step_uV; | |
844 | break; | |
9b2dfee3 | 845 | } |
e92a4047 | 846 | |
1b5b1968 | 847 | selector += vreg->set_points->range[i].n_voltages; |
e92a4047 SB |
848 | } |
849 | ||
1b5b1968 | 850 | if (selector >= vreg->set_points->n_voltages) |
e92a4047 SB |
851 | goto different_range; |
852 | ||
b1d21a24 | 853 | return selector; |
e92a4047 SB |
854 | |
855 | different_range: | |
1b5b1968 | 856 | return spmi_regulator_select_voltage(vreg, min_uV, max_uV); |
e92a4047 SB |
857 | } |
858 | ||
1b5b1968 SB |
859 | static int spmi_regulator_common_map_voltage(struct regulator_dev *rdev, |
860 | int min_uV, int max_uV) | |
e92a4047 SB |
861 | { |
862 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
e92a4047 SB |
863 | |
864 | /* | |
865 | * Favor staying in the current voltage range if possible. This avoids | |
866 | * voltage spikes that occur when changing the voltage range. | |
867 | */ | |
1b5b1968 SB |
868 | return spmi_regulator_select_voltage_same_range(vreg, min_uV, max_uV); |
869 | } | |
870 | ||
871 | static int | |
872 | spmi_regulator_common_set_voltage(struct regulator_dev *rdev, unsigned selector) | |
873 | { | |
874 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
875 | int ret; | |
876 | u8 buf[2]; | |
877 | u8 range_sel, voltage_sel; | |
878 | ||
879 | ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); | |
e92a4047 SB |
880 | if (ret) |
881 | return ret; | |
882 | ||
883 | buf[0] = range_sel; | |
884 | buf[1] = voltage_sel; | |
885 | return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, buf, 2); | |
886 | } | |
887 | ||
42ba89c8 JH |
888 | static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, |
889 | unsigned selector); | |
890 | ||
891 | static int spmi_regulator_ftsmps426_set_voltage(struct regulator_dev *rdev, | |
892 | unsigned selector) | |
893 | { | |
894 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
895 | u8 buf[2]; | |
896 | int mV; | |
897 | ||
898 | mV = spmi_regulator_common_list_voltage(rdev, selector) / 1000; | |
899 | ||
900 | buf[0] = mV & 0xff; | |
901 | buf[1] = mV >> 8; | |
902 | return spmi_vreg_write(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2); | |
903 | } | |
904 | ||
e92a4047 SB |
905 | static int spmi_regulator_set_voltage_time_sel(struct regulator_dev *rdev, |
906 | unsigned int old_selector, unsigned int new_selector) | |
907 | { | |
908 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
e92a4047 SB |
909 | int diff_uV; |
910 | ||
61d7fdc4 JH |
911 | diff_uV = abs(spmi_regulator_common_list_voltage(rdev, new_selector) - |
912 | spmi_regulator_common_list_voltage(rdev, old_selector)); | |
e92a4047 SB |
913 | |
914 | return DIV_ROUND_UP(diff_uV, vreg->slew_rate); | |
915 | } | |
916 | ||
917 | static int spmi_regulator_common_get_voltage(struct regulator_dev *rdev) | |
918 | { | |
919 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
920 | const struct spmi_voltage_range *range; | |
921 | u8 voltage_sel; | |
922 | ||
923 | spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); | |
924 | ||
925 | range = spmi_regulator_find_range(vreg); | |
926 | if (!range) | |
1b5b1968 | 927 | return -EINVAL; |
e92a4047 | 928 | |
1b5b1968 | 929 | return spmi_hw_selector_to_sw(vreg, voltage_sel, range); |
e92a4047 SB |
930 | } |
931 | ||
42ba89c8 JH |
932 | static int spmi_regulator_ftsmps426_get_voltage(struct regulator_dev *rdev) |
933 | { | |
934 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
935 | const struct spmi_voltage_range *range; | |
936 | u8 buf[2]; | |
937 | int uV; | |
938 | ||
939 | spmi_vreg_read(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2); | |
940 | ||
941 | uV = (((unsigned int)buf[1] << 8) | (unsigned int)buf[0]) * 1000; | |
942 | range = vreg->set_points->range; | |
943 | ||
944 | return (uV - range->set_point_min_uV) / range->step_uV; | |
945 | } | |
946 | ||
1b5b1968 SB |
947 | static int spmi_regulator_single_map_voltage(struct regulator_dev *rdev, |
948 | int min_uV, int max_uV) | |
e92a4047 SB |
949 | { |
950 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
e92a4047 | 951 | |
1b5b1968 SB |
952 | return spmi_regulator_select_voltage(vreg, min_uV, max_uV); |
953 | } | |
954 | ||
955 | static int spmi_regulator_single_range_set_voltage(struct regulator_dev *rdev, | |
956 | unsigned selector) | |
957 | { | |
958 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
959 | u8 sel = selector; | |
e92a4047 SB |
960 | |
961 | /* | |
962 | * Certain types of regulators do not have a range select register so | |
963 | * only voltage set register needs to be written. | |
964 | */ | |
965 | return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &sel, 1); | |
966 | } | |
967 | ||
968 | static int spmi_regulator_single_range_get_voltage(struct regulator_dev *rdev) | |
969 | { | |
970 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1b5b1968 SB |
971 | u8 selector; |
972 | int ret; | |
e92a4047 | 973 | |
1b5b1968 SB |
974 | ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &selector, 1); |
975 | if (ret) | |
976 | return ret; | |
e92a4047 | 977 | |
1b5b1968 | 978 | return selector; |
e92a4047 SB |
979 | } |
980 | ||
981 | static int spmi_regulator_ult_lo_smps_set_voltage(struct regulator_dev *rdev, | |
1b5b1968 | 982 | unsigned selector) |
e92a4047 SB |
983 | { |
984 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
985 | int ret; | |
986 | u8 range_sel, voltage_sel; | |
987 | ||
1b5b1968 | 988 | ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); |
e92a4047 SB |
989 | if (ret) |
990 | return ret; | |
991 | ||
992 | /* | |
993 | * Calculate VSET based on range | |
994 | * In case of range 0: voltage_sel is a 7 bit value, can be written | |
995 | * witout any modification. | |
996 | * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to | |
997 | * [011]. | |
998 | */ | |
999 | if (range_sel == 1) | |
1000 | voltage_sel |= ULT_SMPS_RANGE_SPLIT; | |
1001 | ||
0f94bffa | 1002 | return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_VOLTAGE_SET, |
1b5b1968 | 1003 | voltage_sel, 0xff); |
e92a4047 SB |
1004 | } |
1005 | ||
1006 | static int spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev *rdev) | |
1007 | { | |
1008 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1009 | const struct spmi_voltage_range *range; | |
1010 | u8 voltage_sel; | |
1011 | ||
1012 | spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1); | |
1013 | ||
1014 | range = spmi_regulator_find_range(vreg); | |
1015 | if (!range) | |
1b5b1968 | 1016 | return -EINVAL; |
e92a4047 SB |
1017 | |
1018 | if (range->range_sel == 1) | |
1019 | voltage_sel &= ~ULT_SMPS_RANGE_SPLIT; | |
1020 | ||
1b5b1968 | 1021 | return spmi_hw_selector_to_sw(vreg, voltage_sel, range); |
e92a4047 SB |
1022 | } |
1023 | ||
1024 | static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev, | |
1025 | unsigned selector) | |
1026 | { | |
1027 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1028 | int uV = 0; | |
1029 | int i; | |
1030 | ||
1031 | if (selector >= vreg->set_points->n_voltages) | |
1032 | return 0; | |
1033 | ||
1034 | for (i = 0; i < vreg->set_points->count; i++) { | |
9b2dfee3 | 1035 | if (selector < vreg->set_points->range[i].n_voltages) { |
e92a4047 SB |
1036 | uV = selector * vreg->set_points->range[i].step_uV |
1037 | + vreg->set_points->range[i].set_point_min_uV; | |
1038 | break; | |
9b2dfee3 | 1039 | } |
e92a4047 SB |
1040 | |
1041 | selector -= vreg->set_points->range[i].n_voltages; | |
1042 | } | |
1043 | ||
1044 | return uV; | |
1045 | } | |
1046 | ||
1047 | static int | |
1048 | spmi_regulator_common_set_bypass(struct regulator_dev *rdev, bool enable) | |
1049 | { | |
1050 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1051 | u8 mask = SPMI_COMMON_MODE_BYPASS_MASK; | |
1052 | u8 val = 0; | |
1053 | ||
1054 | if (enable) | |
1055 | val = mask; | |
1056 | ||
1057 | return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); | |
1058 | } | |
1059 | ||
1060 | static int | |
1061 | spmi_regulator_common_get_bypass(struct regulator_dev *rdev, bool *enable) | |
1062 | { | |
1063 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1064 | u8 val; | |
1065 | int ret; | |
1066 | ||
1067 | ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &val, 1); | |
1068 | *enable = val & SPMI_COMMON_MODE_BYPASS_MASK; | |
1069 | ||
1070 | return ret; | |
1071 | } | |
1072 | ||
1073 | static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev) | |
1074 | { | |
1075 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1076 | u8 reg; | |
1077 | ||
1078 | spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); | |
1079 | ||
ba576a62 | 1080 | reg &= SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK; |
e92a4047 | 1081 | |
ba576a62 JH |
1082 | switch (reg) { |
1083 | case SPMI_COMMON_MODE_HPM_MASK: | |
1084 | return REGULATOR_MODE_NORMAL; | |
1085 | case SPMI_COMMON_MODE_AUTO_MASK: | |
e2adfacd | 1086 | return REGULATOR_MODE_FAST; |
ba576a62 JH |
1087 | default: |
1088 | return REGULATOR_MODE_IDLE; | |
1089 | } | |
e92a4047 SB |
1090 | } |
1091 | ||
42ba89c8 JH |
1092 | static unsigned int spmi_regulator_ftsmps426_get_mode(struct regulator_dev *rdev) |
1093 | { | |
1094 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1095 | u8 reg; | |
1096 | ||
1097 | spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); | |
1098 | ||
1099 | switch (reg) { | |
1100 | case SPMI_FTSMPS426_MODE_HPM_MASK: | |
1101 | return REGULATOR_MODE_NORMAL; | |
1102 | case SPMI_FTSMPS426_MODE_AUTO_MASK: | |
1103 | return REGULATOR_MODE_FAST; | |
1104 | default: | |
1105 | return REGULATOR_MODE_IDLE; | |
1106 | } | |
1107 | } | |
1108 | ||
27850254 IC |
1109 | static unsigned int spmi_regulator_hfsmps_get_mode(struct regulator_dev *rdev) |
1110 | { | |
1111 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1112 | u8 reg; | |
1113 | ||
1114 | spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1); | |
1115 | ||
1116 | switch (reg) { | |
1117 | case SPMI_HFSMPS_MODE_HPM_MASK: | |
1118 | return REGULATOR_MODE_NORMAL; | |
1119 | case SPMI_HFSMPS_MODE_AUTO_MASK: | |
1120 | return REGULATOR_MODE_FAST; | |
1121 | default: | |
1122 | return REGULATOR_MODE_IDLE; | |
1123 | } | |
1124 | } | |
1125 | ||
e92a4047 SB |
1126 | static int |
1127 | spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode) | |
1128 | { | |
1129 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
e2adfacd | 1130 | u8 mask = SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK; |
ba576a62 | 1131 | u8 val; |
e92a4047 | 1132 | |
ba576a62 JH |
1133 | switch (mode) { |
1134 | case REGULATOR_MODE_NORMAL: | |
e2adfacd | 1135 | val = SPMI_COMMON_MODE_HPM_MASK; |
ba576a62 JH |
1136 | break; |
1137 | case REGULATOR_MODE_FAST: | |
e2adfacd | 1138 | val = SPMI_COMMON_MODE_AUTO_MASK; |
ba576a62 JH |
1139 | break; |
1140 | default: | |
1141 | val = 0; | |
1142 | break; | |
1143 | } | |
e92a4047 SB |
1144 | |
1145 | return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); | |
1146 | } | |
1147 | ||
42ba89c8 JH |
1148 | static int |
1149 | spmi_regulator_ftsmps426_set_mode(struct regulator_dev *rdev, unsigned int mode) | |
1150 | { | |
1151 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1152 | u8 mask = SPMI_FTSMPS426_MODE_MASK; | |
1153 | u8 val; | |
1154 | ||
1155 | switch (mode) { | |
1156 | case REGULATOR_MODE_NORMAL: | |
1157 | val = SPMI_FTSMPS426_MODE_HPM_MASK; | |
1158 | break; | |
1159 | case REGULATOR_MODE_FAST: | |
1160 | val = SPMI_FTSMPS426_MODE_AUTO_MASK; | |
1161 | break; | |
1162 | case REGULATOR_MODE_IDLE: | |
1163 | val = SPMI_FTSMPS426_MODE_LPM_MASK; | |
1164 | break; | |
1165 | default: | |
1166 | return -EINVAL; | |
1167 | } | |
1168 | ||
1169 | return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); | |
1170 | } | |
1171 | ||
27850254 IC |
1172 | static int |
1173 | spmi_regulator_hfsmps_set_mode(struct regulator_dev *rdev, unsigned int mode) | |
1174 | { | |
1175 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1176 | u8 mask = SPMI_HFSMPS_MODE_MASK; | |
1177 | u8 val; | |
1178 | ||
1179 | switch (mode) { | |
1180 | case REGULATOR_MODE_NORMAL: | |
1181 | val = SPMI_HFSMPS_MODE_HPM_MASK; | |
1182 | break; | |
1183 | case REGULATOR_MODE_FAST: | |
1184 | val = SPMI_HFSMPS_MODE_AUTO_MASK; | |
1185 | break; | |
1186 | case REGULATOR_MODE_IDLE: | |
0d1cf568 IC |
1187 | val = vreg->logical_type == |
1188 | SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3 ? | |
1189 | SPMI_HFSMPS_MODE_RETENTION_MASK : | |
1190 | SPMI_HFSMPS_MODE_LPM_MASK; | |
27850254 IC |
1191 | break; |
1192 | default: | |
1193 | return -EINVAL; | |
1194 | } | |
1195 | ||
1196 | return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask); | |
1197 | } | |
1198 | ||
e92a4047 SB |
1199 | static int |
1200 | spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA) | |
1201 | { | |
1202 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1203 | unsigned int mode; | |
1204 | ||
1205 | if (load_uA >= vreg->hpm_min_load) | |
1206 | mode = REGULATOR_MODE_NORMAL; | |
1207 | else | |
1208 | mode = REGULATOR_MODE_IDLE; | |
1209 | ||
1210 | return spmi_regulator_common_set_mode(rdev, mode); | |
1211 | } | |
1212 | ||
1213 | static int spmi_regulator_common_set_pull_down(struct regulator_dev *rdev) | |
1214 | { | |
1215 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1216 | unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK; | |
1217 | ||
1218 | return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_PULL_DOWN, | |
1219 | mask, mask); | |
1220 | } | |
1221 | ||
27850254 IC |
1222 | static int spmi_regulator_hfsmps_set_pull_down(struct regulator_dev *rdev) |
1223 | { | |
1224 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1225 | unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK; | |
1226 | ||
1227 | return spmi_vreg_update_bits(vreg, SPMI_HFSMPS_REG_PULL_DOWN, | |
1228 | mask, mask); | |
1229 | } | |
1230 | ||
e92a4047 SB |
1231 | static int spmi_regulator_common_set_soft_start(struct regulator_dev *rdev) |
1232 | { | |
1233 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1234 | unsigned int mask = SPMI_LDO_SOFT_START_ENABLE_MASK; | |
1235 | ||
1236 | return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_SOFT_START, | |
1237 | mask, mask); | |
1238 | } | |
1239 | ||
1240 | static int spmi_regulator_set_ilim(struct regulator_dev *rdev, int ilim_uA) | |
1241 | { | |
1242 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1243 | enum spmi_regulator_logical_type type = vreg->logical_type; | |
1244 | unsigned int current_reg; | |
1245 | u8 reg; | |
1246 | u8 mask = SPMI_BOOST_CURRENT_LIMIT_MASK | | |
1247 | SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; | |
1248 | int max = (SPMI_BOOST_CURRENT_LIMIT_MASK + 1) * 500; | |
1249 | ||
1250 | if (type == SPMI_REGULATOR_LOGICAL_TYPE_BOOST) | |
1251 | current_reg = SPMI_BOOST_REG_CURRENT_LIMIT; | |
1252 | else | |
1253 | current_reg = SPMI_BOOST_BYP_REG_CURRENT_LIMIT; | |
1254 | ||
1255 | if (ilim_uA > max || ilim_uA <= 0) | |
1256 | return -EINVAL; | |
1257 | ||
1258 | reg = (ilim_uA - 1) / 500; | |
1259 | reg |= SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK; | |
1260 | ||
1261 | return spmi_vreg_update_bits(vreg, current_reg, reg, mask); | |
1262 | } | |
1263 | ||
1264 | static int spmi_regulator_vs_clear_ocp(struct spmi_regulator *vreg) | |
1265 | { | |
1266 | int ret; | |
1267 | ||
1268 | ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, | |
1269 | SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK); | |
1270 | ||
1271 | vreg->vs_enable_time = ktime_get(); | |
1272 | ||
1273 | ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE, | |
1274 | SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK); | |
1275 | ||
1276 | return ret; | |
1277 | } | |
1278 | ||
1279 | static void spmi_regulator_vs_ocp_work(struct work_struct *work) | |
1280 | { | |
1281 | struct delayed_work *dwork = to_delayed_work(work); | |
1282 | struct spmi_regulator *vreg | |
1283 | = container_of(dwork, struct spmi_regulator, ocp_work); | |
1284 | ||
1285 | spmi_regulator_vs_clear_ocp(vreg); | |
1286 | } | |
1287 | ||
1288 | static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data) | |
1289 | { | |
1290 | struct spmi_regulator *vreg = data; | |
1291 | ktime_t ocp_irq_time; | |
1292 | s64 ocp_trigger_delay_us; | |
1293 | ||
1294 | ocp_irq_time = ktime_get(); | |
1295 | ocp_trigger_delay_us = ktime_us_delta(ocp_irq_time, | |
1296 | vreg->vs_enable_time); | |
1297 | ||
1298 | /* | |
1299 | * Reset the OCP count if there is a large delay between switch enable | |
1300 | * and when OCP triggers. This is indicative of a hotplug event as | |
1301 | * opposed to a fault. | |
1302 | */ | |
1303 | if (ocp_trigger_delay_us > SPMI_VS_OCP_FAULT_DELAY_US) | |
1304 | vreg->ocp_count = 0; | |
1305 | ||
1306 | /* Wait for switch output to settle back to 0 V after OCP triggered. */ | |
1307 | udelay(SPMI_VS_OCP_FALL_DELAY_US); | |
1308 | ||
1309 | vreg->ocp_count++; | |
1310 | ||
1311 | if (vreg->ocp_count == 1) { | |
1312 | /* Immediately clear the over current condition. */ | |
1313 | spmi_regulator_vs_clear_ocp(vreg); | |
1314 | } else if (vreg->ocp_count <= vreg->ocp_max_retries) { | |
1315 | /* Schedule the over current clear task to run later. */ | |
1316 | schedule_delayed_work(&vreg->ocp_work, | |
1317 | msecs_to_jiffies(vreg->ocp_retry_delay_ms) + 1); | |
1318 | } else { | |
1319 | dev_err(vreg->dev, | |
1320 | "OCP triggered %d times; no further retries\n", | |
1321 | vreg->ocp_count); | |
1322 | } | |
1323 | ||
1324 | return IRQ_HANDLED; | |
1325 | } | |
1326 | ||
0caecaa8 IL |
1327 | #define SAW3_VCTL_DATA_MASK 0xFF |
1328 | #define SAW3_VCTL_CLEAR_MASK 0x700FF | |
1329 | #define SAW3_AVS_CTL_EN_MASK 0x1 | |
1330 | #define SAW3_AVS_CTL_TGGL_MASK 0x8000000 | |
1331 | #define SAW3_AVS_CTL_CLEAR_MASK 0x7efc00 | |
1332 | ||
9689ca0a | 1333 | static struct regmap *saw_regmap; |
0caecaa8 IL |
1334 | |
1335 | static void spmi_saw_set_vdd(void *data) | |
1336 | { | |
1337 | u32 vctl, data3, avs_ctl, pmic_sts; | |
1338 | bool avs_enabled = false; | |
1339 | unsigned long timeout; | |
1340 | u8 voltage_sel = *(u8 *)data; | |
1341 | ||
1342 | regmap_read(saw_regmap, SAW3_AVS_CTL, &avs_ctl); | |
1343 | regmap_read(saw_regmap, SAW3_VCTL, &vctl); | |
1344 | regmap_read(saw_regmap, SAW3_SPM_PMIC_DATA_3, &data3); | |
1345 | ||
1346 | /* select the band */ | |
1347 | vctl &= ~SAW3_VCTL_CLEAR_MASK; | |
1348 | vctl |= (u32)voltage_sel; | |
1349 | ||
1350 | data3 &= ~SAW3_VCTL_CLEAR_MASK; | |
1351 | data3 |= (u32)voltage_sel; | |
1352 | ||
1353 | /* If AVS is enabled, switch it off during the voltage change */ | |
1354 | avs_enabled = SAW3_AVS_CTL_EN_MASK & avs_ctl; | |
1355 | if (avs_enabled) { | |
1356 | avs_ctl &= ~SAW3_AVS_CTL_TGGL_MASK; | |
1357 | regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl); | |
1358 | } | |
1359 | ||
1360 | regmap_write(saw_regmap, SAW3_RST, 1); | |
1361 | regmap_write(saw_regmap, SAW3_VCTL, vctl); | |
1362 | regmap_write(saw_regmap, SAW3_SPM_PMIC_DATA_3, data3); | |
1363 | ||
1364 | timeout = jiffies + usecs_to_jiffies(100); | |
1365 | do { | |
1366 | regmap_read(saw_regmap, SAW3_PMIC_STS, &pmic_sts); | |
1367 | pmic_sts &= SAW3_VCTL_DATA_MASK; | |
1368 | if (pmic_sts == (u32)voltage_sel) | |
1369 | break; | |
1370 | ||
1371 | cpu_relax(); | |
1372 | ||
1373 | } while (time_before(jiffies, timeout)); | |
1374 | ||
1375 | /* After successful voltage change, switch the AVS back on */ | |
1376 | if (avs_enabled) { | |
1377 | pmic_sts &= 0x3f; | |
1378 | avs_ctl &= ~SAW3_AVS_CTL_CLEAR_MASK; | |
1379 | avs_ctl |= ((pmic_sts - 4) << 10); | |
1380 | avs_ctl |= (pmic_sts << 17); | |
1381 | avs_ctl |= SAW3_AVS_CTL_TGGL_MASK; | |
1382 | regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl); | |
1383 | } | |
1384 | } | |
1385 | ||
1386 | static int | |
1387 | spmi_regulator_saw_set_voltage(struct regulator_dev *rdev, unsigned selector) | |
1388 | { | |
1389 | struct spmi_regulator *vreg = rdev_get_drvdata(rdev); | |
1390 | int ret; | |
1391 | u8 range_sel, voltage_sel; | |
1392 | ||
1393 | ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel); | |
1394 | if (ret) | |
1395 | return ret; | |
1396 | ||
1397 | if (0 != range_sel) { | |
1398 | dev_dbg(&rdev->dev, "range_sel = %02X voltage_sel = %02X", \ | |
1399 | range_sel, voltage_sel); | |
1400 | return -EINVAL; | |
1401 | } | |
1402 | ||
1403 | /* Always do the SAW register writes on the first CPU */ | |
1404 | return smp_call_function_single(0, spmi_saw_set_vdd, \ | |
1405 | &voltage_sel, true); | |
1406 | } | |
1407 | ||
1408 | static struct regulator_ops spmi_saw_ops = {}; | |
1409 | ||
3b619e3e | 1410 | static const struct regulator_ops spmi_smps_ops = { |
9d485332 AL |
1411 | .enable = regulator_enable_regmap, |
1412 | .disable = regulator_disable_regmap, | |
1413 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 | 1414 | .set_voltage_sel = spmi_regulator_common_set_voltage, |
2cf7b99c | 1415 | .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, |
1b5b1968 SB |
1416 | .get_voltage_sel = spmi_regulator_common_get_voltage, |
1417 | .map_voltage = spmi_regulator_common_map_voltage, | |
e92a4047 SB |
1418 | .list_voltage = spmi_regulator_common_list_voltage, |
1419 | .set_mode = spmi_regulator_common_set_mode, | |
1420 | .get_mode = spmi_regulator_common_get_mode, | |
1421 | .set_load = spmi_regulator_common_set_load, | |
1422 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1423 | }; | |
1424 | ||
3b619e3e | 1425 | static const struct regulator_ops spmi_ldo_ops = { |
9d485332 AL |
1426 | .enable = regulator_enable_regmap, |
1427 | .disable = regulator_disable_regmap, | |
1428 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 SB |
1429 | .set_voltage_sel = spmi_regulator_common_set_voltage, |
1430 | .get_voltage_sel = spmi_regulator_common_get_voltage, | |
1431 | .map_voltage = spmi_regulator_common_map_voltage, | |
e92a4047 SB |
1432 | .list_voltage = spmi_regulator_common_list_voltage, |
1433 | .set_mode = spmi_regulator_common_set_mode, | |
1434 | .get_mode = spmi_regulator_common_get_mode, | |
1435 | .set_load = spmi_regulator_common_set_load, | |
1436 | .set_bypass = spmi_regulator_common_set_bypass, | |
1437 | .get_bypass = spmi_regulator_common_get_bypass, | |
1438 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1439 | .set_soft_start = spmi_regulator_common_set_soft_start, | |
1440 | }; | |
1441 | ||
3b619e3e | 1442 | static const struct regulator_ops spmi_ln_ldo_ops = { |
9d485332 AL |
1443 | .enable = regulator_enable_regmap, |
1444 | .disable = regulator_disable_regmap, | |
1445 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 SB |
1446 | .set_voltage_sel = spmi_regulator_common_set_voltage, |
1447 | .get_voltage_sel = spmi_regulator_common_get_voltage, | |
1448 | .map_voltage = spmi_regulator_common_map_voltage, | |
e92a4047 SB |
1449 | .list_voltage = spmi_regulator_common_list_voltage, |
1450 | .set_bypass = spmi_regulator_common_set_bypass, | |
1451 | .get_bypass = spmi_regulator_common_get_bypass, | |
1452 | }; | |
1453 | ||
3b619e3e | 1454 | static const struct regulator_ops spmi_vs_ops = { |
e92a4047 | 1455 | .enable = spmi_regulator_vs_enable, |
9d485332 AL |
1456 | .disable = regulator_disable_regmap, |
1457 | .is_enabled = regulator_is_enabled_regmap, | |
e92a4047 SB |
1458 | .set_pull_down = spmi_regulator_common_set_pull_down, |
1459 | .set_soft_start = spmi_regulator_common_set_soft_start, | |
e2adfacd | 1460 | .set_over_current_protection = spmi_regulator_vs_ocp, |
919163f6 SB |
1461 | .set_mode = spmi_regulator_common_set_mode, |
1462 | .get_mode = spmi_regulator_common_get_mode, | |
e92a4047 SB |
1463 | }; |
1464 | ||
3b619e3e | 1465 | static const struct regulator_ops spmi_boost_ops = { |
9d485332 AL |
1466 | .enable = regulator_enable_regmap, |
1467 | .disable = regulator_disable_regmap, | |
1468 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 SB |
1469 | .set_voltage_sel = spmi_regulator_single_range_set_voltage, |
1470 | .get_voltage_sel = spmi_regulator_single_range_get_voltage, | |
1471 | .map_voltage = spmi_regulator_single_map_voltage, | |
e92a4047 SB |
1472 | .list_voltage = spmi_regulator_common_list_voltage, |
1473 | .set_input_current_limit = spmi_regulator_set_ilim, | |
1474 | }; | |
1475 | ||
3b619e3e | 1476 | static const struct regulator_ops spmi_ftsmps_ops = { |
9d485332 AL |
1477 | .enable = regulator_enable_regmap, |
1478 | .disable = regulator_disable_regmap, | |
1479 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 | 1480 | .set_voltage_sel = spmi_regulator_common_set_voltage, |
e92a4047 | 1481 | .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, |
1b5b1968 SB |
1482 | .get_voltage_sel = spmi_regulator_common_get_voltage, |
1483 | .map_voltage = spmi_regulator_common_map_voltage, | |
e92a4047 SB |
1484 | .list_voltage = spmi_regulator_common_list_voltage, |
1485 | .set_mode = spmi_regulator_common_set_mode, | |
1486 | .get_mode = spmi_regulator_common_get_mode, | |
1487 | .set_load = spmi_regulator_common_set_load, | |
1488 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1489 | }; | |
1490 | ||
3b619e3e | 1491 | static const struct regulator_ops spmi_ult_lo_smps_ops = { |
9d485332 AL |
1492 | .enable = regulator_enable_regmap, |
1493 | .disable = regulator_disable_regmap, | |
1494 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 | 1495 | .set_voltage_sel = spmi_regulator_ult_lo_smps_set_voltage, |
2cf7b99c | 1496 | .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, |
1b5b1968 | 1497 | .get_voltage_sel = spmi_regulator_ult_lo_smps_get_voltage, |
e92a4047 SB |
1498 | .list_voltage = spmi_regulator_common_list_voltage, |
1499 | .set_mode = spmi_regulator_common_set_mode, | |
1500 | .get_mode = spmi_regulator_common_get_mode, | |
1501 | .set_load = spmi_regulator_common_set_load, | |
1502 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1503 | }; | |
1504 | ||
3b619e3e | 1505 | static const struct regulator_ops spmi_ult_ho_smps_ops = { |
9d485332 AL |
1506 | .enable = regulator_enable_regmap, |
1507 | .disable = regulator_disable_regmap, | |
1508 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 | 1509 | .set_voltage_sel = spmi_regulator_single_range_set_voltage, |
2cf7b99c | 1510 | .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, |
1b5b1968 SB |
1511 | .get_voltage_sel = spmi_regulator_single_range_get_voltage, |
1512 | .map_voltage = spmi_regulator_single_map_voltage, | |
e92a4047 SB |
1513 | .list_voltage = spmi_regulator_common_list_voltage, |
1514 | .set_mode = spmi_regulator_common_set_mode, | |
1515 | .get_mode = spmi_regulator_common_get_mode, | |
1516 | .set_load = spmi_regulator_common_set_load, | |
1517 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1518 | }; | |
1519 | ||
3b619e3e | 1520 | static const struct regulator_ops spmi_ult_ldo_ops = { |
9d485332 AL |
1521 | .enable = regulator_enable_regmap, |
1522 | .disable = regulator_disable_regmap, | |
1523 | .is_enabled = regulator_is_enabled_regmap, | |
1b5b1968 SB |
1524 | .set_voltage_sel = spmi_regulator_single_range_set_voltage, |
1525 | .get_voltage_sel = spmi_regulator_single_range_get_voltage, | |
1526 | .map_voltage = spmi_regulator_single_map_voltage, | |
e92a4047 SB |
1527 | .list_voltage = spmi_regulator_common_list_voltage, |
1528 | .set_mode = spmi_regulator_common_set_mode, | |
1529 | .get_mode = spmi_regulator_common_get_mode, | |
1530 | .set_load = spmi_regulator_common_set_load, | |
1531 | .set_bypass = spmi_regulator_common_set_bypass, | |
1532 | .get_bypass = spmi_regulator_common_get_bypass, | |
1533 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1534 | .set_soft_start = spmi_regulator_common_set_soft_start, | |
1535 | }; | |
1536 | ||
3b619e3e | 1537 | static const struct regulator_ops spmi_ftsmps426_ops = { |
42ba89c8 JH |
1538 | .enable = regulator_enable_regmap, |
1539 | .disable = regulator_disable_regmap, | |
1540 | .is_enabled = regulator_is_enabled_regmap, | |
1541 | .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, | |
1542 | .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, | |
1543 | .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, | |
1544 | .map_voltage = spmi_regulator_single_map_voltage, | |
1545 | .list_voltage = spmi_regulator_common_list_voltage, | |
1546 | .set_mode = spmi_regulator_ftsmps426_set_mode, | |
1547 | .get_mode = spmi_regulator_ftsmps426_get_mode, | |
1548 | .set_load = spmi_regulator_common_set_load, | |
1549 | .set_pull_down = spmi_regulator_common_set_pull_down, | |
1550 | }; | |
1551 | ||
3b619e3e | 1552 | static const struct regulator_ops spmi_hfs430_ops = { |
0211f68e JR |
1553 | .enable = regulator_enable_regmap, |
1554 | .disable = regulator_disable_regmap, | |
1555 | .is_enabled = regulator_is_enabled_regmap, | |
1556 | .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, | |
1557 | .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, | |
1558 | .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, | |
1559 | .map_voltage = spmi_regulator_single_map_voltage, | |
1560 | .list_voltage = spmi_regulator_common_list_voltage, | |
1561 | .set_mode = spmi_regulator_ftsmps426_set_mode, | |
1562 | .get_mode = spmi_regulator_ftsmps426_get_mode, | |
1563 | }; | |
1564 | ||
27850254 IC |
1565 | static const struct regulator_ops spmi_hfsmps_ops = { |
1566 | .enable = regulator_enable_regmap, | |
1567 | .disable = regulator_disable_regmap, | |
1568 | .is_enabled = regulator_is_enabled_regmap, | |
1569 | .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage, | |
1570 | .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel, | |
1571 | .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage, | |
1572 | .map_voltage = spmi_regulator_single_map_voltage, | |
1573 | .list_voltage = spmi_regulator_common_list_voltage, | |
1574 | .set_mode = spmi_regulator_hfsmps_set_mode, | |
1575 | .get_mode = spmi_regulator_hfsmps_get_mode, | |
1576 | .set_load = spmi_regulator_common_set_load, | |
1577 | .set_pull_down = spmi_regulator_hfsmps_set_pull_down, | |
1578 | }; | |
1579 | ||
e92a4047 SB |
1580 | /* Maximum possible digital major revision value */ |
1581 | #define INF 0xFF | |
1582 | ||
1583 | static const struct spmi_regulator_mapping supported_regulators[] = { | |
1584 | /* type subtype dig_min dig_max ltype ops setpoints hpm_min */ | |
3d04ae8e | 1585 | SPMI_VREG(LDO, HT_P600, 0, INF, HFS430, hfs430, ht_p600, 10000), |
00f6ebbd | 1586 | SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000), |
e92a4047 | 1587 | SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000), |
27850254 IC |
1588 | SPMI_VREG(BUCK, HFS430, 0, 3, HFS430, hfs430, hfs430, 10000), |
1589 | SPMI_VREG(BUCK, HFSMPS_510, 4, INF, HFSMPS, hfsmps, hfs430, 100000), | |
e92a4047 SB |
1590 | SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000), |
1591 | SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000), | |
1592 | SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000), | |
1593 | SPMI_VREG(LDO, N600, 1, INF, LDO, ldo, nldo3, 10000), | |
1594 | SPMI_VREG(LDO, N1200, 1, INF, LDO, ldo, nldo3, 10000), | |
1595 | SPMI_VREG(LDO, N600_ST, 0, 0, LDO, ldo, nldo2, 10000), | |
1596 | SPMI_VREG(LDO, N1200_ST, 0, 0, LDO, ldo, nldo2, 10000), | |
1597 | SPMI_VREG(LDO, N600_ST, 1, INF, LDO, ldo, nldo3, 10000), | |
1598 | SPMI_VREG(LDO, N1200_ST, 1, INF, LDO, ldo, nldo3, 10000), | |
1599 | SPMI_VREG(LDO, P50, 0, INF, LDO, ldo, pldo, 5000), | |
1600 | SPMI_VREG(LDO, P150, 0, INF, LDO, ldo, pldo, 10000), | |
1601 | SPMI_VREG(LDO, P300, 0, INF, LDO, ldo, pldo, 10000), | |
1602 | SPMI_VREG(LDO, P600, 0, INF, LDO, ldo, pldo, 10000), | |
1603 | SPMI_VREG(LDO, P1200, 0, INF, LDO, ldo, pldo, 10000), | |
1604 | SPMI_VREG(LDO, LN, 0, INF, LN_LDO, ln_ldo, ln_ldo, 0), | |
1605 | SPMI_VREG(LDO, LV_P50, 0, INF, LDO, ldo, pldo, 5000), | |
1606 | SPMI_VREG(LDO, LV_P150, 0, INF, LDO, ldo, pldo, 10000), | |
1607 | SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000), | |
1608 | SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000), | |
1609 | SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000), | |
328816c2 ADR |
1610 | SPMI_VREG(LDO, HT_N300_ST, 0, INF, FTSMPS426, ftsmps426, |
1611 | ht_nldo, 30000), | |
1612 | SPMI_VREG(LDO, HT_N600_ST, 0, INF, FTSMPS426, ftsmps426, | |
1613 | ht_nldo, 30000), | |
1614 | SPMI_VREG(LDO, HT_N1200_ST, 0, INF, FTSMPS426, ftsmps426, | |
1615 | ht_nldo, 30000), | |
1616 | SPMI_VREG(LDO, HT_LVP150, 0, INF, FTSMPS426, ftsmps426, | |
1617 | ht_lvpldo, 10000), | |
1618 | SPMI_VREG(LDO, HT_LVP300, 0, INF, FTSMPS426, ftsmps426, | |
1619 | ht_lvpldo, 10000), | |
1620 | SPMI_VREG(LDO, L660_N300_ST, 0, INF, FTSMPS426, ftsmps426, | |
1621 | nldo660, 10000), | |
1622 | SPMI_VREG(LDO, L660_N600_ST, 0, INF, FTSMPS426, ftsmps426, | |
1623 | nldo660, 10000), | |
1624 | SPMI_VREG(LDO, L660_P50, 0, INF, FTSMPS426, ftsmps426, | |
1625 | pldo660, 10000), | |
1626 | SPMI_VREG(LDO, L660_P150, 0, INF, FTSMPS426, ftsmps426, | |
1627 | pldo660, 10000), | |
1628 | SPMI_VREG(LDO, L660_P600, 0, INF, FTSMPS426, ftsmps426, | |
1629 | pldo660, 10000), | |
1630 | SPMI_VREG(LDO, L660_LVP150, 0, INF, FTSMPS426, ftsmps426, | |
1631 | ht_lvpldo, 10000), | |
1632 | SPMI_VREG(LDO, L660_LVP600, 0, INF, FTSMPS426, ftsmps426, | |
1633 | ht_lvpldo, 10000), | |
e92a4047 SB |
1634 | SPMI_VREG_VS(LV100, 0, INF), |
1635 | SPMI_VREG_VS(LV300, 0, INF), | |
1636 | SPMI_VREG_VS(MV300, 0, INF), | |
1637 | SPMI_VREG_VS(MV500, 0, INF), | |
1638 | SPMI_VREG_VS(HDMI, 0, INF), | |
1639 | SPMI_VREG_VS(OTG, 0, INF), | |
1640 | SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0), | |
1641 | SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000), | |
1642 | SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000), | |
42ba89c8 | 1643 | SPMI_VREG(FTS, FTS426_CTL, 0, INF, FTSMPS426, ftsmps426, ftsmps426, 100000), |
e92a4047 SB |
1644 | SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0), |
1645 | SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps, | |
1646 | ult_lo_smps, 100000), | |
1647 | SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps, | |
1648 | ult_lo_smps, 100000), | |
1649 | SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps, | |
1650 | ult_lo_smps, 100000), | |
1651 | SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps, | |
1652 | ult_ho_smps, 100000), | |
1653 | SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), | |
1654 | SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), | |
1655 | SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), | |
1656 | SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000), | |
438421b0 | 1657 | SPMI_VREG(ULT_LDO, LV_P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), |
e92a4047 SB |
1658 | SPMI_VREG(ULT_LDO, LV_P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), |
1659 | SPMI_VREG(ULT_LDO, LV_P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), | |
1660 | SPMI_VREG(ULT_LDO, LV_P450, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), | |
1661 | SPMI_VREG(ULT_LDO, P600, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), | |
438421b0 | 1662 | SPMI_VREG(ULT_LDO, P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), |
e92a4047 SB |
1663 | SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000), |
1664 | SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000), | |
0d1cf568 IC |
1665 | SPMI_VREG(LDO, LV_P150_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000), |
1666 | SPMI_VREG(LDO, LV_P300_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000), | |
1667 | SPMI_VREG(LDO, LV_P600_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000), | |
1668 | SPMI_VREG(LDO, MV_P50_510, 0, INF, LDO_510, hfsmps, pldo660, 10000), | |
1669 | SPMI_VREG(LDO, MV_P150_510, 0, INF, LDO_510, hfsmps, pldo660, 10000), | |
1670 | SPMI_VREG(LDO, MV_P600_510, 0, INF, LDO_510, hfsmps, pldo660, 10000), | |
1671 | SPMI_VREG(LDO, N300_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000), | |
1672 | SPMI_VREG(LDO, N600_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000), | |
1673 | SPMI_VREG(LDO, N1200_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000), | |
1674 | SPMI_VREG(FTS, FTSMPS_510, 0, INF, FTSMPS3, hfsmps, ftsmps510, 100000), | |
e92a4047 SB |
1675 | }; |
1676 | ||
1677 | static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points) | |
1678 | { | |
1679 | unsigned int n; | |
1680 | struct spmi_voltage_range *range = points->range; | |
1681 | ||
1682 | for (; range < points->range + points->count; range++) { | |
1683 | n = 0; | |
1684 | if (range->set_point_max_uV) { | |
1685 | n = range->set_point_max_uV - range->set_point_min_uV; | |
419d06a1 | 1686 | n = (n / range->step_uV) + 1; |
e92a4047 SB |
1687 | } |
1688 | range->n_voltages = n; | |
1689 | points->n_voltages += n; | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type) | |
1694 | { | |
1695 | const struct spmi_regulator_mapping *mapping; | |
1696 | int ret, i; | |
1697 | u32 dig_major_rev; | |
1698 | u8 version[SPMI_COMMON_REG_SUBTYPE - SPMI_COMMON_REG_DIG_MAJOR_REV + 1]; | |
1699 | u8 type, subtype; | |
1700 | ||
1701 | ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_DIG_MAJOR_REV, version, | |
1702 | ARRAY_SIZE(version)); | |
1703 | if (ret) { | |
6ee5c044 | 1704 | dev_dbg(vreg->dev, "could not read version registers\n"); |
e92a4047 SB |
1705 | return ret; |
1706 | } | |
1707 | dig_major_rev = version[SPMI_COMMON_REG_DIG_MAJOR_REV | |
1708 | - SPMI_COMMON_REG_DIG_MAJOR_REV]; | |
0caecaa8 | 1709 | |
e92a4047 SB |
1710 | if (!force_type) { |
1711 | type = version[SPMI_COMMON_REG_TYPE - | |
1712 | SPMI_COMMON_REG_DIG_MAJOR_REV]; | |
1713 | subtype = version[SPMI_COMMON_REG_SUBTYPE - | |
1714 | SPMI_COMMON_REG_DIG_MAJOR_REV]; | |
1715 | } else { | |
1716 | type = force_type >> 8; | |
1717 | subtype = force_type; | |
1718 | } | |
1719 | ||
1720 | for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) { | |
1721 | mapping = &supported_regulators[i]; | |
1722 | if (mapping->type == type && mapping->subtype == subtype | |
1723 | && mapping->revision_min <= dig_major_rev | |
1724 | && mapping->revision_max >= dig_major_rev) | |
1725 | goto found; | |
1726 | } | |
1727 | ||
1728 | dev_err(vreg->dev, | |
1729 | "unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n", | |
1730 | vreg->desc.name, type, subtype, dig_major_rev); | |
1731 | ||
1732 | return -ENODEV; | |
1733 | ||
1734 | found: | |
1735 | vreg->logical_type = mapping->logical_type; | |
1736 | vreg->set_points = mapping->set_points; | |
1737 | vreg->hpm_min_load = mapping->hpm_min_load; | |
1738 | vreg->desc.ops = mapping->ops; | |
1739 | ||
1740 | if (mapping->set_points) { | |
1741 | if (!mapping->set_points->n_voltages) | |
1742 | spmi_calculate_num_voltages(mapping->set_points); | |
1743 | vreg->desc.n_voltages = mapping->set_points->n_voltages; | |
1744 | } | |
1745 | ||
1746 | return 0; | |
1747 | } | |
1748 | ||
2cf7b99c | 1749 | static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg) |
e92a4047 SB |
1750 | { |
1751 | int ret; | |
1752 | u8 reg = 0; | |
2cf7b99c | 1753 | int step, delay, slew_rate, step_delay; |
e92a4047 SB |
1754 | const struct spmi_voltage_range *range; |
1755 | ||
1756 | ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); | |
1757 | if (ret) { | |
1758 | dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); | |
1759 | return ret; | |
1760 | } | |
1761 | ||
1762 | range = spmi_regulator_find_range(vreg); | |
1763 | if (!range) | |
1764 | return -EINVAL; | |
1765 | ||
2cf7b99c SB |
1766 | switch (vreg->logical_type) { |
1767 | case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS: | |
1768 | step_delay = SPMI_FTSMPS_STEP_DELAY; | |
1769 | break; | |
1770 | default: | |
1771 | step_delay = SPMI_DEFAULT_STEP_DELAY; | |
1772 | break; | |
1773 | } | |
1774 | ||
e92a4047 SB |
1775 | step = reg & SPMI_FTSMPS_STEP_CTRL_STEP_MASK; |
1776 | step >>= SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT; | |
1777 | ||
1778 | delay = reg & SPMI_FTSMPS_STEP_CTRL_DELAY_MASK; | |
1779 | delay >>= SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT; | |
1780 | ||
1781 | /* slew_rate has units of uV/us */ | |
1782 | slew_rate = SPMI_FTSMPS_CLOCK_RATE * range->step_uV * (1 << step); | |
2cf7b99c | 1783 | slew_rate /= 1000 * (step_delay << delay); |
e92a4047 SB |
1784 | slew_rate *= SPMI_FTSMPS_STEP_MARGIN_NUM; |
1785 | slew_rate /= SPMI_FTSMPS_STEP_MARGIN_DEN; | |
1786 | ||
1787 | /* Ensure that the slew rate is greater than 0 */ | |
1788 | vreg->slew_rate = max(slew_rate, 1); | |
1789 | ||
1790 | return ret; | |
1791 | } | |
1792 | ||
0211f68e JR |
1793 | static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg, |
1794 | int clock_rate) | |
42ba89c8 JH |
1795 | { |
1796 | int ret; | |
1797 | u8 reg = 0; | |
1798 | int delay, slew_rate; | |
1799 | const struct spmi_voltage_range *range = &vreg->set_points->range[0]; | |
1800 | ||
1801 | ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1); | |
1802 | if (ret) { | |
1803 | dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); | |
1804 | return ret; | |
1805 | } | |
1806 | ||
1807 | delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK; | |
1808 | delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT; | |
1809 | ||
1810 | /* slew_rate has units of uV/us */ | |
0211f68e | 1811 | slew_rate = clock_rate * range->step_uV; |
42ba89c8 JH |
1812 | slew_rate /= 1000 * (SPMI_FTSMPS426_STEP_DELAY << delay); |
1813 | slew_rate *= SPMI_FTSMPS426_STEP_MARGIN_NUM; | |
1814 | slew_rate /= SPMI_FTSMPS426_STEP_MARGIN_DEN; | |
1815 | ||
1816 | /* Ensure that the slew rate is greater than 0 */ | |
1817 | vreg->slew_rate = max(slew_rate, 1); | |
1818 | ||
1819 | return ret; | |
1820 | } | |
1821 | ||
27850254 IC |
1822 | static int spmi_regulator_init_slew_rate_hfsmps(struct spmi_regulator *vreg) |
1823 | { | |
1824 | int ret; | |
1825 | u8 reg = 0; | |
1826 | int delay; | |
1827 | ||
1828 | ret = spmi_vreg_read(vreg, SPMI_HFSMPS_REG_STEP_CTRL, ®, 1); | |
1829 | if (ret) { | |
1830 | dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret); | |
1831 | return ret; | |
1832 | } | |
1833 | ||
1834 | delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK; | |
1835 | delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT; | |
1836 | ||
1837 | vreg->slew_rate = SPMI_HFSMPS_SLEW_RATE_38p4 >> delay; | |
1838 | ||
1839 | return ret; | |
1840 | } | |
1841 | ||
e2adfacd SB |
1842 | static int spmi_regulator_init_registers(struct spmi_regulator *vreg, |
1843 | const struct spmi_regulator_init_data *data) | |
1844 | { | |
1845 | int ret; | |
1846 | enum spmi_regulator_logical_type type; | |
1847 | u8 ctrl_reg[8], reg, mask; | |
1848 | ||
1849 | type = vreg->logical_type; | |
1850 | ||
1851 | ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8); | |
1852 | if (ret) | |
1853 | return ret; | |
1854 | ||
1855 | /* Set up enable pin control. */ | |
6a1fe83b AL |
1856 | if (!(data->pin_ctrl_enable & SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT)) { |
1857 | switch (type) { | |
1858 | case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: | |
1859 | case SPMI_REGULATOR_LOGICAL_TYPE_LDO: | |
1860 | case SPMI_REGULATOR_LOGICAL_TYPE_VS: | |
1861 | ctrl_reg[SPMI_COMMON_IDX_ENABLE] &= | |
1862 | ~SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK; | |
1863 | ctrl_reg[SPMI_COMMON_IDX_ENABLE] |= | |
1864 | data->pin_ctrl_enable & SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK; | |
1865 | break; | |
1866 | default: | |
1867 | break; | |
1868 | } | |
e2adfacd SB |
1869 | } |
1870 | ||
1871 | /* Set up mode pin control. */ | |
6a1fe83b AL |
1872 | if (!(data->pin_ctrl_hpm & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) { |
1873 | switch (type) { | |
1874 | case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: | |
1875 | case SPMI_REGULATOR_LOGICAL_TYPE_LDO: | |
1876 | ctrl_reg[SPMI_COMMON_IDX_MODE] &= | |
1877 | ~SPMI_COMMON_MODE_FOLLOW_ALL_MASK; | |
1878 | ctrl_reg[SPMI_COMMON_IDX_MODE] |= | |
1879 | data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_ALL_MASK; | |
1880 | break; | |
1881 | case SPMI_REGULATOR_LOGICAL_TYPE_VS: | |
1882 | case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS: | |
1883 | case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS: | |
1884 | case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO: | |
1885 | ctrl_reg[SPMI_COMMON_IDX_MODE] &= | |
1886 | ~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK; | |
1887 | ctrl_reg[SPMI_COMMON_IDX_MODE] |= | |
1888 | data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK; | |
1889 | break; | |
1890 | default: | |
1891 | break; | |
1892 | } | |
e2adfacd SB |
1893 | } |
1894 | ||
1895 | /* Write back any control register values that were modified. */ | |
1896 | ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8); | |
1897 | if (ret) | |
1898 | return ret; | |
1899 | ||
1900 | /* Set soft start strength and over current protection for VS. */ | |
1901 | if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS) { | |
1902 | if (data->vs_soft_start_strength | |
1903 | != SPMI_VS_SOFT_START_STR_HW_DEFAULT) { | |
1904 | reg = data->vs_soft_start_strength | |
1905 | & SPMI_VS_SOFT_START_SEL_MASK; | |
1906 | mask = SPMI_VS_SOFT_START_SEL_MASK; | |
1907 | return spmi_vreg_update_bits(vreg, | |
1908 | SPMI_VS_REG_SOFT_START, | |
1909 | reg, mask); | |
1910 | } | |
1911 | } | |
1912 | ||
1913 | return 0; | |
1914 | } | |
1915 | ||
1916 | static void spmi_regulator_get_dt_config(struct spmi_regulator *vreg, | |
1917 | struct device_node *node, struct spmi_regulator_init_data *data) | |
1918 | { | |
1919 | /* | |
1920 | * Initialize configuration parameters to use hardware default in case | |
1921 | * no value is specified via device tree. | |
1922 | */ | |
1923 | data->pin_ctrl_enable = SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT; | |
1924 | data->pin_ctrl_hpm = SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT; | |
1925 | data->vs_soft_start_strength = SPMI_VS_SOFT_START_STR_HW_DEFAULT; | |
1926 | ||
1927 | /* These bindings are optional, so it is okay if they aren't found. */ | |
1928 | of_property_read_u32(node, "qcom,ocp-max-retries", | |
1929 | &vreg->ocp_max_retries); | |
1930 | of_property_read_u32(node, "qcom,ocp-retry-delay", | |
1931 | &vreg->ocp_retry_delay_ms); | |
1932 | of_property_read_u32(node, "qcom,pin-ctrl-enable", | |
1933 | &data->pin_ctrl_enable); | |
1934 | of_property_read_u32(node, "qcom,pin-ctrl-hpm", &data->pin_ctrl_hpm); | |
1935 | of_property_read_u32(node, "qcom,vs-soft-start-strength", | |
1936 | &data->vs_soft_start_strength); | |
1937 | } | |
1938 | ||
e92a4047 SB |
1939 | static unsigned int spmi_regulator_of_map_mode(unsigned int mode) |
1940 | { | |
e2adfacd | 1941 | if (mode == 1) |
e92a4047 | 1942 | return REGULATOR_MODE_NORMAL; |
e2adfacd SB |
1943 | if (mode == 2) |
1944 | return REGULATOR_MODE_FAST; | |
e92a4047 SB |
1945 | |
1946 | return REGULATOR_MODE_IDLE; | |
1947 | } | |
1948 | ||
1949 | static int spmi_regulator_of_parse(struct device_node *node, | |
1950 | const struct regulator_desc *desc, | |
1951 | struct regulator_config *config) | |
1952 | { | |
e2adfacd | 1953 | struct spmi_regulator_init_data data = { }; |
e92a4047 SB |
1954 | struct spmi_regulator *vreg = config->driver_data; |
1955 | struct device *dev = config->dev; | |
1956 | int ret; | |
1957 | ||
e2adfacd SB |
1958 | spmi_regulator_get_dt_config(vreg, node, &data); |
1959 | ||
1960 | if (!vreg->ocp_max_retries) | |
1961 | vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES; | |
1962 | if (!vreg->ocp_retry_delay_ms) | |
1963 | vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS; | |
1964 | ||
1965 | ret = spmi_regulator_init_registers(vreg, &data); | |
1966 | if (ret) { | |
1967 | dev_err(dev, "common initialization failed, ret=%d\n", ret); | |
1968 | return ret; | |
1969 | } | |
e92a4047 | 1970 | |
2cf7b99c SB |
1971 | switch (vreg->logical_type) { |
1972 | case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS: | |
1973 | case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS: | |
1974 | case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS: | |
1975 | case SPMI_REGULATOR_LOGICAL_TYPE_SMPS: | |
1976 | ret = spmi_regulator_init_slew_rate(vreg); | |
e92a4047 SB |
1977 | if (ret) |
1978 | return ret; | |
42ba89c8 JH |
1979 | break; |
1980 | case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426: | |
0211f68e JR |
1981 | ret = spmi_regulator_init_slew_rate_ftsmps426(vreg, |
1982 | SPMI_FTSMPS426_CLOCK_RATE); | |
1983 | if (ret) | |
1984 | return ret; | |
1985 | break; | |
1986 | case SPMI_REGULATOR_LOGICAL_TYPE_HFS430: | |
1987 | ret = spmi_regulator_init_slew_rate_ftsmps426(vreg, | |
1988 | SPMI_HFS430_CLOCK_RATE); | |
42ba89c8 JH |
1989 | if (ret) |
1990 | return ret; | |
1991 | break; | |
27850254 | 1992 | case SPMI_REGULATOR_LOGICAL_TYPE_HFSMPS: |
0d1cf568 | 1993 | case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3: |
27850254 IC |
1994 | ret = spmi_regulator_init_slew_rate_hfsmps(vreg); |
1995 | if (ret) | |
1996 | return ret; | |
1997 | break; | |
2cf7b99c SB |
1998 | default: |
1999 | break; | |
e92a4047 SB |
2000 | } |
2001 | ||
2002 | if (vreg->logical_type != SPMI_REGULATOR_LOGICAL_TYPE_VS) | |
2003 | vreg->ocp_irq = 0; | |
2004 | ||
2005 | if (vreg->ocp_irq) { | |
2006 | ret = devm_request_irq(dev, vreg->ocp_irq, | |
2007 | spmi_regulator_vs_ocp_isr, IRQF_TRIGGER_RISING, "ocp", | |
2008 | vreg); | |
2009 | if (ret < 0) { | |
2010 | dev_err(dev, "failed to request irq %d, ret=%d\n", | |
2011 | vreg->ocp_irq, ret); | |
2012 | return ret; | |
2013 | } | |
2014 | ||
b6688015 MV |
2015 | ret = devm_delayed_work_autocancel(dev, &vreg->ocp_work, |
2016 | spmi_regulator_vs_ocp_work); | |
2017 | if (ret) | |
2018 | return ret; | |
e92a4047 SB |
2019 | } |
2020 | ||
2021 | return 0; | |
2022 | } | |
2023 | ||
e62ef4a9 IC |
2024 | static const struct spmi_regulator_data pm6125_regulators[] = { |
2025 | { "s1", 0x1400, "vdd_s1" }, | |
2026 | { "s2", 0x1700, "vdd_s2" }, | |
2027 | { "s3", 0x1a00, "vdd_s3" }, | |
2028 | { "s4", 0x1d00, "vdd_s4" }, | |
2029 | { "s5", 0x2000, "vdd_s5" }, | |
2030 | { "s6", 0x2300, "vdd_s6" }, | |
2031 | { "s7", 0x2600, "vdd_s7" }, | |
2032 | { "s8", 0x2900, "vdd_s8" }, | |
2033 | { "l1", 0x4000, "vdd_l1_l7_l17_l18" }, | |
2034 | { "l2", 0x4100, "vdd_l2_l3_l4" }, | |
2035 | { "l3", 0x4200, "vdd_l2_l3_l4" }, | |
2036 | { "l4", 0x4300, "vdd_l2_l3_l4" }, | |
2037 | { "l5", 0x4400, "vdd_l5_l15_l19_l20_l21_l22" }, | |
2038 | { "l6", 0x4500, "vdd_l6_l8" }, | |
2039 | { "l7", 0x4600, "vdd_l1_l7_l17_l18" }, | |
2040 | { "l8", 0x4700, "vdd_l6_l8" }, | |
2041 | { "l9", 0x4800, "vdd_l9_l11" }, | |
2042 | { "l10", 0x4900, "vdd_l10_l13_l14" }, | |
2043 | { "l11", 0x4a00, "vdd_l9_l11" }, | |
2044 | { "l12", 0x4b00, "vdd_l12_l16" }, | |
2045 | { "l13", 0x4c00, "vdd_l10_l13_l14" }, | |
2046 | { "l14", 0x4d00, "vdd_l10_l13_l14" }, | |
2047 | { "l15", 0x4e00, "vdd_l5_l15_l19_l20_l21_l22" }, | |
2048 | { "l16", 0x4f00, "vdd_l12_l16" }, | |
2049 | { "l17", 0x5000, "vdd_l1_l7_l17_l18" }, | |
2050 | { "l18", 0x5100, "vdd_l1_l7_l17_l18" }, | |
2051 | { "l19", 0x5200, "vdd_l5_l15_l19_l20_l21_l22" }, | |
2052 | { "l20", 0x5300, "vdd_l5_l15_l19_l20_l21_l22" }, | |
2053 | { "l21", 0x5400, "vdd_l5_l15_l19_l20_l21_l22" }, | |
2054 | { "l22", 0x5500, "vdd_l5_l15_l19_l20_l21_l22" }, | |
2055 | { "l23", 0x5600, "vdd_l23_l24" }, | |
2056 | { "l24", 0x5700, "vdd_l23_l24" }, | |
2057 | }; | |
2058 | ||
9a2da074 IC |
2059 | static const struct spmi_regulator_data pm660_regulators[] = { |
2060 | { "s1", 0x1400, "vdd_s1", }, | |
2061 | { "s2", 0x1700, "vdd_s2", }, | |
2062 | { "s3", 0x1a00, "vdd_s3", }, | |
2063 | { "s4", 0x1d00, "vdd_s3", }, | |
2064 | { "s5", 0x2000, "vdd_s5", }, | |
2065 | { "s6", 0x2300, "vdd_s6", }, | |
2066 | { "l1", 0x4000, "vdd_l1_l6_l7", }, | |
2067 | { "l2", 0x4100, "vdd_l2_l3", }, | |
2068 | { "l3", 0x4200, "vdd_l2_l3", }, | |
2069 | /* l4 is unaccessible on PM660 */ | |
2070 | { "l5", 0x4400, "vdd_l5", }, | |
2071 | { "l6", 0x4500, "vdd_l1_l6_l7", }, | |
2072 | { "l7", 0x4600, "vdd_l1_l6_l7", }, | |
2073 | { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", }, | |
2074 | { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", }, | |
2075 | { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", }, | |
2076 | { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, | |
2077 | { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, | |
2078 | { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, | |
2079 | { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", }, | |
2080 | { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", }, | |
2081 | { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", }, | |
2082 | { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", }, | |
2083 | { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", }, | |
2084 | { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", }, | |
2085 | { } | |
2086 | }; | |
2087 | ||
2088 | static const struct spmi_regulator_data pm660l_regulators[] = { | |
2089 | { "s1", 0x1400, "vdd_s1", }, | |
2090 | { "s2", 0x1700, "vdd_s2", }, | |
2091 | { "s3", 0x1a00, "vdd_s3", }, | |
2092 | { "s4", 0x1d00, "vdd_s4", }, | |
2093 | { "s5", 0x2000, "vdd_s5", }, | |
2094 | { "l1", 0x4000, "vdd_l1_l9_l10", }, | |
2095 | { "l2", 0x4100, "vdd_l2", }, | |
2096 | { "l3", 0x4200, "vdd_l3_l5_l7_l8", }, | |
2097 | { "l4", 0x4300, "vdd_l4_l6", }, | |
2098 | { "l5", 0x4400, "vdd_l3_l5_l7_l8", }, | |
2099 | { "l6", 0x4500, "vdd_l4_l6", }, | |
2100 | { "l7", 0x4600, "vdd_l3_l5_l7_l8", }, | |
2101 | { "l8", 0x4700, "vdd_l3_l5_l7_l8", }, | |
2102 | { "l9", 0x4800, "vdd_l1_l9_l10", }, | |
2103 | { "l10", 0x4900, "vdd_l1_l9_l10", }, | |
2104 | { } | |
2105 | }; | |
2106 | ||
2107 | static const struct spmi_regulator_data pm8004_regulators[] = { | |
2108 | { "s2", 0x1700, "vdd_s2", }, | |
2109 | { "s5", 0x2000, "vdd_s5", }, | |
2110 | { } | |
2111 | }; | |
2112 | ||
2113 | static const struct spmi_regulator_data pm8005_regulators[] = { | |
2114 | { "s1", 0x1400, "vdd_s1", }, | |
2115 | { "s2", 0x1700, "vdd_s2", }, | |
2116 | { "s3", 0x1a00, "vdd_s3", }, | |
2117 | { "s4", 0x1d00, "vdd_s4", }, | |
2118 | { } | |
2119 | }; | |
2120 | ||
f8843e5e DK |
2121 | static const struct spmi_regulator_data pm8226_regulators[] = { |
2122 | { "s1", 0x1400, "vdd_s1", }, | |
2123 | { "s2", 0x1700, "vdd_s2", }, | |
2124 | { "s3", 0x1a00, "vdd_s3", }, | |
2125 | { "s4", 0x1d00, "vdd_s4", }, | |
2126 | { "s5", 0x2000, "vdd_s5", }, | |
2127 | { "l1", 0x4000, "vdd_l1_l2_l4_l5", }, | |
2128 | { "l2", 0x4100, "vdd_l1_l2_l4_l5", }, | |
2129 | { "l3", 0x4200, "vdd_l3_l24_l26", }, | |
2130 | { "l4", 0x4300, "vdd_l1_l2_l4_l5", }, | |
2131 | { "l5", 0x4400, "vdd_l1_l2_l4_l5", }, | |
2132 | { "l6", 0x4500, "vdd_l6_l7_l8_l9_l27", }, | |
2133 | { "l7", 0x4600, "vdd_l6_l7_l8_l9_l27", }, | |
2134 | { "l8", 0x4700, "vdd_l6_l7_l8_l9_l27", }, | |
2135 | { "l9", 0x4800, "vdd_l6_l7_l8_l9_l27", }, | |
2136 | { "l10", 0x4900, "vdd_l10_l11_l13", }, | |
2137 | { "l11", 0x4a00, "vdd_l10_l11_l13", }, | |
2138 | { "l12", 0x4b00, "vdd_l12_l14", }, | |
2139 | { "l13", 0x4c00, "vdd_l10_l11_l13", }, | |
2140 | { "l14", 0x4d00, "vdd_l12_l14", }, | |
2141 | { "l15", 0x4e00, "vdd_l15_l16_l17_l18", }, | |
2142 | { "l16", 0x4f00, "vdd_l15_l16_l17_l18", }, | |
2143 | { "l17", 0x5000, "vdd_l15_l16_l17_l18", }, | |
2144 | { "l18", 0x5100, "vdd_l15_l16_l17_l18", }, | |
2145 | { "l19", 0x5200, "vdd_l19_l20_l21_l22_l23_l28", }, | |
2146 | { "l20", 0x5300, "vdd_l19_l20_l21_l22_l23_l28", }, | |
2147 | { "l21", 0x5400, "vdd_l19_l20_l21_l22_l23_l28", }, | |
2148 | { "l22", 0x5500, "vdd_l19_l20_l21_l22_l23_l28", }, | |
2149 | { "l23", 0x5600, "vdd_l19_l20_l21_l22_l23_l28", }, | |
2150 | { "l24", 0x5700, "vdd_l3_l24_l26", }, | |
2151 | { "l25", 0x5800, "vdd_l25", }, | |
2152 | { "l26", 0x5900, "vdd_l3_l24_l26", }, | |
2153 | { "l27", 0x5a00, "vdd_l6_l7_l8_l9_l27", }, | |
2154 | { "l28", 0x5b00, "vdd_l19_l20_l21_l22_l23_l28", }, | |
2155 | { "lvs1", 0x8000, "vdd_lvs1", }, | |
2156 | { } | |
2157 | }; | |
2158 | ||
e92a4047 SB |
2159 | static const struct spmi_regulator_data pm8841_regulators[] = { |
2160 | { "s1", 0x1400, "vdd_s1", }, | |
2161 | { "s2", 0x1700, "vdd_s2", NULL, 0x1c08 }, | |
2162 | { "s3", 0x1a00, "vdd_s3", }, | |
2163 | { "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 }, | |
2164 | { "s5", 0x2000, "vdd_s5", NULL, 0x1c08 }, | |
2165 | { "s6", 0x2300, "vdd_s6", NULL, 0x1c08 }, | |
2166 | { "s7", 0x2600, "vdd_s7", NULL, 0x1c08 }, | |
2167 | { "s8", 0x2900, "vdd_s8", NULL, 0x1c08 }, | |
2168 | { } | |
2169 | }; | |
2170 | ||
2171 | static const struct spmi_regulator_data pm8916_regulators[] = { | |
2172 | { "s1", 0x1400, "vdd_s1", }, | |
2173 | { "s2", 0x1700, "vdd_s2", }, | |
2174 | { "s3", 0x1a00, "vdd_s3", }, | |
2175 | { "s4", 0x1d00, "vdd_s4", }, | |
2176 | { "l1", 0x4000, "vdd_l1_l3", }, | |
2177 | { "l2", 0x4100, "vdd_l2", }, | |
2178 | { "l3", 0x4200, "vdd_l1_l3", }, | |
2179 | { "l4", 0x4300, "vdd_l4_l5_l6", }, | |
2180 | { "l5", 0x4400, "vdd_l4_l5_l6", }, | |
2181 | { "l6", 0x4500, "vdd_l4_l5_l6", }, | |
2182 | { "l7", 0x4600, "vdd_l7", }, | |
2183 | { "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", }, | |
2184 | { "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", }, | |
2185 | { "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", }, | |
2186 | { "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", }, | |
2187 | { "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", }, | |
2188 | { "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", }, | |
2189 | { "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", }, | |
2190 | { "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", }, | |
2191 | { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", }, | |
2192 | { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", }, | |
2193 | { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", }, | |
2194 | { } | |
2195 | }; | |
2196 | ||
046d7e32 IC |
2197 | static const struct spmi_regulator_data pm8941_regulators[] = { |
2198 | { "s1", 0x1400, "vdd_s1", }, | |
2199 | { "s2", 0x1700, "vdd_s2", }, | |
2200 | { "s3", 0x1a00, "vdd_s3", }, | |
2201 | { "s4", 0xa000, }, | |
2202 | { "l1", 0x4000, "vdd_l1_l3", }, | |
2203 | { "l2", 0x4100, "vdd_l2_lvs_1_2_3", }, | |
2204 | { "l3", 0x4200, "vdd_l1_l3", }, | |
2205 | { "l4", 0x4300, "vdd_l4_l11", }, | |
2206 | { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 }, | |
2207 | { "l6", 0x4500, "vdd_l6_l12_l14_l15", }, | |
2208 | { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 }, | |
2209 | { "l8", 0x4700, "vdd_l8_l16_l18_19", }, | |
2210 | { "l9", 0x4800, "vdd_l9_l10_l17_l22", }, | |
2211 | { "l10", 0x4900, "vdd_l9_l10_l17_l22", }, | |
2212 | { "l11", 0x4a00, "vdd_l4_l11", }, | |
2213 | { "l12", 0x4b00, "vdd_l6_l12_l14_l15", }, | |
2214 | { "l13", 0x4c00, "vdd_l13_l20_l23_l24", }, | |
2215 | { "l14", 0x4d00, "vdd_l6_l12_l14_l15", }, | |
2216 | { "l15", 0x4e00, "vdd_l6_l12_l14_l15", }, | |
2217 | { "l16", 0x4f00, "vdd_l8_l16_l18_19", }, | |
2218 | { "l17", 0x5000, "vdd_l9_l10_l17_l22", }, | |
2219 | { "l18", 0x5100, "vdd_l8_l16_l18_19", }, | |
2220 | { "l19", 0x5200, "vdd_l8_l16_l18_19", }, | |
2221 | { "l20", 0x5300, "vdd_l13_l20_l23_l24", }, | |
2222 | { "l21", 0x5400, "vdd_l21", }, | |
2223 | { "l22", 0x5500, "vdd_l9_l10_l17_l22", }, | |
2224 | { "l23", 0x5600, "vdd_l13_l20_l23_l24", }, | |
2225 | { "l24", 0x5700, "vdd_l13_l20_l23_l24", }, | |
2226 | { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", }, | |
2227 | { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", }, | |
2228 | { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", }, | |
2229 | { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", }, | |
2230 | { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", }, | |
2231 | { } | |
2232 | }; | |
2233 | ||
e4ff1710 ADR |
2234 | static const struct spmi_regulator_data pm8950_regulators[] = { |
2235 | { "s1", 0x1400, "vdd_s1", }, | |
2236 | { "s2", 0x1700, "vdd_s2", }, | |
2237 | { "s3", 0x1a00, "vdd_s3", }, | |
2238 | { "s4", 0x1d00, "vdd_s4", }, | |
2239 | { "s5", 0x2000, "vdd_s5", }, | |
2240 | { "s6", 0x2300, "vdd_s6", }, | |
2241 | { "l1", 0x4000, "vdd_l1_l19", }, | |
2242 | { "l2", 0x4100, "vdd_l2_l23", }, | |
2243 | { "l3", 0x4200, "vdd_l3", }, | |
2244 | { "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", }, | |
2245 | { "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", }, | |
2246 | { "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", }, | |
2247 | { "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", }, | |
2248 | { "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", }, | |
2249 | { "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", }, | |
2250 | { "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", }, | |
2251 | { "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", }, | |
2252 | { "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", }, | |
2253 | { "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", }, | |
2254 | { "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", }, | |
2255 | { "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", }, | |
2256 | { "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", }, | |
2257 | { "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", }, | |
2258 | { "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", }, | |
2259 | { "l19", 0x5200, "vdd_l1_l19", }, | |
2260 | { "l20", 0x5300, "vdd_l20", }, | |
2261 | { "l21", 0x5400, "vdd_l21", }, | |
2262 | { "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", }, | |
2263 | { "l23", 0x5600, "vdd_l2_l23", }, | |
2264 | { } | |
2265 | }; | |
2266 | ||
50314e55 SB |
2267 | static const struct spmi_regulator_data pm8994_regulators[] = { |
2268 | { "s1", 0x1400, "vdd_s1", }, | |
2269 | { "s2", 0x1700, "vdd_s2", }, | |
2270 | { "s3", 0x1a00, "vdd_s3", }, | |
2271 | { "s4", 0x1d00, "vdd_s4", }, | |
2272 | { "s5", 0x2000, "vdd_s5", }, | |
2273 | { "s6", 0x2300, "vdd_s6", }, | |
2274 | { "s7", 0x2600, "vdd_s7", }, | |
2275 | { "s8", 0x2900, "vdd_s8", }, | |
2276 | { "s9", 0x2c00, "vdd_s9", }, | |
2277 | { "s10", 0x2f00, "vdd_s10", }, | |
2278 | { "s11", 0x3200, "vdd_s11", }, | |
2279 | { "s12", 0x3500, "vdd_s12", }, | |
2280 | { "l1", 0x4000, "vdd_l1", }, | |
2281 | { "l2", 0x4100, "vdd_l2_l26_l28", }, | |
2282 | { "l3", 0x4200, "vdd_l3_l11", }, | |
2283 | { "l4", 0x4300, "vdd_l4_l27_l31", }, | |
2284 | { "l5", 0x4400, "vdd_l5_l7", }, | |
2285 | { "l6", 0x4500, "vdd_l6_l12_l32", }, | |
2286 | { "l7", 0x4600, "vdd_l5_l7", }, | |
2287 | { "l8", 0x4700, "vdd_l8_l16_l30", }, | |
2288 | { "l9", 0x4800, "vdd_l9_l10_l18_l22", }, | |
2289 | { "l10", 0x4900, "vdd_l9_l10_l18_l22", }, | |
2290 | { "l11", 0x4a00, "vdd_l3_l11", }, | |
2291 | { "l12", 0x4b00, "vdd_l6_l12_l32", }, | |
2292 | { "l13", 0x4c00, "vdd_l13_l19_l23_l24", }, | |
2293 | { "l14", 0x4d00, "vdd_l14_l15", }, | |
2294 | { "l15", 0x4e00, "vdd_l14_l15", }, | |
2295 | { "l16", 0x4f00, "vdd_l8_l16_l30", }, | |
2296 | { "l17", 0x5000, "vdd_l17_l29", }, | |
2297 | { "l18", 0x5100, "vdd_l9_l10_l18_l22", }, | |
2298 | { "l19", 0x5200, "vdd_l13_l19_l23_l24", }, | |
2299 | { "l20", 0x5300, "vdd_l20_l21", }, | |
2300 | { "l21", 0x5400, "vdd_l20_l21", }, | |
2301 | { "l22", 0x5500, "vdd_l9_l10_l18_l22", }, | |
2302 | { "l23", 0x5600, "vdd_l13_l19_l23_l24", }, | |
2303 | { "l24", 0x5700, "vdd_l13_l19_l23_l24", }, | |
2304 | { "l25", 0x5800, "vdd_l25", }, | |
2305 | { "l26", 0x5900, "vdd_l2_l26_l28", }, | |
2306 | { "l27", 0x5a00, "vdd_l4_l27_l31", }, | |
2307 | { "l28", 0x5b00, "vdd_l2_l26_l28", }, | |
2308 | { "l29", 0x5c00, "vdd_l17_l29", }, | |
2309 | { "l30", 0x5d00, "vdd_l8_l16_l30", }, | |
2310 | { "l31", 0x5e00, "vdd_l4_l27_l31", }, | |
2311 | { "l32", 0x5f00, "vdd_l6_l12_l32", }, | |
2312 | { "lvs1", 0x8000, "vdd_lvs_1_2", }, | |
2313 | { "lvs2", 0x8100, "vdd_lvs_1_2", }, | |
2314 | { } | |
2315 | }; | |
2316 | ||
ca5cd8c9 RN |
2317 | static const struct spmi_regulator_data pmi8994_regulators[] = { |
2318 | { "s1", 0x1400, "vdd_s1", }, | |
2319 | { "s2", 0x1700, "vdd_s2", }, | |
2320 | { "s3", 0x1a00, "vdd_s3", }, | |
2321 | { "l1", 0x4000, "vdd_l1", }, | |
37164571 | 2322 | { } |
ca5cd8c9 RN |
2323 | }; |
2324 | ||
34ceb6a6 RM |
2325 | static const struct spmi_regulator_data pmp8074_regulators[] = { |
2326 | { "s1", 0x1400, "vdd_s1"}, | |
2327 | { "s2", 0x1700, "vdd_s2"}, | |
2328 | { "s3", 0x1a00, "vdd_s3"}, | |
2329 | { "s4", 0x1d00, "vdd_s4"}, | |
2330 | { "s5", 0x2000, "vdd_s5"}, | |
2331 | { "l1", 0x4000, "vdd_l1_l2"}, | |
2332 | { "l2", 0x4100, "vdd_l1_l2"}, | |
2333 | { "l3", 0x4200, "vdd_l3_l8"}, | |
2334 | { "l4", 0x4300, "vdd_l4"}, | |
2335 | { "l5", 0x4400, "vdd_l5_l6_l15"}, | |
2336 | { "l6", 0x4500, "vdd_l5_l6_l15"}, | |
2337 | { "l7", 0x4600, "vdd_l7"}, | |
2338 | { "l8", 0x4700, "vdd_l3_l8"}, | |
2339 | { "l9", 0x4800, "vdd_l9"}, | |
2340 | /* l10 is currently unsupported HT_P50 */ | |
2341 | { "l11", 0x4a00, "vdd_l10_l11_l12_l13"}, | |
2342 | { "l12", 0x4b00, "vdd_l10_l11_l12_l13"}, | |
2343 | { "l13", 0x4c00, "vdd_l10_l11_l12_l13"}, | |
2344 | { } | |
2345 | }; | |
2346 | ||
0211f68e JR |
2347 | static const struct spmi_regulator_data pms405_regulators[] = { |
2348 | { "s3", 0x1a00, "vdd_s3"}, | |
2349 | { } | |
2350 | }; | |
2351 | ||
e92a4047 | 2352 | static const struct of_device_id qcom_spmi_regulator_match[] = { |
e62ef4a9 | 2353 | { .compatible = "qcom,pm6125-regulators", .data = &pm6125_regulators }, |
9a2da074 IC |
2354 | { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators }, |
2355 | { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators }, | |
2e36e140 | 2356 | { .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators }, |
42ba89c8 | 2357 | { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators }, |
f8843e5e | 2358 | { .compatible = "qcom,pm8226-regulators", .data = &pm8226_regulators }, |
e92a4047 SB |
2359 | { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators }, |
2360 | { .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators }, | |
2361 | { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators }, | |
e4ff1710 | 2362 | { .compatible = "qcom,pm8950-regulators", .data = &pm8950_regulators }, |
50314e55 | 2363 | { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators }, |
ca5cd8c9 | 2364 | { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators }, |
34ceb6a6 | 2365 | { .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators }, |
0211f68e | 2366 | { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators }, |
e92a4047 SB |
2367 | { } |
2368 | }; | |
2369 | MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match); | |
2370 | ||
2371 | static int qcom_spmi_regulator_probe(struct platform_device *pdev) | |
2372 | { | |
2373 | const struct spmi_regulator_data *reg; | |
86f4ff7a | 2374 | const struct spmi_voltage_range *range; |
e92a4047 SB |
2375 | const struct of_device_id *match; |
2376 | struct regulator_config config = { }; | |
2377 | struct regulator_dev *rdev; | |
2378 | struct spmi_regulator *vreg; | |
2379 | struct regmap *regmap; | |
2380 | const char *name; | |
2381 | struct device *dev = &pdev->dev; | |
0caecaa8 | 2382 | struct device_node *node = pdev->dev.of_node; |
fffe7f52 NC |
2383 | struct device_node *syscon, *reg_node; |
2384 | struct property *reg_prop; | |
0caecaa8 | 2385 | int ret, lenp; |
e92a4047 SB |
2386 | struct list_head *vreg_list; |
2387 | ||
2388 | vreg_list = devm_kzalloc(dev, sizeof(*vreg_list), GFP_KERNEL); | |
2389 | if (!vreg_list) | |
2390 | return -ENOMEM; | |
2391 | INIT_LIST_HEAD(vreg_list); | |
2392 | platform_set_drvdata(pdev, vreg_list); | |
2393 | ||
2394 | regmap = dev_get_regmap(dev->parent, NULL); | |
2395 | if (!regmap) | |
2396 | return -ENODEV; | |
2397 | ||
2398 | match = of_match_device(qcom_spmi_regulator_match, &pdev->dev); | |
2399 | if (!match) | |
2400 | return -ENODEV; | |
2401 | ||
0caecaa8 IL |
2402 | if (of_find_property(node, "qcom,saw-reg", &lenp)) { |
2403 | syscon = of_parse_phandle(node, "qcom,saw-reg", 0); | |
2404 | saw_regmap = syscon_node_to_regmap(syscon); | |
2405 | of_node_put(syscon); | |
85046a15 | 2406 | if (IS_ERR(saw_regmap)) |
0caecaa8 IL |
2407 | dev_err(dev, "ERROR reading SAW regmap\n"); |
2408 | } | |
2409 | ||
e92a4047 | 2410 | for (reg = match->data; reg->name; reg++) { |
0caecaa8 | 2411 | |
fffe7f52 NC |
2412 | if (saw_regmap) { |
2413 | reg_node = of_get_child_by_name(node, reg->name); | |
2414 | reg_prop = of_find_property(reg_node, "qcom,saw-slave", | |
2415 | &lenp); | |
2416 | of_node_put(reg_node); | |
2417 | if (reg_prop) | |
2418 | continue; | |
0caecaa8 IL |
2419 | } |
2420 | ||
e92a4047 SB |
2421 | vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL); |
2422 | if (!vreg) | |
2423 | return -ENOMEM; | |
2424 | ||
2425 | vreg->dev = dev; | |
2426 | vreg->base = reg->base; | |
2427 | vreg->regmap = regmap; | |
e92a4047 SB |
2428 | if (reg->ocp) { |
2429 | vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp); | |
b6688015 MV |
2430 | if (vreg->ocp_irq < 0) |
2431 | return vreg->ocp_irq; | |
e92a4047 | 2432 | } |
e92a4047 SB |
2433 | vreg->desc.id = -1; |
2434 | vreg->desc.owner = THIS_MODULE; | |
2435 | vreg->desc.type = REGULATOR_VOLTAGE; | |
9d485332 AL |
2436 | vreg->desc.enable_reg = reg->base + SPMI_COMMON_REG_ENABLE; |
2437 | vreg->desc.enable_mask = SPMI_COMMON_ENABLE_MASK; | |
2438 | vreg->desc.enable_val = SPMI_COMMON_ENABLE; | |
e92a4047 SB |
2439 | vreg->desc.name = name = reg->name; |
2440 | vreg->desc.supply_name = reg->supply; | |
2441 | vreg->desc.of_match = reg->name; | |
2442 | vreg->desc.of_parse_cb = spmi_regulator_of_parse; | |
2443 | vreg->desc.of_map_mode = spmi_regulator_of_map_mode; | |
2444 | ||
2445 | ret = spmi_regulator_match(vreg, reg->force_type); | |
2446 | if (ret) | |
6ee5c044 | 2447 | continue; |
e92a4047 | 2448 | |
fffe7f52 NC |
2449 | if (saw_regmap) { |
2450 | reg_node = of_get_child_by_name(node, reg->name); | |
2451 | reg_prop = of_find_property(reg_node, "qcom,saw-leader", | |
2452 | &lenp); | |
2453 | of_node_put(reg_node); | |
2454 | if (reg_prop) { | |
2455 | spmi_saw_ops = *(vreg->desc.ops); | |
2456 | spmi_saw_ops.set_voltage_sel = | |
2457 | spmi_regulator_saw_set_voltage; | |
2458 | vreg->desc.ops = &spmi_saw_ops; | |
2459 | } | |
0caecaa8 IL |
2460 | } |
2461 | ||
b01d1823 | 2462 | if (vreg->set_points && vreg->set_points->count == 1) { |
86f4ff7a JRO |
2463 | /* since there is only one range */ |
2464 | range = vreg->set_points->range; | |
2465 | vreg->desc.uV_step = range->step_uV; | |
2466 | } | |
2467 | ||
e92a4047 SB |
2468 | config.dev = dev; |
2469 | config.driver_data = vreg; | |
9d485332 | 2470 | config.regmap = regmap; |
e92a4047 SB |
2471 | rdev = devm_regulator_register(dev, &vreg->desc, &config); |
2472 | if (IS_ERR(rdev)) { | |
2473 | dev_err(dev, "failed to register %s\n", name); | |
b6688015 | 2474 | return PTR_ERR(rdev); |
e92a4047 SB |
2475 | } |
2476 | ||
2477 | INIT_LIST_HEAD(&vreg->node); | |
2478 | list_add(&vreg->node, vreg_list); | |
2479 | } | |
2480 | ||
2481 | return 0; | |
e92a4047 SB |
2482 | } |
2483 | ||
2484 | static struct platform_driver qcom_spmi_regulator_driver = { | |
2485 | .driver = { | |
2486 | .name = "qcom-spmi-regulator", | |
2487 | .of_match_table = qcom_spmi_regulator_match, | |
2488 | }, | |
2489 | .probe = qcom_spmi_regulator_probe, | |
e92a4047 SB |
2490 | }; |
2491 | module_platform_driver(qcom_spmi_regulator_driver); | |
2492 | ||
2493 | MODULE_DESCRIPTION("Qualcomm SPMI PMIC regulator driver"); | |
2494 | MODULE_LICENSE("GPL v2"); | |
2495 | MODULE_ALIAS("platform:qcom-spmi-regulator"); |