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Merge tag 'nfsd-6.2-4' of git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux
[linux-block.git] / drivers / regulator / qcom_smd-regulator.c
CommitLineData
97fb5e8d 1// SPDX-License-Identifier: GPL-2.0-only
da65e367
BA		 2/*
3 * Copyright (c) 2015, Sony Mobile Communications AB.
4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
da65e367
BA		 5 */
6
7#include <linux/module.h>
8#include <linux/of.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11#include <linux/regulator/driver.h>
14e2976f 12#include <linux/regulator/of_regulator.h>
da65e367
BA		 13#include <linux/soc/qcom/smd-rpm.h>
14
15struct qcom_rpm_reg {
16 struct device *dev;
17
18 struct qcom_smd_rpm *rpm;
19
20 u32 type;
21 u32 id;
22
23 struct regulator_desc desc;
24
25 int is_enabled;
26 int uV;
fd805d99
BA		 27 u32 load;
28
29 unsigned int enabled_updated:1;
30 unsigned int uv_updated:1;
31 unsigned int load_updated:1;
da65e367
BA		 32};
33
34struct rpm_regulator_req {
2c652a98
SB		 35 __le32 key;
36 __le32 nbytes;
37 __le32 value;
da65e367
BA		 38};
39
40#define RPM_KEY_SWEN 0x6e657773 /* "swen" */
41#define RPM_KEY_UV 0x00007675 /* "uv" */
42#define RPM_KEY_MA 0x0000616d /* "ma" */
43
fd805d99 44static int rpm_reg_write_active(struct qcom_rpm_reg *vreg)
da65e367 45{
fd805d99
BA		 46 struct rpm_regulator_req req[3];
47 int reqlen = 0;
48 int ret;
49
50 if (vreg->enabled_updated) {
51 req[reqlen].key = cpu_to_le32(RPM_KEY_SWEN);
52 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
53 req[reqlen].value = cpu_to_le32(vreg->is_enabled);
54 reqlen++;
55 }
56
57 if (vreg->uv_updated && vreg->is_enabled) {
58 req[reqlen].key = cpu_to_le32(RPM_KEY_UV);
59 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
60 req[reqlen].value = cpu_to_le32(vreg->uV);
61 reqlen++;
62 }
63
64 if (vreg->load_updated && vreg->is_enabled) {
65 req[reqlen].key = cpu_to_le32(RPM_KEY_MA);
66 req[reqlen].nbytes = cpu_to_le32(sizeof(u32));
67 req[reqlen].value = cpu_to_le32(vreg->load / 1000);
68 reqlen++;
69 }
70
71 if (!reqlen)
72 return 0;
73
74 ret = qcom_rpm_smd_write(vreg->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
75 vreg->type, vreg->id,
76 req, sizeof(req[0]) * reqlen);
77 if (!ret) {
78 vreg->enabled_updated = 0;
79 vreg->uv_updated = 0;
80 vreg->load_updated = 0;
81 }
82
83 return ret;
da65e367
BA		 84}
85
86static int rpm_reg_enable(struct regulator_dev *rdev)
87{
88 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
da65e367
BA		 89 int ret;
90
fd805d99
BA		 91 vreg->is_enabled = 1;
92 vreg->enabled_updated = 1;
da65e367 93
fd805d99
BA		 94 ret = rpm_reg_write_active(vreg);
95 if (ret)
96 vreg->is_enabled = 0;
da65e367
BA		 97
98 return ret;
99}
100
101static int rpm_reg_is_enabled(struct regulator_dev *rdev)
102{
103 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
104
105 return vreg->is_enabled;
106}
107
108static int rpm_reg_disable(struct regulator_dev *rdev)
109{
110 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
da65e367
BA		 111 int ret;
112
fd805d99
BA		 113 vreg->is_enabled = 0;
114 vreg->enabled_updated = 1;
da65e367 115
fd805d99
BA		 116 ret = rpm_reg_write_active(vreg);
117 if (ret)
118 vreg->is_enabled = 1;
da65e367
BA		 119
120 return ret;
121}
122
123static int rpm_reg_get_voltage(struct regulator_dev *rdev)
124{
125 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
126
127 return vreg->uV;
128}
129
130static int rpm_reg_set_voltage(struct regulator_dev *rdev,
131 int min_uV,
132 int max_uV,
133 unsigned *selector)
134{
135 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
fd805d99
BA		 136 int ret;
137 int old_uV = vreg->uV;
da65e367 138
fd805d99
BA		 139 vreg->uV = min_uV;
140 vreg->uv_updated = 1;
da65e367 141
fd805d99
BA		 142 ret = rpm_reg_write_active(vreg);
143 if (ret)
144 vreg->uV = old_uV;
da65e367
BA		 145
146 return ret;
147}
148
149static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
150{
151 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
fd805d99
BA		 152 u32 old_load = vreg->load;
153 int ret;
da65e367 154
fd805d99
BA		 155 vreg->load = load_uA;
156 vreg->load_updated = 1;
157 ret = rpm_reg_write_active(vreg);
158 if (ret)
159 vreg->load = old_load;
da65e367 160
fd805d99 161 return ret;
da65e367
BA		 162}
163
164static const struct regulator_ops rpm_smps_ldo_ops = {
165 .enable = rpm_reg_enable,
166 .disable = rpm_reg_disable,
167 .is_enabled = rpm_reg_is_enabled,
a8a47540 168 .list_voltage = regulator_list_voltage_linear_range,
da65e367
BA		 169
170 .get_voltage = rpm_reg_get_voltage,
171 .set_voltage = rpm_reg_set_voltage,
172
173 .set_load = rpm_reg_set_load,
174};
175
d1e44b6b
SK		 176static const struct regulator_ops rpm_smps_ldo_ops_fixed = {
177 .enable = rpm_reg_enable,
178 .disable = rpm_reg_disable,
179 .is_enabled = rpm_reg_is_enabled,
180
181 .get_voltage = rpm_reg_get_voltage,
182 .set_voltage = rpm_reg_set_voltage,
183
184 .set_load = rpm_reg_set_load,
185};
186
da65e367
BA		 187static const struct regulator_ops rpm_switch_ops = {
188 .enable = rpm_reg_enable,
189 .disable = rpm_reg_disable,
190 .is_enabled = rpm_reg_is_enabled,
191};
192
3cdb741e
BA		 193static const struct regulator_ops rpm_bob_ops = {
194 .enable = rpm_reg_enable,
195 .disable = rpm_reg_disable,
196 .is_enabled = rpm_reg_is_enabled,
197
198 .get_voltage = rpm_reg_get_voltage,
199 .set_voltage = rpm_reg_set_voltage,
200};
201
47894c85
K		 202static const struct regulator_ops rpm_mp5496_ops = {
203 .enable = rpm_reg_enable,
204 .disable = rpm_reg_disable,
205 .is_enabled = rpm_reg_is_enabled,
206 .list_voltage = regulator_list_voltage_linear_range,
207
f210f387 208 .get_voltage = rpm_reg_get_voltage,
47894c85
K		 209 .set_voltage = rpm_reg_set_voltage,
210};
211
ee01d0c9 212static const struct regulator_desc pma8084_hfsmps = {
60ab7f41 213 .linear_ranges = (struct linear_range[]) {
ee01d0c9
AG		 214 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
215 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
216 },
217 .n_linear_ranges = 2,
218 .n_voltages = 159,
219 .ops = &rpm_smps_ldo_ops,
220};
221
222static const struct regulator_desc pma8084_ftsmps = {
60ab7f41 223 .linear_ranges = (struct linear_range[]) {
ee01d0c9 224 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
c488f007 225 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
ee01d0c9
AG		 226 },
227 .n_linear_ranges = 2,
c488f007 228 .n_voltages = 262,
ee01d0c9
AG		 229 .ops = &rpm_smps_ldo_ops,
230};
231
232static const struct regulator_desc pma8084_pldo = {
60ab7f41 233 .linear_ranges = (struct linear_range[]) {
c488f007
SB		 234 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
235 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
236 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
ee01d0c9 237 },
c488f007
SB		 238 .n_linear_ranges = 3,
239 .n_voltages = 164,
ee01d0c9
AG		 240 .ops = &rpm_smps_ldo_ops,
241};
242
243static const struct regulator_desc pma8084_nldo = {
60ab7f41 244 .linear_ranges = (struct linear_range[]) {
ee01d0c9
AG		 245 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
246 },
247 .n_linear_ranges = 1,
248 .n_voltages = 64,
249 .ops = &rpm_smps_ldo_ops,
250};
251
252static const struct regulator_desc pma8084_switch = {
253 .ops = &rpm_switch_ops,
254};
255
8c816d56
BD		 256static const struct regulator_desc pm8226_hfsmps = {
257 .linear_ranges = (struct linear_range[]) {
258 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
259 REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
260 },
261 .n_linear_ranges = 2,
262 .n_voltages = 159,
263 .ops = &rpm_smps_ldo_ops,
264};
265
266static const struct regulator_desc pm8226_ftsmps = {
267 .linear_ranges = (struct linear_range[]) {
268 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
269 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
270 },
271 .n_linear_ranges = 2,
272 .n_voltages = 262,
273 .ops = &rpm_smps_ldo_ops,
274};
275
276static const struct regulator_desc pm8226_pldo = {
277 .linear_ranges = (struct linear_range[]) {
278 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
279 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
280 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
281 },
282 .n_linear_ranges = 3,
283 .n_voltages = 164,
284 .ops = &rpm_smps_ldo_ops,
285};
286
287static const struct regulator_desc pm8226_nldo = {
288 .linear_ranges = (struct linear_range[]) {
289 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
290 },
291 .n_linear_ranges = 1,
292 .n_voltages = 64,
293 .ops = &rpm_smps_ldo_ops,
294};
295
296static const struct regulator_desc pm8226_switch = {
297 .ops = &rpm_switch_ops,
298};
299
da65e367 300static const struct regulator_desc pm8x41_hfsmps = {
60ab7f41 301 .linear_ranges = (struct linear_range[]) {
da65e367 302 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
b7a8524c 303 REGULATOR_LINEAR_RANGE(1575000, 96, 158, 25000),
da65e367
BA		 304 },
305 .n_linear_ranges = 2,
306 .n_voltages = 159,
307 .ops = &rpm_smps_ldo_ops,
308};
309
310static const struct regulator_desc pm8841_ftsmps = {
60ab7f41 311 .linear_ranges = (struct linear_range[]) {
da65e367 312 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
29028477 313 REGULATOR_LINEAR_RANGE(1280000, 185, 261, 10000),
da65e367
BA		 314 },
315 .n_linear_ranges = 2,
29028477 316 .n_voltages = 262,
da65e367
BA		 317 .ops = &rpm_smps_ldo_ops,
318};
319
320static const struct regulator_desc pm8941_boost = {
60ab7f41 321 .linear_ranges = (struct linear_range[]) {
29028477 322 REGULATOR_LINEAR_RANGE(4000000, 0, 30, 50000),
da65e367
BA		 323 },
324 .n_linear_ranges = 1,
29028477 325 .n_voltages = 31,
da65e367
BA		 326 .ops = &rpm_smps_ldo_ops,
327};
328
329static const struct regulator_desc pm8941_pldo = {
60ab7f41 330 .linear_ranges = (struct linear_range[]) {
29028477
SB		 331 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
332 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
333 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
da65e367 334 },
29028477
SB		 335 .n_linear_ranges = 3,
336 .n_voltages = 164,
da65e367
BA		 337 .ops = &rpm_smps_ldo_ops,
338};
339
340static const struct regulator_desc pm8941_nldo = {
60ab7f41 341 .linear_ranges = (struct linear_range[]) {
da65e367
BA		 342 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
343 },
344 .n_linear_ranges = 1,
345 .n_voltages = 64,
346 .ops = &rpm_smps_ldo_ops,
347};
348
349static const struct regulator_desc pm8941_lnldo = {
350 .fixed_uV = 1740000,
5a286aae 351 .n_voltages = 1,
d1e44b6b 352 .ops = &rpm_smps_ldo_ops_fixed,
da65e367
BA		 353};
354
355static const struct regulator_desc pm8941_switch = {
356 .ops = &rpm_switch_ops,
357};
358
57d65676 359static const struct regulator_desc pm8916_pldo = {
60ab7f41 360 .linear_ranges = (struct linear_range[]) {
e8977917 361 REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500),
57d65676
AG		 362 },
363 .n_linear_ranges = 1,
e8977917 364 .n_voltages = 128,
57d65676
AG		 365 .ops = &rpm_smps_ldo_ops,
366};
367
368static const struct regulator_desc pm8916_nldo = {
60ab7f41 369 .linear_ranges = (struct linear_range[]) {
57d65676
AG		 370 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
371 },
372 .n_linear_ranges = 1,
373 .n_voltages = 94,
374 .ops = &rpm_smps_ldo_ops,
375};
376
377static const struct regulator_desc pm8916_buck_lvo_smps = {
60ab7f41 378 .linear_ranges = (struct linear_range[]) {
57d65676
AG		 379 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
380 REGULATOR_LINEAR_RANGE(750000, 96, 127, 25000),
381 },
382 .n_linear_ranges = 2,
383 .n_voltages = 128,
384 .ops = &rpm_smps_ldo_ops,
385};
386
387static const struct regulator_desc pm8916_buck_hvo_smps = {
60ab7f41 388 .linear_ranges = (struct linear_range[]) {
57d65676
AG		 389 REGULATOR_LINEAR_RANGE(1550000, 0, 31, 25000),
390 },
391 .n_linear_ranges = 1,
392 .n_voltages = 32,
393 .ops = &rpm_smps_ldo_ops,
394};
395
e44adca5 396static const struct regulator_desc pm8950_hfsmps = {
60ab7f41 397 .linear_ranges = (struct linear_range[]) {
e44adca5
ADR		 398 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
399 REGULATOR_LINEAR_RANGE(1550000, 96, 127, 25000),
400 },
401 .n_linear_ranges = 2,
402 .n_voltages = 128,
403 .ops = &rpm_smps_ldo_ops,
404};
405
406static const struct regulator_desc pm8950_ftsmps2p5 = {
60ab7f41 407 .linear_ranges = (struct linear_range[]) {
e44adca5
ADR		 408 REGULATOR_LINEAR_RANGE(80000, 0, 255, 5000),
409 REGULATOR_LINEAR_RANGE(160000, 256, 460, 10000),
410 },
411 .n_linear_ranges = 2,
412 .n_voltages = 461,
413 .ops = &rpm_smps_ldo_ops,
414};
415
416static const struct regulator_desc pm8950_ult_nldo = {
60ab7f41 417 .linear_ranges = (struct linear_range[]) {
e44adca5
ADR		 418 REGULATOR_LINEAR_RANGE(375000, 0, 202, 12500),
419 },
420 .n_linear_ranges = 1,
421 .n_voltages = 203,
422 .ops = &rpm_smps_ldo_ops,
423};
424
425static const struct regulator_desc pm8950_ult_pldo = {
60ab7f41 426 .linear_ranges = (struct linear_range[]) {
e44adca5
ADR		 427 REGULATOR_LINEAR_RANGE(1750000, 0, 127, 12500),
428 },
429 .n_linear_ranges = 1,
430 .n_voltages = 128,
431 .ops = &rpm_smps_ldo_ops,
432};
433
434static const struct regulator_desc pm8950_pldo_lv = {
60ab7f41 435 .linear_ranges = (struct linear_range[]) {
e44adca5
ADR		 436 REGULATOR_LINEAR_RANGE(1500000, 0, 16, 25000),
437 },
438 .n_linear_ranges = 1,
439 .n_voltages = 17,
440 .ops = &rpm_smps_ldo_ops,
441};
442
443static const struct regulator_desc pm8950_pldo = {
60ab7f41 444 .linear_ranges = (struct linear_range[]) {
e44adca5
ADR		 445 REGULATOR_LINEAR_RANGE(975000, 0, 164, 12500),
446 },
447 .n_linear_ranges = 1,
448 .n_voltages = 165,
449 .ops = &rpm_smps_ldo_ops,
450};
451
b1a2fb10
VL		 452static const struct regulator_desc pm8953_lnldo = {
453 .linear_ranges = (struct linear_range[]) {
b1a2fb10 454 REGULATOR_LINEAR_RANGE(690000, 0, 7, 60000),
e0f33921 455 REGULATOR_LINEAR_RANGE(1380000, 8, 15, 120000),
b1a2fb10
VL		 456 },
457 .n_linear_ranges = 2,
458 .n_voltages = 16,
459 .ops = &rpm_smps_ldo_ops,
460};
461
462static const struct regulator_desc pm8953_ult_nldo = {
463 .linear_ranges = (struct linear_range[]) {
464 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
465 },
466 .n_linear_ranges = 1,
467 .n_voltages = 94,
468 .ops = &rpm_smps_ldo_ops,
469};
e44adca5 470
14a16992 471static const struct regulator_desc pm8994_hfsmps = {
60ab7f41 472 .linear_ranges = (struct linear_range[]) {
14a16992
RN		 473 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
474 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
475 },
476 .n_linear_ranges = 2,
477 .n_voltages = 159,
478 .ops = &rpm_smps_ldo_ops,
479};
480
481static const struct regulator_desc pm8994_ftsmps = {
60ab7f41 482 .linear_ranges = (struct linear_range[]) {
14a16992
RN		 483 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000),
484 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
485 },
486 .n_linear_ranges = 2,
487 .n_voltages = 350,
488 .ops = &rpm_smps_ldo_ops,
489};
490
491static const struct regulator_desc pm8994_nldo = {
60ab7f41 492 .linear_ranges = (struct linear_range[]) {
14a16992
RN		 493 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
494 },
495 .n_linear_ranges = 1,
496 .n_voltages = 64,
497 .ops = &rpm_smps_ldo_ops,
498};
499
500static const struct regulator_desc pm8994_pldo = {
60ab7f41 501 .linear_ranges = (struct linear_range[]) {
14a16992
RN		 502 REGULATOR_LINEAR_RANGE( 750000, 0, 63, 12500),
503 REGULATOR_LINEAR_RANGE(1550000, 64, 126, 25000),
504 REGULATOR_LINEAR_RANGE(3100000, 127, 163, 50000),
505 },
506 .n_linear_ranges = 3,
507 .n_voltages = 164,
508 .ops = &rpm_smps_ldo_ops,
509};
510
511static const struct regulator_desc pm8994_switch = {
512 .ops = &rpm_switch_ops,
513};
514
515static const struct regulator_desc pm8994_lnldo = {
516 .fixed_uV = 1740000,
517 .n_voltages = 1,
518 .ops = &rpm_smps_ldo_ops_fixed,
519};
520
86332c34 521static const struct regulator_desc pmi8994_ftsmps = {
60ab7f41 522 .linear_ranges = (struct linear_range[]) {
86332c34
BA		 523 REGULATOR_LINEAR_RANGE(350000, 0, 199, 5000),
524 REGULATOR_LINEAR_RANGE(700000, 200, 349, 10000),
525 },
526 .n_linear_ranges = 2,
527 .n_voltages = 350,
528 .ops = &rpm_smps_ldo_ops,
529};
530
531static const struct regulator_desc pmi8994_hfsmps = {
60ab7f41 532 .linear_ranges = (struct linear_range[]) {
86332c34
BA		 533 REGULATOR_LINEAR_RANGE(350000, 0, 80, 12500),
534 REGULATOR_LINEAR_RANGE(700000, 81, 141, 25000),
535 },
536 .n_linear_ranges = 2,
537 .n_voltages = 142,
538 .ops = &rpm_smps_ldo_ops,
539};
540
541static const struct regulator_desc pmi8994_bby = {
60ab7f41 542 .linear_ranges = (struct linear_range[]) {
86332c34
BA		 543 REGULATOR_LINEAR_RANGE(3000000, 0, 44, 50000),
544 },
545 .n_linear_ranges = 1,
546 .n_voltages = 45,
547 .ops = &rpm_bob_ops,
548};
549
3cdb741e 550static const struct regulator_desc pm8998_ftsmps = {
60ab7f41 551 .linear_ranges = (struct linear_range[]) {
3cdb741e
BA		 552 REGULATOR_LINEAR_RANGE(320000, 0, 258, 4000),
553 },
554 .n_linear_ranges = 1,
555 .n_voltages = 259,
556 .ops = &rpm_smps_ldo_ops,
557};
558
559static const struct regulator_desc pm8998_hfsmps = {
60ab7f41 560 .linear_ranges = (struct linear_range[]) {
3cdb741e
BA		 561 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
562 },
563 .n_linear_ranges = 1,
564 .n_voltages = 216,
565 .ops = &rpm_smps_ldo_ops,
566};
567
568static const struct regulator_desc pm8998_nldo = {
60ab7f41 569 .linear_ranges = (struct linear_range[]) {
3cdb741e
BA		 570 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
571 },
572 .n_linear_ranges = 1,
573 .n_voltages = 128,
574 .ops = &rpm_smps_ldo_ops,
575};
576
577static const struct regulator_desc pm8998_pldo = {
60ab7f41 578 .linear_ranges = (struct linear_range[]) {
3cdb741e
BA		 579 REGULATOR_LINEAR_RANGE(1664000, 0, 255, 8000),
580 },
581 .n_linear_ranges = 1,
582 .n_voltages = 256,
583 .ops = &rpm_smps_ldo_ops,
584};
585
586static const struct regulator_desc pm8998_pldo_lv = {
60ab7f41 587 .linear_ranges = (struct linear_range[]) {
3cdb741e
BA		 588 REGULATOR_LINEAR_RANGE(1256000, 0, 127, 8000),
589 },
590 .n_linear_ranges = 1,
591 .n_voltages = 128,
592 .ops = &rpm_smps_ldo_ops,
593};
594
595static const struct regulator_desc pm8998_switch = {
596 .ops = &rpm_switch_ops,
597};
598
599static const struct regulator_desc pmi8998_bob = {
60ab7f41 600 .linear_ranges = (struct linear_range[]) {
3cdb741e
BA		 601 REGULATOR_LINEAR_RANGE(1824000, 0, 83, 32000),
602 },
603 .n_linear_ranges = 1,
604 .n_voltages = 84,
605 .ops = &rpm_bob_ops,
606};
607
6d849653
ADR		 608static const struct regulator_desc pm660_ftsmps = {
609 .linear_ranges = (struct linear_range[]) {
610 REGULATOR_LINEAR_RANGE(355000, 0, 199, 5000),
611 },
612 .n_linear_ranges = 1,
613 .n_voltages = 200,
614 .ops = &rpm_smps_ldo_ops,
615};
616
617static const struct regulator_desc pm660_hfsmps = {
618 .linear_ranges = (struct linear_range[]) {
619 REGULATOR_LINEAR_RANGE(320000, 0, 216, 8000),
620 },
621 .n_linear_ranges = 1,
622 .n_voltages = 217,
623 .ops = &rpm_smps_ldo_ops,
624};
625
626static const struct regulator_desc pm660_ht_nldo = {
627 .linear_ranges = (struct linear_range[]) {
628 REGULATOR_LINEAR_RANGE(312000, 0, 124, 8000),
629 },
630 .n_linear_ranges = 1,
631 .n_voltages = 125,
632 .ops = &rpm_smps_ldo_ops,
633};
634
635static const struct regulator_desc pm660_ht_lvpldo = {
636 .linear_ranges = (struct linear_range[]) {
637 REGULATOR_LINEAR_RANGE(1504000, 0, 62, 8000),
638 },
639 .n_linear_ranges = 1,
640 .n_voltages = 63,
641 .ops = &rpm_smps_ldo_ops,
642};
643
644static const struct regulator_desc pm660_nldo660 = {
645 .linear_ranges = (struct linear_range[]) {
646 REGULATOR_LINEAR_RANGE(320000, 0, 123, 8000),
647 },
648 .n_linear_ranges = 1,
649 .n_voltages = 124,
650 .ops = &rpm_smps_ldo_ops,
651};
652
653static const struct regulator_desc pm660_pldo660 = {
654 .linear_ranges = (struct linear_range[]) {
655 REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000),
656 },
657 .n_linear_ranges = 1,
658 .n_voltages = 256,
659 .ops = &rpm_smps_ldo_ops,
660};
661
662static const struct regulator_desc pm660l_bob = {
663 .linear_ranges = (struct linear_range[]) {
664 REGULATOR_LINEAR_RANGE(1800000, 0, 84, 32000),
665 },
666 .n_linear_ranges = 1,
667 .n_voltages = 85,
668 .ops = &rpm_bob_ops,
669};
670
95b5f3ef
IC		 671static const struct regulator_desc pm6125_ftsmps = {
672 .linear_ranges = (struct linear_range[]) {
673 REGULATOR_LINEAR_RANGE(300000, 0, 268, 4000),
674 },
675 .n_linear_ranges = 1,
676 .n_voltages = 269,
677 .ops = &rpm_smps_ldo_ops,
678};
679
0cda8c43
KD		 680static const struct regulator_desc pmic5_ftsmps520 = {
681 .linear_ranges = (struct linear_range[]) {
682 REGULATOR_LINEAR_RANGE(300000, 0, 263, 4000),
683 },
684 .n_linear_ranges = 1,
685 .n_voltages = 264,
686 .ops = &rpm_smps_ldo_ops,
687};
688
91016037
KD		 689static const struct regulator_desc pmic5_hfsmps515 = {
690 .linear_ranges = (struct linear_range[]) {
691 REGULATOR_LINEAR_RANGE(320000, 0, 235, 16000),
692 },
693 .n_linear_ranges = 1,
694 .n_voltages = 236,
695 .ops = &rpm_smps_ldo_ops,
696};
697
f589d95b 698static const struct regulator_desc pms405_hfsmps3 = {
60ab7f41 699 .linear_ranges = (struct linear_range[]) {
f589d95b
BA		 700 REGULATOR_LINEAR_RANGE(320000, 0, 215, 8000),
701 },
702 .n_linear_ranges = 1,
703 .n_voltages = 216,
704 .ops = &rpm_smps_ldo_ops,
705};
706
707static const struct regulator_desc pms405_nldo300 = {
60ab7f41 708 .linear_ranges = (struct linear_range[]) {
f589d95b
BA		 709 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
710 },
711 .n_linear_ranges = 1,
712 .n_voltages = 128,
713 .ops = &rpm_smps_ldo_ops,
714};
715
716static const struct regulator_desc pms405_nldo1200 = {
60ab7f41 717 .linear_ranges = (struct linear_range[]) {
f589d95b
BA		 718 REGULATOR_LINEAR_RANGE(312000, 0, 127, 8000),
719 },
720 .n_linear_ranges = 1,
721 .n_voltages = 128,
722 .ops = &rpm_smps_ldo_ops,
723};
724
725static const struct regulator_desc pms405_pldo50 = {
60ab7f41 726 .linear_ranges = (struct linear_range[]) {
f589d95b
BA		 727 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
728 },
729 .n_linear_ranges = 1,
730 .n_voltages = 129,
731 .ops = &rpm_smps_ldo_ops,
732};
733
734static const struct regulator_desc pms405_pldo150 = {
60ab7f41 735 .linear_ranges = (struct linear_range[]) {
f589d95b
BA		 736 REGULATOR_LINEAR_RANGE(1664000, 0, 128, 16000),
737 },
738 .n_linear_ranges = 1,
739 .n_voltages = 129,
740 .ops = &rpm_smps_ldo_ops,
741};
742
743static const struct regulator_desc pms405_pldo600 = {
60ab7f41 744 .linear_ranges = (struct linear_range[]) {
f589d95b
BA		 745 REGULATOR_LINEAR_RANGE(1256000, 0, 98, 8000),
746 },
747 .n_linear_ranges = 1,
748 .n_voltages = 99,
749 .ops = &rpm_smps_ldo_ops,
750};
751
47894c85
K		 752static const struct regulator_desc mp5496_smpa2 = {
753 .linear_ranges = (struct linear_range[]) {
122e951e 754 REGULATOR_LINEAR_RANGE(600000, 0, 127, 12500),
47894c85
K		 755 },
756 .n_linear_ranges = 1,
122e951e 757 .n_voltages = 128,
47894c85
K		 758 .ops = &rpm_mp5496_ops,
759};
760
761static const struct regulator_desc mp5496_ldoa2 = {
762 .linear_ranges = (struct linear_range[]) {
122e951e 763 REGULATOR_LINEAR_RANGE(800000, 0, 127, 25000),
47894c85
K		 764 },
765 .n_linear_ranges = 1,
122e951e 766 .n_voltages = 128,
47894c85
K		 767 .ops = &rpm_mp5496_ops,
768};
769
400c9315
SG		 770static const struct regulator_desc pm2250_lvftsmps = {
771 .linear_ranges = (struct linear_range[]) {
772 REGULATOR_LINEAR_RANGE(320000, 0, 269, 4000),
773 },
774 .n_linear_ranges = 1,
775 .n_voltages = 270,
776 .ops = &rpm_smps_ldo_ops,
777};
778
779static const struct regulator_desc pm2250_ftsmps = {
780 .linear_ranges = (struct linear_range[]) {
781 REGULATOR_LINEAR_RANGE(640000, 0, 269, 8000),
782 },
783 .n_linear_ranges = 1,
784 .n_voltages = 270,
785 .ops = &rpm_smps_ldo_ops,
786};
787
da65e367
BA		 788struct rpm_regulator_data {
789 const char *name;
790 u32 type;
791 u32 id;
792 const struct regulator_desc *desc;
793 const char *supply;
794};
795
47894c85
K		 796static const struct rpm_regulator_data rpm_mp5496_regulators[] = {
797 { "s2", QCOM_SMD_RPM_SMPA, 2, &mp5496_smpa2, "s2" },
798 { "l2", QCOM_SMD_RPM_LDOA, 2, &mp5496_ldoa2, "l2" },
799 {}
800};
801
13b3d005
IC		 802static const struct rpm_regulator_data rpm_pm2250_regulators[] = {
803 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm2250_lvftsmps, "vdd_s1" },
804 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm2250_lvftsmps, "vdd_s2" },
805 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm2250_lvftsmps, "vdd_s3" },
806 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm2250_ftsmps, "vdd_s4" },
807 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
808 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
809 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
810 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
811 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
812 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
813 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
814 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
815 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
816 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
817 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
818 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_nldo660, "vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12" },
819 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
820 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
821 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
822 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_ht_lvpldo, "vdd_l13_l14_l15_l16" },
823 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
824 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
825 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
826 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
827 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
828 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm660_pldo660, "vdd_l4_l17_l18_l19_l20_l21_l22" },
829 {}
830};
831
95b5f3ef
IC		 832static const struct rpm_regulator_data rpm_pm6125_regulators[] = {
833 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm6125_ftsmps, "vdd_s1" },
834 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm6125_ftsmps, "vdd_s2" },
835 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm6125_ftsmps, "vdd_s3" },
836 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm6125_ftsmps, "vdd_s4" },
837 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
838 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_hfsmps, "vdd_s6" },
839 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_hfsmps, "vdd_s7" },
840 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm6125_ftsmps, "vdd_s8" },
841 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
842 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_nldo660, "vdd_l2_l3_l4" },
843 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3_l4" },
844 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm660_nldo660, "vdd_l2_l3_l4" },
845 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
846 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_nldo660, "vdd_l6_l8" },
847 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
848 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_nldo660, "vdd_l6_l8" },
849 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l9_l11" },
850 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l10_l13_l14" },
851 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l9_l11" },
852 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l12_l16" },
853 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l10_l13_l14" },
854 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l10_l13_l14" },
855 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
856 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_ht_lvpldo, "vdd_l12_l16" },
857 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
858 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_nldo660, "vdd_l1_l7_l17_l18" },
859 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
860 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
861 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
862 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm660_pldo660, "vdd_l5_l15_l19_l20_l21_l22" },
863 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm660_pldo660, "vdd_l23_l24" },
864 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm660_pldo660, "vdd_l23_l24" },
865 { }
866};
867
a39d0100
IC		 868static const struct rpm_regulator_data rpm_pm660_regulators[] = {
869 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm660_ftsmps, "vdd_s1" },
870 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm660_ftsmps, "vdd_s2" },
871 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm660_ftsmps, "vdd_s3" },
872 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm660_hfsmps, "vdd_s4" },
873 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm660_hfsmps, "vdd_s5" },
874 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm660_hfsmps, "vdd_s6" },
875 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm660_nldo660, "vdd_l1_l6_l7" },
876 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm660_ht_nldo, "vdd_l2_l3" },
877 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm660_nldo660, "vdd_l2_l3" },
878 /* l4 is unaccessible on PM660 */
879 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm660_ht_nldo, "vdd_l5" },
880 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm660_ht_nldo, "vdd_l1_l6_l7" },
881 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm660_ht_nldo, "vdd_l1_l6_l7" },
882 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
883 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
884 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
885 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
886 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
887 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
888 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm660_ht_lvpldo, "vdd_l8_l9_l10_l11_l12_l13_l14" },
889 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
890 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
891 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
892 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
893 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm660_pldo660, "vdd_l15_l16_l17_l18_l19" },
894 { }
895};
896
897static const struct rpm_regulator_data rpm_pm660l_regulators[] = {
898 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm660_ftsmps, "vdd_s1" },
899 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm660_ftsmps, "vdd_s2" },
900 { "s3", QCOM_SMD_RPM_RWCX, 0, &pm660_ftsmps, "vdd_s3_s4" },
901 { "s5", QCOM_SMD_RPM_RWMX, 0, &pm660_ftsmps, "vdd_s5" },
902 { "l1", QCOM_SMD_RPM_LDOB, 1, &pm660_nldo660, "vdd_l1_l9_l10" },
903 { "l2", QCOM_SMD_RPM_LDOB, 2, &pm660_pldo660, "vdd_l2" },
904 { "l3", QCOM_SMD_RPM_LDOB, 3, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
905 { "l4", QCOM_SMD_RPM_LDOB, 4, &pm660_pldo660, "vdd_l4_l6" },
906 { "l5", QCOM_SMD_RPM_LDOB, 5, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
907 { "l6", QCOM_SMD_RPM_LDOB, 6, &pm660_pldo660, "vdd_l4_l6" },
908 { "l7", QCOM_SMD_RPM_LDOB, 7, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
909 { "l8", QCOM_SMD_RPM_LDOB, 8, &pm660_pldo660, "vdd_l3_l5_l7_l8" },
910 { "l9", QCOM_SMD_RPM_RWLC, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" },
911 { "l10", QCOM_SMD_RPM_RWLM, 0, &pm660_ht_nldo, "vdd_l1_l9_l10" },
912 { "bob", QCOM_SMD_RPM_BOBB, 1, &pm660l_bob, "vdd_bob", },
913 { }
914};
915
8e584e84
IC		 916static const struct rpm_regulator_data rpm_pm8226_regulators[] = {
917 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8226_hfsmps, "vdd_s1" },
918 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8226_ftsmps, "vdd_s2" },
919 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8226_hfsmps, "vdd_s3" },
920 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8226_hfsmps, "vdd_s4" },
921 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8226_hfsmps, "vdd_s5" },
922 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
923 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
924 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8226_nldo, "vdd_l3_l24_l26" },
925 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
926 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_nldo, "vdd_l1_l2_l4_l5" },
927 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
928 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
929 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
930 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
931 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8226_pldo, "vdd_l10_l11_l13" },
932 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8226_pldo, "vdd_l10_l11_l13" },
933 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8226_pldo, "vdd_l12_l14" },
934 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8226_pldo, "vdd_l10_l11_l13" },
935 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8226_pldo, "vdd_l12_l14" },
936 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
937 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
938 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
939 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8226_pldo, "vdd_l15_l16_l17_l18" },
940 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
941 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
942 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
943 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
944 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
945 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8226_nldo, "vdd_l3_l24_l26" },
946 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8226_pldo, "vdd_l25" },
947 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8226_nldo, "vdd_l3_l24_l26" },
948 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8226_pldo, "vdd_l6_l7_l8_l9_l27" },
949 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8226_pldo, "vdd_l19_l20_l21_l22_l23_l28" },
950 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8226_switch, "vdd_lvs1" },
951 {}
952};
953
da65e367
BA		 954static const struct rpm_regulator_data rpm_pm8841_regulators[] = {
955 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" },
956 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" },
957 { "s3", QCOM_SMD_RPM_SMPB, 3, &pm8x41_hfsmps, "vdd_s3" },
958 { "s4", QCOM_SMD_RPM_SMPB, 4, &pm8841_ftsmps, "vdd_s4" },
959 { "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" },
960 { "s6", QCOM_SMD_RPM_SMPB, 6, &pm8841_ftsmps, "vdd_s6" },
961 { "s7", QCOM_SMD_RPM_SMPB, 7, &pm8841_ftsmps, "vdd_s7" },
962 { "s8", QCOM_SMD_RPM_SMPB, 8, &pm8841_ftsmps, "vdd_s8" },
963 {}
964};
965
bc4d1932
SG		 966static const struct rpm_regulator_data rpm_pm8909_regulators[] = {
967 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
968 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_hvo_smps, "vdd_s2" },
969 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1" },
970 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l2_l5" },
971 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l3_l6_l10" },
972 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l7" },
973 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8226_pldo, "vdd_l2_l5" },
974 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8226_pldo, "vdd_l3_l6_l10" },
975 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8226_pldo, "vdd_l4_l7" },
976 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l11_l15_l18" },
977 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
978 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_nldo, "vdd_l3_l6_l10" },
979 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8226_pldo, "vdd_l8_l11_l15_l18" },
980 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
981 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l13" },
982 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
983 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l11_l15_l18" },
984 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l9_l12_l14_l17" },
985 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l11_l15_l18" },
986 {}
987};
988
57d65676
AG		 989static const struct rpm_regulator_data rpm_pm8916_regulators[] = {
990 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
991 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_lvo_smps, "vdd_s2" },
992 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8916_buck_lvo_smps, "vdd_s3" },
993 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8916_buck_hvo_smps, "vdd_s4" },
994 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1_l2_l3" },
995 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l1_l2_l3" },
996 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l1_l2_l3" },
997 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l5_l6" },
998 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8916_pldo, "vdd_l4_l5_l6" },
999 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8916_pldo, "vdd_l4_l5_l6" },
1000 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8916_pldo, "vdd_l7" },
1001 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
1002 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
1003 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1004 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1005 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1006 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1007 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1008 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1009 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1010 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1011 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
1012 {}
1013};
1014
da65e367
BA		 1015static const struct rpm_regulator_data rpm_pm8941_regulators[] = {
1016 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" },
1017 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" },
1018 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8x41_hfsmps, "vdd_s3" },
1019 { "s4", QCOM_SMD_RPM_BOOST, 1, &pm8941_boost },
1020
1021 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8941_nldo, "vdd_l1_l3" },
1022 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8941_nldo, "vdd_l2_lvs1_2_3" },
1023 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8941_nldo, "vdd_l1_l3" },
1024 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8941_nldo, "vdd_l4_l11" },
1025 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8941_lnldo, "vdd_l5_l7" },
1026 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
1027 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8941_lnldo, "vdd_l5_l7" },
1028 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
1029 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
1030 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
1031 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8941_nldo, "vdd_l4_l11" },
1032 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
1033 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
1034 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
1035 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
1036 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
1037 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
1038 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
1039 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
1040 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
1041 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8941_pldo, "vdd_l21" },
1042 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
1043 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
1044 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
1045
1046 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8941_switch, "vdd_l2_lvs1_2_3" },
1047 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8941_switch, "vdd_l2_lvs1_2_3" },
1048 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pm8941_switch, "vdd_l2_lvs1_2_3" },
1049
1050 { "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" },
1051 { "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" },
1052
1053 {}
1054};
1055
e44adca5
ADR		 1056static const struct rpm_regulator_data rpm_pm8950_regulators[] = {
1057 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8950_hfsmps, "vdd_s1" },
1058 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8950_hfsmps, "vdd_s2" },
1059 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8950_hfsmps, "vdd_s3" },
1060 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8950_hfsmps, "vdd_s4" },
b11b3d21 1061 /* S5 is managed via SPMI. */
e44adca5
ADR		 1062 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_hfsmps, "vdd_s6" },
1063
1064 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8950_ult_nldo, "vdd_l1_l19" },
1065 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8950_ult_nldo, "vdd_l2_l23" },
1066 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8950_ult_nldo, "vdd_l3" },
b11b3d21
KD		 1067 /* L4 seems not to exist. */
1068 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
1069 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
1070 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_pldo_lv, "vdd_l5_l6_l7_l16" },
e44adca5
ADR		 1071 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1072 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1073 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_nldo, "vdd_l9_l10_l13_l14_l15_l18"},
b11b3d21
KD		 1074 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1075 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1076 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1077 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1078 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l9_l10_l13_l14_l15_l18" },
1079 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l5_l6_l7_l16" },
1080 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l8_l11_l12_l17_l22" },
1081 /* L18 seems not to exist. */
1082 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8950_pldo, "vdd_l1_l19" },
1083 /* L20 & L21 seem not to exist. */
1084 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_pldo, "vdd_l8_l11_l12_l17_l22" },
1085 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8950_pldo, "vdd_l2_l23" },
e44adca5
ADR		 1086 {}
1087};
1088
b1a2fb10
VL		 1089static const struct rpm_regulator_data rpm_pm8953_regulators[] = {
1090 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_hfsmps, "vdd_s1" },
1091 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_hfsmps, "vdd_s2" },
1092 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
1093 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
1094 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8950_ftsmps2p5, "vdd_s5" },
1095 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8950_ftsmps2p5, "vdd_s6" },
1096 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_hfsmps, "vdd_s7" },
1097
1098 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8953_ult_nldo, "vdd_l1" },
1099 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8953_ult_nldo, "vdd_l2_l3" },
1100 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8953_ult_nldo, "vdd_l2_l3" },
1101 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1102 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1103 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1104 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1105 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1106 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1107 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1108 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1109 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1110 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1111 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1112 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8950_ult_pldo, "vdd_l8_l11_l12_l13_l14_l15" },
1113 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8950_ult_pldo, "vdd_l4_l5_l6_l7_l16_l19" },
1114 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1115 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1116 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8953_ult_nldo, "vdd_l4_l5_l6_l7_l16_l19" },
1117 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8953_lnldo, "vdd_l20" },
1118 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8953_lnldo, "vdd_l21" },
1119 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8950_ult_pldo, "vdd_l9_l10_l17_l18_l22" },
1120 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8953_ult_nldo, "vdd_l23" },
1121 {}
1122};
1123
14a16992
RN		 1124static const struct rpm_regulator_data rpm_pm8994_regulators[] = {
1125 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8994_ftsmps, "vdd_s1" },
1126 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8994_ftsmps, "vdd_s2" },
1127 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8994_hfsmps, "vdd_s3" },
1128 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8994_hfsmps, "vdd_s4" },
1129 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8994_hfsmps, "vdd_s5" },
1130 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8994_ftsmps, "vdd_s6" },
1131 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8994_hfsmps, "vdd_s7" },
1132 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8994_ftsmps, "vdd_s8" },
1133 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8994_ftsmps, "vdd_s9" },
1134 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8994_ftsmps, "vdd_s10" },
1135 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8994_ftsmps, "vdd_s11" },
1136 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8994_ftsmps, "vdd_s12" },
1137 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8994_nldo, "vdd_l1" },
1138 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8994_nldo, "vdd_l2_l26_l28" },
1139 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8994_nldo, "vdd_l3_l11" },
1140 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8994_nldo, "vdd_l4_l27_l31" },
1141 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8994_lnldo, "vdd_l5_l7" },
1142 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8994_pldo, "vdd_l6_l12_l32" },
1143 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8994_lnldo, "vdd_l5_l7" },
1144 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8994_pldo, "vdd_l8_l16_l30" },
1145 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1146 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1147 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8994_nldo, "vdd_l3_l11" },
1148 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8994_pldo, "vdd_l6_l12_l32" },
1149 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1150 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8994_pldo, "vdd_l14_l15" },
1151 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8994_pldo, "vdd_l14_l15" },
1152 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8994_pldo, "vdd_l8_l16_l30" },
1153 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8994_pldo, "vdd_l17_l29" },
1154 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1155 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1156 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8994_pldo, "vdd_l20_l21" },
1157 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8994_pldo, "vdd_l20_l21" },
1158 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8994_pldo, "vdd_l9_l10_l18_l22" },
1159 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1160 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8994_pldo, "vdd_l13_l19_l23_l24" },
1161 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8994_pldo, "vdd_l25" },
1162 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8994_nldo, "vdd_l2_l26_l28" },
1163 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8994_nldo, "vdd_l4_l27_l31" },
1164 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8994_nldo, "vdd_l2_l26_l28" },
1165 { "l29", QCOM_SMD_RPM_LDOA, 29, &pm8994_pldo, "vdd_l17_l29" },
1166 { "l30", QCOM_SMD_RPM_LDOA, 30, &pm8994_pldo, "vdd_l8_l16_l30" },
1167 { "l31", QCOM_SMD_RPM_LDOA, 31, &pm8994_nldo, "vdd_l4_l27_l31" },
1168 { "l32", QCOM_SMD_RPM_LDOA, 32, &pm8994_pldo, "vdd_l6_l12_l32" },
1169 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8994_switch, "vdd_lvs1_2" },
1170 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8994_switch, "vdd_lvs1_2" },
1171
1172 {}
1173};
1174
13b3d005
IC		 1175static const struct rpm_regulator_data rpm_pm8998_regulators[] = {
1176 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8998_ftsmps, "vdd_s1" },
1177 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8998_ftsmps, "vdd_s2" },
1178 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8998_hfsmps, "vdd_s3" },
1179 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8998_hfsmps, "vdd_s4" },
1180 { "s5", QCOM_SMD_RPM_SMPA, 5, &pm8998_hfsmps, "vdd_s5" },
1181 { "s6", QCOM_SMD_RPM_SMPA, 6, &pm8998_ftsmps, "vdd_s6" },
1182 { "s7", QCOM_SMD_RPM_SMPA, 7, &pm8998_ftsmps, "vdd_s7" },
1183 { "s8", QCOM_SMD_RPM_SMPA, 8, &pm8998_ftsmps, "vdd_s8" },
1184 { "s9", QCOM_SMD_RPM_SMPA, 9, &pm8998_ftsmps, "vdd_s9" },
1185 { "s10", QCOM_SMD_RPM_SMPA, 10, &pm8998_ftsmps, "vdd_s10" },
1186 { "s11", QCOM_SMD_RPM_SMPA, 11, &pm8998_ftsmps, "vdd_s11" },
1187 { "s12", QCOM_SMD_RPM_SMPA, 12, &pm8998_ftsmps, "vdd_s12" },
1188 { "s13", QCOM_SMD_RPM_SMPA, 13, &pm8998_ftsmps, "vdd_s13" },
1189 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8998_nldo, "vdd_l1_l27" },
1190 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8998_nldo, "vdd_l2_l8_l17" },
1191 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8998_nldo, "vdd_l3_l11" },
1192 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8998_nldo, "vdd_l4_l5" },
1193 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8998_nldo, "vdd_l4_l5" },
1194 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8998_pldo, "vdd_l6" },
1195 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1196 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8998_nldo, "vdd_l2_l8_l17" },
1197 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8998_pldo, "vdd_l9" },
1198 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8998_pldo, "vdd_l10_l23_l25" },
1199 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8998_nldo, "vdd_l3_l11" },
1200 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1201 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8998_pldo, "vdd_l13_l19_l21" },
1202 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1203 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8998_pldo_lv, "vdd_l7_l12_l14_l15" },
1204 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8998_pldo, "vdd_l16_l28" },
1205 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8998_nldo, "vdd_l2_l8_l17" },
1206 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8998_pldo, "vdd_l18_l22" },
1207 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8998_pldo, "vdd_l13_l19_l21" },
1208 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8998_pldo, "vdd_l20_l24" },
1209 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8998_pldo, "vdd_l13_l19_l21" },
1210 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8998_pldo, "vdd_l18_l22" },
1211 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8998_pldo, "vdd_l10_l23_l25" },
1212 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8998_pldo, "vdd_l20_l24" },
1213 { "l25", QCOM_SMD_RPM_LDOA, 25, &pm8998_pldo, "vdd_l10_l23_l25" },
1214 { "l26", QCOM_SMD_RPM_LDOA, 26, &pm8998_nldo, "vdd_l26" },
1215 { "l27", QCOM_SMD_RPM_LDOA, 27, &pm8998_nldo, "vdd_l1_l27" },
1216 { "l28", QCOM_SMD_RPM_LDOA, 28, &pm8998_pldo, "vdd_l16_l28" },
1217 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8998_switch, "vdd_lvs1_lvs2" },
1218 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8998_switch, "vdd_lvs1_lvs2" },
1219 {}
1220};
1221
8e584e84
IC		 1222static const struct rpm_regulator_data rpm_pma8084_regulators[] = {
1223 { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" },
1224 { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" },
1225 { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" },
1226 { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" },
1227 { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" },
1228 { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" },
1229 { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" },
1230 { "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" },
1231 { "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" },
1232 { "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" },
1233 { "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" },
1234 { "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" },
1235
1236 { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" },
1237 { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
1238 { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
1239 { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
1240 { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" },
1241 { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1242 { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" },
1243 { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" },
1244 { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1245 { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1246 { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" },
1247 { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1248 { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1249 { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1250 { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1251 { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" },
1252 { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" },
1253 { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" },
1254 { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" },
1255 { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1256 { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" },
1257 { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" },
1258 { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1259 { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
1260 { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" },
1261 { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
1262 { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
1263
1264 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch },
1265 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch },
1266 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch },
1267 { "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch },
1268 { "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch },
1269
1270 {}
1271};
1272
86332c34
BA		 1273static const struct rpm_regulator_data rpm_pmi8994_regulators[] = {
1274 { "s1", QCOM_SMD_RPM_SMPB, 1, &pmi8994_ftsmps, "vdd_s1" },
1275 { "s2", QCOM_SMD_RPM_SMPB, 2, &pmi8994_hfsmps, "vdd_s2" },
0d46f698 1276 { "s3", QCOM_SMD_RPM_SMPB, 3, &pmi8994_hfsmps, "vdd_s3" },
86332c34
BA		 1277 { "boost-bypass", QCOM_SMD_RPM_BBYB, 1, &pmi8994_bby, "vdd_bst_byp" },
1278 {}
1279};
1280
3cdb741e
BA		 1281static const struct rpm_regulator_data rpm_pmi8998_regulators[] = {
1282 { "bob", QCOM_SMD_RPM_BOBB, 1, &pmi8998_bob, "vdd_bob" },
1283 {}
1284};
1285
0cda8c43
KD		 1286static const struct rpm_regulator_data rpm_pmr735a_regulators[] = {
1287 { "s1", QCOM_SMD_RPM_SMPE, 1, &pmic5_ftsmps520, "vdd_s1"},
1288 { "s2", QCOM_SMD_RPM_SMPE, 2, &pmic5_ftsmps520, "vdd_s2"},
91016037 1289 { "s3", QCOM_SMD_RPM_SMPE, 3, &pmic5_hfsmps515, "vdd_s3"},
0cda8c43
KD		 1290 { "l1", QCOM_SMD_RPM_LDOE, 1, &pm660_nldo660, "vdd_l1_l2"},
1291 { "l2", QCOM_SMD_RPM_LDOE, 2, &pm660_nldo660, "vdd_l1_l2"},
1292 { "l3", QCOM_SMD_RPM_LDOE, 3, &pm660_nldo660, "vdd_l3"},
1293 { "l4", QCOM_SMD_RPM_LDOE, 4, &pm660_ht_lvpldo, "vdd_l4"},
1294 { "l5", QCOM_SMD_RPM_LDOE, 5, &pm660_nldo660, "vdd_l5_l6"},
1295 { "l6", QCOM_SMD_RPM_LDOE, 6, &pm660_nldo660, "vdd_l5_l6"},
1296 { "l7", QCOM_SMD_RPM_LDOE, 7, &pm660_pldo660, "vdd_l7_bob"},
1297 {}
1298};
1299
f589d95b
BA		 1300static const struct rpm_regulator_data rpm_pms405_regulators[] = {
1301 { "s1", QCOM_SMD_RPM_SMPA, 1, &pms405_hfsmps3, "vdd_s1" },
1302 { "s2", QCOM_SMD_RPM_SMPA, 2, &pms405_hfsmps3, "vdd_s2" },
1303 { "s3", QCOM_SMD_RPM_SMPA, 3, &pms405_hfsmps3, "vdd_s3" },
1304 { "s4", QCOM_SMD_RPM_SMPA, 4, &pms405_hfsmps3, "vdd_s4" },
1305 { "s5", QCOM_SMD_RPM_SMPA, 5, &pms405_hfsmps3, "vdd_s5" },
1306 { "l1", QCOM_SMD_RPM_LDOA, 1, &pms405_nldo1200, "vdd_l1_l2" },
1307 { "l2", QCOM_SMD_RPM_LDOA, 2, &pms405_nldo1200, "vdd_l1_l2" },
1308 { "l3", QCOM_SMD_RPM_LDOA, 3, &pms405_nldo1200, "vdd_l3_l8" },
1309 { "l4", QCOM_SMD_RPM_LDOA, 4, &pms405_nldo300, "vdd_l4" },
1310 { "l5", QCOM_SMD_RPM_LDOA, 5, &pms405_pldo600, "vdd_l5_l6" },
1311 { "l6", QCOM_SMD_RPM_LDOA, 6, &pms405_pldo600, "vdd_l5_l6" },
1312 { "l7", QCOM_SMD_RPM_LDOA, 7, &pms405_pldo150, "vdd_l7" },
1313 { "l8", QCOM_SMD_RPM_LDOA, 8, &pms405_nldo1200, "vdd_l3_l8" },
1314 { "l9", QCOM_SMD_RPM_LDOA, 9, &pms405_nldo1200, "vdd_l9" },
1315 { "l10", QCOM_SMD_RPM_LDOA, 10, &pms405_pldo50, "vdd_l10_l11_l12_l13" },
1316 { "l11", QCOM_SMD_RPM_LDOA, 11, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1317 { "l12", QCOM_SMD_RPM_LDOA, 12, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1318 { "l13", QCOM_SMD_RPM_LDOA, 13, &pms405_pldo150, "vdd_l10_l11_l12_l13" },
1319 {}
1320};
1321
da65e367 1322static const struct of_device_id rpm_of_match[] = {
47894c85 1323 { .compatible = "qcom,rpm-mp5496-regulators", .data = &rpm_mp5496_regulators },
a39d0100 1324 { .compatible = "qcom,rpm-pm2250-regulators", .data = &rpm_pm2250_regulators },
95b5f3ef 1325 { .compatible = "qcom,rpm-pm6125-regulators", .data = &rpm_pm6125_regulators },
a39d0100
IC		 1326 { .compatible = "qcom,rpm-pm660-regulators", .data = &rpm_pm660_regulators },
1327 { .compatible = "qcom,rpm-pm660l-regulators", .data = &rpm_pm660l_regulators },
1328 { .compatible = "qcom,rpm-pm8226-regulators", .data = &rpm_pm8226_regulators },
da65e367 1329 { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators },
bc4d1932 1330 { .compatible = "qcom,rpm-pm8909-regulators", .data = &rpm_pm8909_regulators },
57d65676 1331 { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators },
da65e367 1332 { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators },
e44adca5 1333 { .compatible = "qcom,rpm-pm8950-regulators", .data = &rpm_pm8950_regulators },
b1a2fb10 1334 { .compatible = "qcom,rpm-pm8953-regulators", .data = &rpm_pm8953_regulators },
14a16992 1335 { .compatible = "qcom,rpm-pm8994-regulators", .data = &rpm_pm8994_regulators },
3cdb741e 1336 { .compatible = "qcom,rpm-pm8998-regulators", .data = &rpm_pm8998_regulators },
ee01d0c9 1337 { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators },
86332c34 1338 { .compatible = "qcom,rpm-pmi8994-regulators", .data = &rpm_pmi8994_regulators },
3cdb741e 1339 { .compatible = "qcom,rpm-pmi8998-regulators", .data = &rpm_pmi8998_regulators },
0cda8c43 1340 { .compatible = "qcom,rpm-pmr735a-regulators", .data = &rpm_pmr735a_regulators },
f589d95b 1341 { .compatible = "qcom,rpm-pms405-regulators", .data = &rpm_pms405_regulators },
da65e367
BA		 1342 {}
1343};
1344MODULE_DEVICE_TABLE(of, rpm_of_match);
1345
14e2976f
KD		 1346/**
1347 * rpm_regulator_init_vreg() - initialize all attributes of a qcom_smd-regulator
1348 * @vreg: Pointer to the individual qcom_smd-regulator resource
1349 * @dev: Pointer to the top level qcom_smd-regulator PMIC device
1350 * @node: Pointer to the individual qcom_smd-regulator resource
1351 * device node
1352 * @rpm: Pointer to the rpm bus node
1353 * @pmic_rpm_data: Pointer to a null-terminated array of qcom_smd-regulator
1354 * resources defined for the top level PMIC device
1355 *
1356 * Return: 0 on success, errno on failure
1357 */
1358static int rpm_regulator_init_vreg(struct qcom_rpm_reg *vreg, struct device *dev,
1359 struct device_node *node, struct qcom_smd_rpm *rpm,
1360 const struct rpm_regulator_data *pmic_rpm_data)
da65e367 1361{
14e2976f
KD		 1362 struct regulator_config config = {};
1363 const struct rpm_regulator_data *rpm_data;
da65e367 1364 struct regulator_dev *rdev;
14e2976f
KD		 1365 int ret;
1366
1367 for (rpm_data = pmic_rpm_data; rpm_data->name; rpm_data++)
1368 if (of_node_name_eq(node, rpm_data->name))
1369 break;
1370
1371 if (!rpm_data->name) {
1372 dev_err(dev, "Unknown regulator %pOFn\n", node);
1373 return -EINVAL;
1374 }
1375
1376 vreg->dev = dev;
1377 vreg->rpm = rpm;
1378 vreg->type = rpm_data->type;
1379 vreg->id = rpm_data->id;
1380
1381 memcpy(&vreg->desc, rpm_data->desc, sizeof(vreg->desc));
1382 vreg->desc.name = rpm_data->name;
1383 vreg->desc.supply_name = rpm_data->supply;
1384 vreg->desc.owner = THIS_MODULE;
1385 vreg->desc.type = REGULATOR_VOLTAGE;
1386 vreg->desc.of_match = rpm_data->name;
1387
1388 config.dev = dev;
1389 config.of_node = node;
1390 config.driver_data = vreg;
1391
1392 rdev = devm_regulator_register(dev, &vreg->desc, &config);
1393 if (IS_ERR(rdev)) {
1394 ret = PTR_ERR(rdev);
1395 dev_err(dev, "%pOFn: devm_regulator_register() failed, ret=%d\n", node, ret);
1396 return ret;
1397 }
1398
1399 return 0;
1400}
1401
1402static int rpm_reg_probe(struct platform_device *pdev)
1403{
1404 struct device *dev = &pdev->dev;
1405 const struct rpm_regulator_data *vreg_data;
1406 struct device_node *node;
da65e367
BA		 1407 struct qcom_rpm_reg *vreg;
1408 struct qcom_smd_rpm *rpm;
14e2976f 1409 int ret;
da65e367
BA		 1410
1411 rpm = dev_get_drvdata(pdev->dev.parent);
1412 if (!rpm) {
14e2976f 1413 dev_err(&pdev->dev, "Unable to retrieve handle to rpm\n");
da65e367
BA		 1414 return -ENODEV;
1415 }
1416
14e2976f
KD		 1417 vreg_data = of_device_get_match_data(dev);
1418 if (!vreg_data)
e3b53b8a 1419 return -ENODEV;
e3b53b8a 1420
14e2976f 1421 for_each_available_child_of_node(dev->of_node, node) {
da65e367 1422 vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
6390d42c 1423 if (!vreg) {
1424 of_node_put(node);
da65e367 1425 return -ENOMEM;
6390d42c 1426 }
da65e367 1427
14e2976f
KD		 1428 ret = rpm_regulator_init_vreg(vreg, dev, node, rpm, vreg_data);
1429
1430 if (ret < 0) {
1431 of_node_put(node);
1432 return ret;
da65e367
BA		 1433 }
1434 }
1435
1436 return 0;
1437}
1438
1439static struct platform_driver rpm_reg_driver = {
1440 .probe = rpm_reg_probe,
1441 .driver = {
1442 .name = "qcom_rpm_smd_regulator",
1443 .of_match_table = rpm_of_match,
1444 },
1445};
1446
1447static int __init rpm_reg_init(void)
1448{
1449 return platform_driver_register(&rpm_reg_driver);
1450}
1451subsys_initcall(rpm_reg_init);
1452
1453static void __exit rpm_reg_exit(void)
1454{
1455 platform_driver_unregister(&rpm_reg_driver);
1456}
1457module_exit(rpm_reg_exit)
1458
1459MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
1460MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)