[linux-2.6-block.git] / drivers / regulator / pfuze100-regulator.c

/*
 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/regulator/of_regulator.h>
#include <linux/platform_device.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/pfuze100.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/regmap.h>

#define PFUZE_NUMREGS		128
#define PFUZE100_VOL_OFFSET	0
#define PFUZE100_STANDBY_OFFSET	1
#define PFUZE100_MODE_OFFSET	3
#define PFUZE100_CONF_OFFSET	4

#define PFUZE100_DEVICEID	0x0
#define PFUZE100_REVID		0x3
#define PFUZE100_FABID		0x4

#define PFUZE100_SW1ABVOL	0x20
#define PFUZE100_SW1CVOL	0x2e
#define PFUZE100_SW2VOL		0x35
#define PFUZE100_SW3AVOL	0x3c
#define PFUZE100_SW3BVOL	0x43
#define PFUZE100_SW4VOL		0x4a
#define PFUZE100_SWBSTCON1	0x66
#define PFUZE100_VREFDDRCON	0x6a
#define PFUZE100_VSNVSVOL	0x6b
#define PFUZE100_VGEN1VOL	0x6c
#define PFUZE100_VGEN2VOL	0x6d
#define PFUZE100_VGEN3VOL	0x6e
#define PFUZE100_VGEN4VOL	0x6f
#define PFUZE100_VGEN5VOL	0x70
#define PFUZE100_VGEN6VOL	0x71

enum chips {PFUZE100, PFUZE200, PFUZE_NUM};

struct pfuze_regulator {
	struct regulator_desc desc;
	unsigned char stby_reg;
	unsigned char stby_mask;
};

struct pfuze_chip {
	int	chip_id;
	struct regmap *regmap;
	struct device *dev;
	struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
	struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
};

static const int pfuze100_swbst[] = {
	5000000, 5050000, 5100000, 5150000,
};

static const int pfuze100_vsnvs[] = {
	1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
};

static const struct i2c_device_id pfuze_device_id[PFUZE_NUM] = {
	{.name = "pfuze100", .driver_data = PFUZE100},
	{.name = "pfuze200", .driver_data = PFUZE200},
};
MODULE_DEVICE_TABLE(i2c, pfuze_device_id);

static const struct of_device_id pfuze_dt_ids[PFUZE_NUM] = {
	{ .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
	{ .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
};
MODULE_DEVICE_TABLE(of, pfuze_dt_ids);

static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
{
	struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
	int id = rdev->desc->id;
	unsigned int ramp_bits;
	int ret;

	if (id < PFUZE100_SWBST) {
		ramp_delay = 12500 / ramp_delay;
		ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
		ret = regmap_update_bits(pfuze100->regmap,
					 rdev->desc->vsel_reg + 4,
					 0xc0, ramp_bits << 6);
		if (ret < 0)
			dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
	} else
		ret = -EACCES;

	return ret;
}

static struct regulator_ops pfuze100_ldo_regulator_ops = {
	.enable = regulator_enable_regmap,
	.disable = regulator_disable_regmap,
	.is_enabled = regulator_is_enabled_regmap,
	.list_voltage = regulator_list_voltage_linear,
	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	.get_voltage_sel = regulator_get_voltage_sel_regmap,
};

static struct regulator_ops pfuze100_fixed_regulator_ops = {
	.list_voltage = regulator_list_voltage_linear,
};

static struct regulator_ops pfuze100_sw_regulator_ops = {
	.list_voltage = regulator_list_voltage_linear,
	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	.set_voltage_time_sel = regulator_set_voltage_time_sel,
	.set_ramp_delay = pfuze100_set_ramp_delay,
};

static struct regulator_ops pfuze100_swb_regulator_ops = {
	.list_voltage = regulator_list_voltage_table,
	.map_voltage = regulator_map_voltage_ascend,
	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	.get_voltage_sel = regulator_get_voltage_sel_regmap,

};

#define PFUZE100_FIXED_REG(_chip, _name, base, voltage)	\
	[_chip ## _ ## _name] = {	\
		.desc = {	\
			.name = #_name,	\
			.n_voltages = 1,	\
			.ops = &pfuze100_fixed_regulator_ops,	\
			.type = REGULATOR_VOLTAGE,	\
			.id = _chip ## _ ## _name,	\
			.owner = THIS_MODULE,	\
			.min_uV = (voltage),	\
			.enable_reg = (base),	\
			.enable_mask = 0x10,	\
		},	\
	}

#define PFUZE100_SW_REG(_chip, _name, base, min, max, step)	\
	[_chip ## _ ## _name] = {	\
		.desc = {	\
			.name = #_name,\
			.n_voltages = ((max) - (min)) / (step) + 1,	\
			.ops = &pfuze100_sw_regulator_ops,	\
			.type = REGULATOR_VOLTAGE,	\
			.id = _chip ## _ ## _name,	\
			.owner = THIS_MODULE,	\
			.min_uV = (min),	\
			.uV_step = (step),	\
			.vsel_reg = (base) + PFUZE100_VOL_OFFSET,	\
			.vsel_mask = 0x3f,	\
		},	\
		.stby_reg = (base) + PFUZE100_STANDBY_OFFSET,	\
		.stby_mask = 0x3f,	\
	}

#define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages)	\
	[_chip ## _ ##  _name] = {	\
		.desc = {	\
			.name = #_name,	\
			.n_voltages = ARRAY_SIZE(voltages),	\
			.ops = &pfuze100_swb_regulator_ops,	\
			.type = REGULATOR_VOLTAGE,	\
			.id = _chip ## _ ## _name,	\
			.owner = THIS_MODULE,	\
			.volt_table = voltages,	\
			.vsel_reg = (base),	\
			.vsel_mask = (mask),	\
		},	\
	}

#define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step)	\
	[_chip ## _ ## _name] = {	\
		.desc = {	\
			.name = #_name,	\
			.n_voltages = ((max) - (min)) / (step) + 1,	\
			.ops = &pfuze100_ldo_regulator_ops,	\
			.type = REGULATOR_VOLTAGE,	\
			.id = _chip ## _ ## _name,	\
			.owner = THIS_MODULE,	\
			.min_uV = (min),	\
			.uV_step = (step),	\
			.vsel_reg = (base),	\
			.vsel_mask = 0xf,	\
			.enable_reg = (base),	\
			.enable_mask = 0x10,	\
		},	\
		.stby_reg = (base),	\
		.stby_mask = 0x20,	\
	}

/* PFUZE100 */
static struct pfuze_regulator pfuze100_regulators[] = {
	PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
	PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
	PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
	PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
	PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
	PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
	PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
	PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
	PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
	PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
	PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
	PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
	PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
	PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
	PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
};

static struct pfuze_regulator pfuze200_regulators[] = {
	PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
	PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
	PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
	PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
	PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
	PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
	PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
	PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
	PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
	PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
	PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
	PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
	PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
};

static struct pfuze_regulator *pfuze_regulators;

#ifdef CONFIG_OF
/* PFUZE100 */
static struct of_regulator_match pfuze100_matches[] = {
	{ .name = "sw1ab",	},
	{ .name = "sw1c",	},
	{ .name = "sw2",	},
	{ .name = "sw3a",	},
	{ .name = "sw3b",	},
	{ .name = "sw4",	},
	{ .name = "swbst",	},
	{ .name = "vsnvs",	},
	{ .name = "vrefddr",	},
	{ .name = "vgen1",	},
	{ .name = "vgen2",	},
	{ .name = "vgen3",	},
	{ .name = "vgen4",	},
	{ .name = "vgen5",	},
	{ .name = "vgen6",	},
};

/* PFUZE200 */
static struct of_regulator_match pfuze200_matches[] = {

	{ .name = "sw1ab",	},
	{ .name = "sw2",	},
	{ .name = "sw3a",	},
	{ .name = "sw3b",	},
	{ .name = "swbst",	},
	{ .name = "vsnvs",	},
	{ .name = "vrefddr",	},
	{ .name = "vgen1",	},
	{ .name = "vgen2",	},
	{ .name = "vgen3",	},
	{ .name = "vgen4",	},
	{ .name = "vgen5",	},
	{ .name = "vgen6",	},
};

static struct of_regulator_match *pfuze_matches;

static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
{
	struct device *dev = chip->dev;
	struct device_node *np, *parent;
	int ret;

	np = of_node_get(dev->of_node);
	if (!np)
		return -EINVAL;

	parent = of_get_child_by_name(np, "regulators");
	if (!parent) {
		dev_err(dev, "regulators node not found\n");
		return -EINVAL;
	}

	switch (chip->chip_id) {
	case PFUZE200:
		pfuze_matches = pfuze200_matches;
		ret = of_regulator_match(dev, parent, pfuze200_matches,
					 ARRAY_SIZE(pfuze200_matches));
		break;

	case PFUZE100:
	default:
		pfuze_matches = pfuze100_matches;
		ret = of_regulator_match(dev, parent, pfuze100_matches,
					 ARRAY_SIZE(pfuze100_matches));
		break;
	}

	of_node_put(parent);
	if (ret < 0) {
		dev_err(dev, "Error parsing regulator init data: %d\n",
			ret);
		return ret;
	}

	return 0;
}

static inline struct regulator_init_data *match_init_data(int index)
{
	return pfuze_matches[index].init_data;
}

static inline struct device_node *match_of_node(int index)
{
	return pfuze_matches[index].of_node;
}
#else
static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
{
	return 0;
}

static inline struct regulator_init_data *match_init_data(int index)
{
	return NULL;
}

static inline struct device_node *match_of_node(int index)
{
	return NULL;
}
#endif

static int pfuze_identify(struct pfuze_chip *pfuze_chip)
{
	unsigned int value;
	int ret;

	ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
	if (ret)
		return ret;

	if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
		/*
		 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
		 * as ID=8 in PFUZE100
		 */
		dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
	} else if ((value & 0x0f) != pfuze_chip->chip_id) {
		/* device id NOT match with your setting */
		dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
		return -ENODEV;
	}

	ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
	if (ret)
		return ret;
	dev_info(pfuze_chip->dev,
		 "Full layer: %x, Metal layer: %x\n",
		 (value & 0xf0) >> 4, value & 0x0f);

	ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
	if (ret)
		return ret;
	dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
		 (value & 0xc) >> 2, value & 0x3);

	return 0;
}

static const struct regmap_config pfuze_regmap_config = {
	.reg_bits = 8,
	.val_bits = 8,
	.max_register = PFUZE_NUMREGS - 1,
	.cache_type = REGCACHE_RBTREE,
};

static int pfuze100_regulator_probe(struct i2c_client *client,
				    const struct i2c_device_id *id)
{
	struct pfuze_chip *pfuze_chip;
	struct pfuze_regulator_platform_data *pdata =
	    dev_get_platdata(&client->dev);
	struct regulator_config config = { };
	int i, ret;
	const struct of_device_id *match;
	u32 regulator_num;
	u32 sw_check_start, sw_check_end;

	pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
			GFP_KERNEL);
	if (!pfuze_chip)
		return -ENOMEM;

	if (client->dev.of_node) {
		match = of_match_device(of_match_ptr(pfuze_dt_ids),
				&client->dev);
		if (!match) {
			dev_err(&client->dev, "Error: No device match found\n");
			return -ENODEV;
		}
		pfuze_chip->chip_id = (int)(long)match->data;
	} else if (id) {
		pfuze_chip->chip_id = id->driver_data;
	} else {
		dev_err(&client->dev, "No dts match or id table match found\n");
		return -ENODEV;
	}

	i2c_set_clientdata(client, pfuze_chip);
	pfuze_chip->dev = &client->dev;

	pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
	if (IS_ERR(pfuze_chip->regmap)) {
		ret = PTR_ERR(pfuze_chip->regmap);
		dev_err(&client->dev,
			"regmap allocation failed with err %d\n", ret);
		return ret;
	}

	ret = pfuze_identify(pfuze_chip);
	if (ret) {
		dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
		return ret;
	}

	/* use the right regulators after identify the right device */
	switch (pfuze_chip->chip_id) {
	case PFUZE200:
		pfuze_regulators = pfuze200_regulators;
		regulator_num = ARRAY_SIZE(pfuze200_regulators);
		sw_check_start = PFUZE200_SW2;
		sw_check_end = PFUZE200_SW3B;
		break;

	case PFUZE100:
	default:
		pfuze_regulators = pfuze100_regulators;
		regulator_num = ARRAY_SIZE(pfuze100_regulators);
		sw_check_start = PFUZE100_SW2;
		sw_check_end = PFUZE100_SW4;
		break;
	}
	dev_info(&client->dev, "pfuze%s found.\n",
		(pfuze_chip->chip_id == PFUZE100) ? "100" : "200");

	memcpy(pfuze_chip->regulator_descs, pfuze_regulators,
		sizeof(pfuze_chip->regulator_descs));

	ret = pfuze_parse_regulators_dt(pfuze_chip);
	if (ret)
		return ret;

	for (i = 0; i < regulator_num; i++) {
		struct regulator_init_data *init_data;
		struct regulator_desc *desc;
		int val;

		desc = &pfuze_chip->regulator_descs[i].desc;

		if (pdata)
			init_data = pdata->init_data[i];
		else
			init_data = match_init_data(i);

		/* SW2~SW4 high bit check and modify the voltage value table */
		if (i >= sw_check_start && i <= sw_check_end) {
			regmap_read(pfuze_chip->regmap, desc->vsel_reg, &val);
			if (val & 0x40) {
				desc->min_uV = 800000;
				desc->uV_step = 50000;
				desc->n_voltages = 51;
			}
		}

		config.dev = &client->dev;
		config.init_data = init_data;
		config.driver_data = pfuze_chip;
		config.of_node = match_of_node(i);

		pfuze_chip->regulators[i] =
			devm_regulator_register(&client->dev, desc, &config);
		if (IS_ERR(pfuze_chip->regulators[i])) {
			dev_err(&client->dev, "register regulator%s failed\n",
				pfuze_regulators[i].desc.name);
			return PTR_ERR(pfuze_chip->regulators[i]);
		}
	}

	return 0;
}

static struct i2c_driver pfuze_driver = {
	.id_table = pfuze_device_id,
	.driver = {
		.name = "pfuze100-regulator",
		.owner = THIS_MODULE,
		.of_match_table = pfuze_dt_ids,
	},
	.probe = pfuze100_regulator_probe,
};
module_i2c_driver(pfuze_driver);

MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100 PMIC");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("i2c:pfuze100-regulator");
Commit	Line	Data
3784b6d6 RG	1	/*
	2	* Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
	20	#include <linux/init.h>
	21	#include <linux/err.h>
	22	#include <linux/of.h>
	23	#include <linux/of_device.h>
	24	#include <linux/regulator/of_regulator.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/regulator/driver.h>
	27	#include <linux/regulator/machine.h>
	28	#include <linux/regulator/pfuze100.h>
	29	#include <linux/i2c.h>
	30	#include <linux/slab.h>
	31	#include <linux/regmap.h>
	32
	33	#define PFUZE_NUMREGS 128
	34	#define PFUZE100_VOL_OFFSET 0
	35	#define PFUZE100_STANDBY_OFFSET 1
	36	#define PFUZE100_MODE_OFFSET 3
	37	#define PFUZE100_CONF_OFFSET 4
	38
	39	#define PFUZE100_DEVICEID 0x0
	40	#define PFUZE100_REVID 0x3
a1b6fa85	41	#define PFUZE100_FABID 0x4
3784b6d6 RG	42
	43	#define PFUZE100_SW1ABVOL 0x20
	44	#define PFUZE100_SW1CVOL 0x2e
	45	#define PFUZE100_SW2VOL 0x35
	46	#define PFUZE100_SW3AVOL 0x3c
	47	#define PFUZE100_SW3BVOL 0x43
	48	#define PFUZE100_SW4VOL 0x4a
	49	#define PFUZE100_SWBSTCON1 0x66
	50	#define PFUZE100_VREFDDRCON 0x6a
	51	#define PFUZE100_VSNVSVOL 0x6b
	52	#define PFUZE100_VGEN1VOL 0x6c
	53	#define PFUZE100_VGEN2VOL 0x6d
	54	#define PFUZE100_VGEN3VOL 0x6e
	55	#define PFUZE100_VGEN4VOL 0x6f
	56	#define PFUZE100_VGEN5VOL 0x70
	57	#define PFUZE100_VGEN6VOL 0x71
	58
f2518480 RG	59	enum chips {PFUZE100, PFUZE200, PFUZE_NUM};
f2518480 RG	60
3784b6d6 RG	61	struct pfuze_regulator {
	62	struct regulator_desc desc;
	63	unsigned char stby_reg;
	64	unsigned char stby_mask;
	65	};
	66
	67	struct pfuze_chip {
f2518480	68	int chip_id;
3784b6d6 RG	69	struct regmap *regmap;
	70	struct device *dev;
	71	struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
	72	struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
	73	};
	74
	75	static const int pfuze100_swbst[] = {
	76	5000000, 5050000, 5100000, 5150000,
	77	};
	78
	79	static const int pfuze100_vsnvs[] = {
	80	1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
	81	};
	82
f2518480 RG	83	static const struct i2c_device_id pfuze_device_id[PFUZE_NUM] = {
	84	{.name = "pfuze100", .driver_data = PFUZE100},
	85	{.name = "pfuze200", .driver_data = PFUZE200},
3784b6d6 RG	86	};
	87	MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
	88
f2518480 RG	89	static const struct of_device_id pfuze_dt_ids[PFUZE_NUM] = {
	90	{ .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
	91	{ .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
3784b6d6 RG	92	};
	93	MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
	94
	95	static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
	96	{
	97	struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
	98	int id = rdev->desc->id;
e5656669	99	unsigned int ramp_bits;
3784b6d6 RG	100	int ret;
	101
	102	if (id < PFUZE100_SWBST) {
e5656669	103	ramp_delay = 12500 / ramp_delay;
3784b6d6	104	ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
e5656669 AL	105	ret = regmap_update_bits(pfuze100->regmap,
	106	rdev->desc->vsel_reg + 4,
	107	0xc0, ramp_bits << 6);
3784b6d6 RG	108	if (ret < 0)
	109	dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
	110	} else
	111	ret = -EACCES;
	112
	113	return ret;
	114	}
	115
	116	static struct regulator_ops pfuze100_ldo_regulator_ops = {
	117	.enable = regulator_enable_regmap,
	118	.disable = regulator_disable_regmap,
	119	.is_enabled = regulator_is_enabled_regmap,
	120	.list_voltage = regulator_list_voltage_linear,
	121	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	122	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	123	};
	124
	125	static struct regulator_ops pfuze100_fixed_regulator_ops = {
	126	.list_voltage = regulator_list_voltage_linear,
	127	};
	128
	129	static struct regulator_ops pfuze100_sw_regulator_ops = {
	130	.list_voltage = regulator_list_voltage_linear,
	131	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	132	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	133	.set_voltage_time_sel = regulator_set_voltage_time_sel,
	134	.set_ramp_delay = pfuze100_set_ramp_delay,
	135	};
	136
	137	static struct regulator_ops pfuze100_swb_regulator_ops = {
	138	.list_voltage = regulator_list_voltage_table,
2e04cc41	139	.map_voltage = regulator_map_voltage_ascend,
3784b6d6 RG	140	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	141	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	142
	143	};
	144
f2518480 RG	145	#define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
f2518480 RG	146	[_chip ## _ ## _name] = { \
3784b6d6 RG	147	.desc = { \
	148	.name = #_name, \
	149	.n_voltages = 1, \
	150	.ops = &pfuze100_fixed_regulator_ops, \
	151	.type = REGULATOR_VOLTAGE, \
f2518480	152	.id = _chip ## _ ## _name, \
3784b6d6 RG	153	.owner = THIS_MODULE, \
	154	.min_uV = (voltage), \
	155	.enable_reg = (base), \
	156	.enable_mask = 0x10, \
	157	}, \
	158	}
	159
f2518480 RG	160	#define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
f2518480 RG	161	[_chip ## _ ## _name] = { \
3784b6d6 RG	162	.desc = { \
	163	.name = #_name,\
	164	.n_voltages = ((max) - (min)) / (step) + 1, \
	165	.ops = &pfuze100_sw_regulator_ops, \
	166	.type = REGULATOR_VOLTAGE, \
f2518480	167	.id = _chip ## _ ## _name, \
3784b6d6 RG	168	.owner = THIS_MODULE, \
	169	.min_uV = (min), \
	170	.uV_step = (step), \
	171	.vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
	172	.vsel_mask = 0x3f, \
	173	}, \
	174	.stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
	175	.stby_mask = 0x3f, \
	176	}
	177
f2518480 RG	178	#define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
f2518480 RG	179	[_chip ## _ ## _name] = { \
3784b6d6 RG	180	.desc = { \
	181	.name = #_name, \
	182	.n_voltages = ARRAY_SIZE(voltages), \
	183	.ops = &pfuze100_swb_regulator_ops, \
	184	.type = REGULATOR_VOLTAGE, \
f2518480	185	.id = _chip ## _ ## _name, \
3784b6d6 RG	186	.owner = THIS_MODULE, \
	187	.volt_table = voltages, \
	188	.vsel_reg = (base), \
	189	.vsel_mask = (mask), \
	190	}, \
	191	}
	192
f2518480 RG	193	#define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
f2518480 RG	194	[_chip ## _ ## _name] = { \
3784b6d6 RG	195	.desc = { \
	196	.name = #_name, \
	197	.n_voltages = ((max) - (min)) / (step) + 1, \
	198	.ops = &pfuze100_ldo_regulator_ops, \
	199	.type = REGULATOR_VOLTAGE, \
f2518480	200	.id = _chip ## _ ## _name, \
3784b6d6 RG	201	.owner = THIS_MODULE, \
	202	.min_uV = (min), \
	203	.uV_step = (step), \
	204	.vsel_reg = (base), \
	205	.vsel_mask = 0xf, \
	206	.enable_reg = (base), \
	207	.enable_mask = 0x10, \
	208	}, \
	209	.stby_reg = (base), \
	210	.stby_mask = 0x20, \
	211	}
	212
f2518480	213	/* PFUZE100 */
3784b6d6	214	static struct pfuze_regulator pfuze100_regulators[] = {
f2518480 RG	215	PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
	216	PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
	217	PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
	218	PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
	219	PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
	220	PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
	221	PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
	222	PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
	223	PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
	224	PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
	225	PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
	226	PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
	227	PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
	228	PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
	229	PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
	230	};
	231
	232	static struct pfuze_regulator pfuze200_regulators[] = {
	233	PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
	234	PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
	235	PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
	236	PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
	237	PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
	238	PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
	239	PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
	240	PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
	241	PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
	242	PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
	243	PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
	244	PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
	245	PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
3784b6d6 RG	246	};
3784b6d6 RG	247
f2518480 RG	248	static struct pfuze_regulator *pfuze_regulators;
f2518480 RG	249
3784b6d6	250	#ifdef CONFIG_OF
f2518480	251	/* PFUZE100 */
3784b6d6 RG	252	static struct of_regulator_match pfuze100_matches[] = {
	253	{ .name = "sw1ab", },
	254	{ .name = "sw1c", },
	255	{ .name = "sw2", },
	256	{ .name = "sw3a", },
	257	{ .name = "sw3b", },
	258	{ .name = "sw4", },
	259	{ .name = "swbst", },
	260	{ .name = "vsnvs", },
	261	{ .name = "vrefddr", },
	262	{ .name = "vgen1", },
	263	{ .name = "vgen2", },
	264	{ .name = "vgen3", },
	265	{ .name = "vgen4", },
	266	{ .name = "vgen5", },
	267	{ .name = "vgen6", },
	268	};
	269
f2518480 RG	270	/* PFUZE200 */
	271	static struct of_regulator_match pfuze200_matches[] = {
	272
	273	{ .name = "sw1ab", },
	274	{ .name = "sw2", },
	275	{ .name = "sw3a", },
	276	{ .name = "sw3b", },
	277	{ .name = "swbst", },
	278	{ .name = "vsnvs", },
	279	{ .name = "vrefddr", },
	280	{ .name = "vgen1", },
	281	{ .name = "vgen2", },
	282	{ .name = "vgen3", },
	283	{ .name = "vgen4", },
	284	{ .name = "vgen5", },
	285	{ .name = "vgen6", },
	286	};
	287
	288	static struct of_regulator_match *pfuze_matches;
	289
3784b6d6 RG	290	static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
	291	{
	292	struct device *dev = chip->dev;
	293	struct device_node np, parent;
	294	int ret;
	295
3e01c75a	296	np = of_node_get(dev->of_node);
3784b6d6	297	if (!np)
6428789e	298	return -EINVAL;
3784b6d6	299
d7857c42	300	parent = of_get_child_by_name(np, "regulators");
3784b6d6 RG	301	if (!parent) {
	302	dev_err(dev, "regulators node not found\n");
	303	return -EINVAL;
	304	}
	305
f2518480 RG	306	switch (chip->chip_id) {
	307	case PFUZE200:
	308	pfuze_matches = pfuze200_matches;
	309	ret = of_regulator_match(dev, parent, pfuze200_matches,
	310	ARRAY_SIZE(pfuze200_matches));
	311	break;
	312
	313	case PFUZE100:
	314	default:
	315	pfuze_matches = pfuze100_matches;
	316	ret = of_regulator_match(dev, parent, pfuze100_matches,
	317	ARRAY_SIZE(pfuze100_matches));
	318	break;
	319	}
3784b6d6 RG	320
	321	of_node_put(parent);
	322	if (ret < 0) {
	323	dev_err(dev, "Error parsing regulator init data: %d\n",
	324	ret);
	325	return ret;
	326	}
	327
	328	return 0;
	329	}
	330
	331	static inline struct regulator_init_data *match_init_data(int index)
	332	{
f2518480	333	return pfuze_matches[index].init_data;
3784b6d6 RG	334	}
	335
	336	static inline struct device_node *match_of_node(int index)
	337	{
f2518480	338	return pfuze_matches[index].of_node;
3784b6d6 RG	339	}
	340	#else
	341	static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
	342	{
205c97bc	343	return 0;
3784b6d6 RG	344	}
	345
	346	static inline struct regulator_init_data *match_init_data(int index)
	347	{
	348	return NULL;
	349	}
	350
	351	static inline struct device_node *match_of_node(int index)
	352	{
	353	return NULL;
	354	}
	355	#endif
	356
	357	static int pfuze_identify(struct pfuze_chip *pfuze_chip)
	358	{
	359	unsigned int value;
	360	int ret;
	361
	362	ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
	363	if (ret)
	364	return ret;
	365
f2518480 RG	366	if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
	367	/*
	368	* Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
	369	* as ID=8 in PFUZE100
	370	*/
62b38916	371	dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
f2518480 RG	372	} else if ((value & 0x0f) != pfuze_chip->chip_id) {
f2518480 RG	373	/* device id NOT match with your setting */
3784b6d6 RG	374	dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
	375	return -ENODEV;
	376	}
	377
	378	ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
	379	if (ret)
	380	return ret;
	381	dev_info(pfuze_chip->dev,
f2694383	382	"Full layer: %x, Metal layer: %x\n",
3784b6d6 RG	383	(value & 0xf0) >> 4, value & 0x0f);
	384
	385	ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
	386	if (ret)
	387	return ret;
	388	dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
	389	(value & 0xc) >> 2, value & 0x3);
	390
	391	return 0;
	392	}
	393
	394	static const struct regmap_config pfuze_regmap_config = {
	395	.reg_bits = 8,
	396	.val_bits = 8,
6b8430c3	397	.max_register = PFUZE_NUMREGS - 1,
3784b6d6 RG	398	.cache_type = REGCACHE_RBTREE,
	399	};
	400
	401	static int pfuze100_regulator_probe(struct i2c_client *client,
	402	const struct i2c_device_id *id)
	403	{
	404	struct pfuze_chip *pfuze_chip;
	405	struct pfuze_regulator_platform_data *pdata =
	406	dev_get_platdata(&client->dev);
	407	struct regulator_config config = { };
	408	int i, ret;
f2518480 RG	409	const struct of_device_id *match;
	410	u32 regulator_num;
	411	u32 sw_check_start, sw_check_end;
3784b6d6 RG	412
	413	pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
	414	GFP_KERNEL);
	415	if (!pfuze_chip)
	416	return -ENOMEM;
	417
f2518480 RG	418	if (client->dev.of_node) {
	419	match = of_match_device(of_match_ptr(pfuze_dt_ids),
	420	&client->dev);
	421	if (!match) {
	422	dev_err(&client->dev, "Error: No device match found\n");
	423	return -ENODEV;
	424	}
	425	pfuze_chip->chip_id = (int)(long)match->data;
	426	} else if (id) {
	427	pfuze_chip->chip_id = id->driver_data;
	428	} else {
	429	dev_err(&client->dev, "No dts match or id table match found\n");
	430	return -ENODEV;
	431	}
3784b6d6	432
f2518480	433	i2c_set_clientdata(client, pfuze_chip);
3784b6d6 RG	434	pfuze_chip->dev = &client->dev;
	435
	436	pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
	437	if (IS_ERR(pfuze_chip->regmap)) {
	438	ret = PTR_ERR(pfuze_chip->regmap);
	439	dev_err(&client->dev,
	440	"regmap allocation failed with err %d\n", ret);
	441	return ret;
	442	}
	443
	444	ret = pfuze_identify(pfuze_chip);
	445	if (ret) {
	446	dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
	447	return ret;
	448	}
	449
f2518480 RG	450	/* use the right regulators after identify the right device */
	451	switch (pfuze_chip->chip_id) {
	452	case PFUZE200:
	453	pfuze_regulators = pfuze200_regulators;
	454	regulator_num = ARRAY_SIZE(pfuze200_regulators);
	455	sw_check_start = PFUZE200_SW2;
	456	sw_check_end = PFUZE200_SW3B;
	457	break;
	458
	459	case PFUZE100:
	460	default:
	461	pfuze_regulators = pfuze100_regulators;
	462	regulator_num = ARRAY_SIZE(pfuze100_regulators);
	463	sw_check_start = PFUZE100_SW2;
	464	sw_check_end = PFUZE100_SW4;
	465	break;
	466	}
	467	dev_info(&client->dev, "pfuze%s found.\n",
	468	(pfuze_chip->chip_id == PFUZE100) ? "100" : "200");
	469
	470	memcpy(pfuze_chip->regulator_descs, pfuze_regulators,
	471	sizeof(pfuze_chip->regulator_descs));
	472
3784b6d6 RG	473	ret = pfuze_parse_regulators_dt(pfuze_chip);
	474	if (ret)
	475	return ret;
	476
f2518480	477	for (i = 0; i < regulator_num; i++) {
3784b6d6	478	struct regulator_init_data *init_data;
d9493234	479	struct regulator_desc *desc;
3784b6d6 RG	480	int val;
3784b6d6 RG	481
d9493234 AL	482	desc = &pfuze_chip->regulator_descs[i].desc;
d9493234 AL	483
3784b6d6 RG	484	if (pdata)
	485	init_data = pdata->init_data[i];
	486	else
	487	init_data = match_init_data(i);
	488
	489	/* SW2~SW4 high bit check and modify the voltage value table */
f2518480	490	if (i >= sw_check_start && i <= sw_check_end) {
d9493234	491	regmap_read(pfuze_chip->regmap, desc->vsel_reg, &val);
3784b6d6	492	if (val & 0x40) {
d9493234 AL	493	desc->min_uV = 800000;
	494	desc->uV_step = 50000;
	495	desc->n_voltages = 51;
3784b6d6 RG	496	}
	497	}
	498
	499	config.dev = &client->dev;
	500	config.init_data = init_data;
	501	config.driver_data = pfuze_chip;
	502	config.of_node = match_of_node(i);
	503
f5247b40 JH	504	pfuze_chip->regulators[i] =
f5247b40 JH	505	devm_regulator_register(&client->dev, desc, &config);
3784b6d6 RG	506	if (IS_ERR(pfuze_chip->regulators[i])) {
3784b6d6 RG	507	dev_err(&client->dev, "register regulator%s failed\n",
f2518480	508	pfuze_regulators[i].desc.name);
f5247b40	509	return PTR_ERR(pfuze_chip->regulators[i]);
3784b6d6 RG	510	}
	511	}
	512
	513	return 0;
	514	}
	515
3784b6d6 RG	516	static struct i2c_driver pfuze_driver = {
	517	.id_table = pfuze_device_id,
	518	.driver = {
	519	.name = "pfuze100-regulator",
	520	.owner = THIS_MODULE,
	521	.of_match_table = pfuze_dt_ids,
	522	},
	523	.probe = pfuze100_regulator_probe,
3784b6d6 RG	524	};
	525	module_i2c_driver(pfuze_driver);
	526
	527	MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
	528	MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100 PMIC");
12d20fc2	529	MODULE_LICENSE("GPL v2");
40839bff	530	MODULE_ALIAS("i2c:pfuze100-regulator");