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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
e5ce4208 GG |
2 | /* |
3 | * Driver for Regulator part of Palmas PMIC Chips | |
4 | * | |
7be859f7 | 5 | * Copyright 2011-2013 Texas Instruments Inc. |
e5ce4208 GG |
6 | * |
7 | * Author: Graeme Gregory <gg@slimlogic.co.uk> | |
a7dddf27 | 8 | * Author: Ian Lartey <ian@slimlogic.co.uk> |
e5ce4208 GG |
9 | */ |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/regulator/driver.h> | |
17 | #include <linux/regulator/machine.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/regmap.h> | |
20 | #include <linux/mfd/palmas.h> | |
a361cd9f GG |
21 | #include <linux/of.h> |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/regulator/of_regulator.h> | |
e5ce4208 | 24 | |
dbabd624 | 25 | static const struct regulator_linear_range smps_low_ranges[] = { |
6b7f2d82 | 26 | REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0), |
dbabd624 K |
27 | REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0), |
28 | REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000), | |
29 | REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0), | |
30 | }; | |
31 | ||
32 | static const struct regulator_linear_range smps_high_ranges[] = { | |
6b7f2d82 | 33 | REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0), |
dbabd624 K |
34 | REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0), |
35 | REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000), | |
36 | REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0), | |
37 | }; | |
38 | ||
6839cd6f | 39 | static struct palmas_regs_info palmas_generic_regs_info[] = { |
e5ce4208 GG |
40 | { |
41 | .name = "SMPS12", | |
504382c9 | 42 | .sname = "smps1-in", |
e5ce4208 GG |
43 | .vsel_addr = PALMAS_SMPS12_VOLTAGE, |
44 | .ctrl_addr = PALMAS_SMPS12_CTRL, | |
45 | .tstep_addr = PALMAS_SMPS12_TSTEP, | |
32b6d3f6 | 46 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12, |
e5ce4208 GG |
47 | }, |
48 | { | |
49 | .name = "SMPS123", | |
504382c9 | 50 | .sname = "smps1-in", |
e5ce4208 GG |
51 | .vsel_addr = PALMAS_SMPS12_VOLTAGE, |
52 | .ctrl_addr = PALMAS_SMPS12_CTRL, | |
53 | .tstep_addr = PALMAS_SMPS12_TSTEP, | |
32b6d3f6 | 54 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12, |
e5ce4208 GG |
55 | }, |
56 | { | |
57 | .name = "SMPS3", | |
504382c9 | 58 | .sname = "smps3-in", |
e5ce4208 GG |
59 | .vsel_addr = PALMAS_SMPS3_VOLTAGE, |
60 | .ctrl_addr = PALMAS_SMPS3_CTRL, | |
32b6d3f6 | 61 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS3, |
e5ce4208 GG |
62 | }, |
63 | { | |
64 | .name = "SMPS45", | |
504382c9 | 65 | .sname = "smps4-in", |
e5ce4208 GG |
66 | .vsel_addr = PALMAS_SMPS45_VOLTAGE, |
67 | .ctrl_addr = PALMAS_SMPS45_CTRL, | |
68 | .tstep_addr = PALMAS_SMPS45_TSTEP, | |
32b6d3f6 | 69 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45, |
e5ce4208 GG |
70 | }, |
71 | { | |
72 | .name = "SMPS457", | |
504382c9 | 73 | .sname = "smps4-in", |
e5ce4208 GG |
74 | .vsel_addr = PALMAS_SMPS45_VOLTAGE, |
75 | .ctrl_addr = PALMAS_SMPS45_CTRL, | |
76 | .tstep_addr = PALMAS_SMPS45_TSTEP, | |
32b6d3f6 | 77 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45, |
e5ce4208 GG |
78 | }, |
79 | { | |
80 | .name = "SMPS6", | |
504382c9 | 81 | .sname = "smps6-in", |
e5ce4208 GG |
82 | .vsel_addr = PALMAS_SMPS6_VOLTAGE, |
83 | .ctrl_addr = PALMAS_SMPS6_CTRL, | |
84 | .tstep_addr = PALMAS_SMPS6_TSTEP, | |
32b6d3f6 | 85 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS6, |
e5ce4208 GG |
86 | }, |
87 | { | |
88 | .name = "SMPS7", | |
504382c9 | 89 | .sname = "smps7-in", |
e5ce4208 GG |
90 | .vsel_addr = PALMAS_SMPS7_VOLTAGE, |
91 | .ctrl_addr = PALMAS_SMPS7_CTRL, | |
32b6d3f6 | 92 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS7, |
e5ce4208 GG |
93 | }, |
94 | { | |
95 | .name = "SMPS8", | |
504382c9 | 96 | .sname = "smps8-in", |
e5ce4208 GG |
97 | .vsel_addr = PALMAS_SMPS8_VOLTAGE, |
98 | .ctrl_addr = PALMAS_SMPS8_CTRL, | |
99 | .tstep_addr = PALMAS_SMPS8_TSTEP, | |
32b6d3f6 | 100 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS8, |
e5ce4208 GG |
101 | }, |
102 | { | |
103 | .name = "SMPS9", | |
504382c9 | 104 | .sname = "smps9-in", |
e5ce4208 GG |
105 | .vsel_addr = PALMAS_SMPS9_VOLTAGE, |
106 | .ctrl_addr = PALMAS_SMPS9_CTRL, | |
32b6d3f6 | 107 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS9, |
e5ce4208 GG |
108 | }, |
109 | { | |
77409d9b | 110 | .name = "SMPS10_OUT2", |
504382c9 | 111 | .sname = "smps10-in", |
e31089c6 | 112 | .ctrl_addr = PALMAS_SMPS10_CTRL, |
32b6d3f6 | 113 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10, |
e5ce4208 | 114 | }, |
77409d9b KVA |
115 | { |
116 | .name = "SMPS10_OUT1", | |
117 | .sname = "smps10-out2", | |
118 | .ctrl_addr = PALMAS_SMPS10_CTRL, | |
32b6d3f6 | 119 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10, |
77409d9b | 120 | }, |
e5ce4208 GG |
121 | { |
122 | .name = "LDO1", | |
504382c9 | 123 | .sname = "ldo1-in", |
e5ce4208 GG |
124 | .vsel_addr = PALMAS_LDO1_VOLTAGE, |
125 | .ctrl_addr = PALMAS_LDO1_CTRL, | |
32b6d3f6 | 126 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO1, |
e5ce4208 GG |
127 | }, |
128 | { | |
129 | .name = "LDO2", | |
504382c9 | 130 | .sname = "ldo2-in", |
e5ce4208 GG |
131 | .vsel_addr = PALMAS_LDO2_VOLTAGE, |
132 | .ctrl_addr = PALMAS_LDO2_CTRL, | |
32b6d3f6 | 133 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO2, |
e5ce4208 GG |
134 | }, |
135 | { | |
136 | .name = "LDO3", | |
504382c9 | 137 | .sname = "ldo3-in", |
e5ce4208 GG |
138 | .vsel_addr = PALMAS_LDO3_VOLTAGE, |
139 | .ctrl_addr = PALMAS_LDO3_CTRL, | |
32b6d3f6 | 140 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO3, |
e5ce4208 GG |
141 | }, |
142 | { | |
143 | .name = "LDO4", | |
504382c9 | 144 | .sname = "ldo4-in", |
e5ce4208 GG |
145 | .vsel_addr = PALMAS_LDO4_VOLTAGE, |
146 | .ctrl_addr = PALMAS_LDO4_CTRL, | |
32b6d3f6 | 147 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO4, |
e5ce4208 GG |
148 | }, |
149 | { | |
150 | .name = "LDO5", | |
504382c9 | 151 | .sname = "ldo5-in", |
e5ce4208 GG |
152 | .vsel_addr = PALMAS_LDO5_VOLTAGE, |
153 | .ctrl_addr = PALMAS_LDO5_CTRL, | |
32b6d3f6 | 154 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO5, |
e5ce4208 GG |
155 | }, |
156 | { | |
157 | .name = "LDO6", | |
504382c9 | 158 | .sname = "ldo6-in", |
e5ce4208 GG |
159 | .vsel_addr = PALMAS_LDO6_VOLTAGE, |
160 | .ctrl_addr = PALMAS_LDO6_CTRL, | |
32b6d3f6 | 161 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO6, |
e5ce4208 GG |
162 | }, |
163 | { | |
164 | .name = "LDO7", | |
504382c9 | 165 | .sname = "ldo7-in", |
e5ce4208 GG |
166 | .vsel_addr = PALMAS_LDO7_VOLTAGE, |
167 | .ctrl_addr = PALMAS_LDO7_CTRL, | |
32b6d3f6 | 168 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO7, |
e5ce4208 GG |
169 | }, |
170 | { | |
171 | .name = "LDO8", | |
504382c9 | 172 | .sname = "ldo8-in", |
e5ce4208 GG |
173 | .vsel_addr = PALMAS_LDO8_VOLTAGE, |
174 | .ctrl_addr = PALMAS_LDO8_CTRL, | |
32b6d3f6 | 175 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO8, |
e5ce4208 GG |
176 | }, |
177 | { | |
178 | .name = "LDO9", | |
504382c9 | 179 | .sname = "ldo9-in", |
e5ce4208 GG |
180 | .vsel_addr = PALMAS_LDO9_VOLTAGE, |
181 | .ctrl_addr = PALMAS_LDO9_CTRL, | |
32b6d3f6 | 182 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO9, |
e5ce4208 GG |
183 | }, |
184 | { | |
185 | .name = "LDOLN", | |
504382c9 | 186 | .sname = "ldoln-in", |
e5ce4208 GG |
187 | .vsel_addr = PALMAS_LDOLN_VOLTAGE, |
188 | .ctrl_addr = PALMAS_LDOLN_CTRL, | |
32b6d3f6 | 189 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOLN, |
e5ce4208 GG |
190 | }, |
191 | { | |
192 | .name = "LDOUSB", | |
504382c9 | 193 | .sname = "ldousb-in", |
e5ce4208 GG |
194 | .vsel_addr = PALMAS_LDOUSB_VOLTAGE, |
195 | .ctrl_addr = PALMAS_LDOUSB_CTRL, | |
32b6d3f6 | 196 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOUSB, |
e5ce4208 | 197 | }, |
aa07f027 LD |
198 | { |
199 | .name = "REGEN1", | |
200 | .ctrl_addr = PALMAS_REGEN1_CTRL, | |
32b6d3f6 | 201 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN1, |
aa07f027 LD |
202 | }, |
203 | { | |
204 | .name = "REGEN2", | |
205 | .ctrl_addr = PALMAS_REGEN2_CTRL, | |
32b6d3f6 | 206 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN2, |
aa07f027 LD |
207 | }, |
208 | { | |
209 | .name = "REGEN3", | |
210 | .ctrl_addr = PALMAS_REGEN3_CTRL, | |
32b6d3f6 | 211 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN3, |
aa07f027 LD |
212 | }, |
213 | { | |
214 | .name = "SYSEN1", | |
215 | .ctrl_addr = PALMAS_SYSEN1_CTRL, | |
32b6d3f6 | 216 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN1, |
aa07f027 LD |
217 | }, |
218 | { | |
219 | .name = "SYSEN2", | |
220 | .ctrl_addr = PALMAS_SYSEN2_CTRL, | |
32b6d3f6 | 221 | .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN2, |
aa07f027 | 222 | }, |
e5ce4208 GG |
223 | }; |
224 | ||
e7cf34ef | 225 | static struct palmas_regs_info tps65917_regs_info[] = { |
d6f83370 K |
226 | { |
227 | .name = "SMPS1", | |
228 | .sname = "smps1-in", | |
229 | .vsel_addr = TPS65917_SMPS1_VOLTAGE, | |
230 | .ctrl_addr = TPS65917_SMPS1_CTRL, | |
231 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1, | |
232 | }, | |
233 | { | |
234 | .name = "SMPS2", | |
235 | .sname = "smps2-in", | |
236 | .vsel_addr = TPS65917_SMPS2_VOLTAGE, | |
237 | .ctrl_addr = TPS65917_SMPS2_CTRL, | |
238 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2, | |
239 | }, | |
240 | { | |
241 | .name = "SMPS3", | |
242 | .sname = "smps3-in", | |
243 | .vsel_addr = TPS65917_SMPS3_VOLTAGE, | |
244 | .ctrl_addr = TPS65917_SMPS3_CTRL, | |
245 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3, | |
246 | }, | |
247 | { | |
248 | .name = "SMPS4", | |
249 | .sname = "smps4-in", | |
250 | .vsel_addr = TPS65917_SMPS4_VOLTAGE, | |
251 | .ctrl_addr = TPS65917_SMPS4_CTRL, | |
252 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4, | |
253 | }, | |
254 | { | |
255 | .name = "SMPS5", | |
256 | .sname = "smps5-in", | |
257 | .vsel_addr = TPS65917_SMPS5_VOLTAGE, | |
258 | .ctrl_addr = TPS65917_SMPS5_CTRL, | |
259 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5, | |
260 | }, | |
be035303 K |
261 | { |
262 | .name = "SMPS12", | |
263 | .sname = "smps1-in", | |
264 | .vsel_addr = TPS65917_SMPS1_VOLTAGE, | |
265 | .ctrl_addr = TPS65917_SMPS1_CTRL, | |
266 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS12, | |
267 | }, | |
d6f83370 K |
268 | { |
269 | .name = "LDO1", | |
270 | .sname = "ldo1-in", | |
271 | .vsel_addr = TPS65917_LDO1_VOLTAGE, | |
272 | .ctrl_addr = TPS65917_LDO1_CTRL, | |
273 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1, | |
274 | }, | |
275 | { | |
276 | .name = "LDO2", | |
277 | .sname = "ldo2-in", | |
278 | .vsel_addr = TPS65917_LDO2_VOLTAGE, | |
279 | .ctrl_addr = TPS65917_LDO2_CTRL, | |
280 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2, | |
281 | }, | |
282 | { | |
283 | .name = "LDO3", | |
284 | .sname = "ldo3-in", | |
285 | .vsel_addr = TPS65917_LDO3_VOLTAGE, | |
286 | .ctrl_addr = TPS65917_LDO3_CTRL, | |
287 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3, | |
288 | }, | |
289 | { | |
290 | .name = "LDO4", | |
291 | .sname = "ldo4-in", | |
292 | .vsel_addr = TPS65917_LDO4_VOLTAGE, | |
293 | .ctrl_addr = TPS65917_LDO4_CTRL, | |
294 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4, | |
295 | }, | |
296 | { | |
297 | .name = "LDO5", | |
298 | .sname = "ldo5-in", | |
299 | .vsel_addr = TPS65917_LDO5_VOLTAGE, | |
300 | .ctrl_addr = TPS65917_LDO5_CTRL, | |
301 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5, | |
302 | }, | |
303 | { | |
304 | .name = "REGEN1", | |
305 | .ctrl_addr = TPS65917_REGEN1_CTRL, | |
306 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1, | |
307 | }, | |
308 | { | |
309 | .name = "REGEN2", | |
310 | .ctrl_addr = TPS65917_REGEN2_CTRL, | |
311 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2, | |
312 | }, | |
313 | { | |
314 | .name = "REGEN3", | |
315 | .ctrl_addr = TPS65917_REGEN3_CTRL, | |
316 | .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3, | |
317 | }, | |
318 | }; | |
319 | ||
cac9e916 K |
320 | #define EXTERNAL_REQUESTOR(_id, _offset, _pos) \ |
321 | [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \ | |
322 | .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \ | |
323 | .reg_offset = _offset, \ | |
324 | .bit_pos = _pos, \ | |
325 | } | |
326 | ||
4b09e17b | 327 | static struct palmas_sleep_requestor_info palma_sleep_req_info[] = { |
cac9e916 K |
328 | EXTERNAL_REQUESTOR(REGEN1, 0, 0), |
329 | EXTERNAL_REQUESTOR(REGEN2, 0, 1), | |
330 | EXTERNAL_REQUESTOR(SYSEN1, 0, 2), | |
331 | EXTERNAL_REQUESTOR(SYSEN2, 0, 3), | |
332 | EXTERNAL_REQUESTOR(CLK32KG, 0, 4), | |
333 | EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5), | |
334 | EXTERNAL_REQUESTOR(REGEN3, 0, 6), | |
335 | EXTERNAL_REQUESTOR(SMPS12, 1, 0), | |
336 | EXTERNAL_REQUESTOR(SMPS3, 1, 1), | |
337 | EXTERNAL_REQUESTOR(SMPS45, 1, 2), | |
338 | EXTERNAL_REQUESTOR(SMPS6, 1, 3), | |
339 | EXTERNAL_REQUESTOR(SMPS7, 1, 4), | |
340 | EXTERNAL_REQUESTOR(SMPS8, 1, 5), | |
341 | EXTERNAL_REQUESTOR(SMPS9, 1, 6), | |
342 | EXTERNAL_REQUESTOR(SMPS10, 1, 7), | |
343 | EXTERNAL_REQUESTOR(LDO1, 2, 0), | |
344 | EXTERNAL_REQUESTOR(LDO2, 2, 1), | |
345 | EXTERNAL_REQUESTOR(LDO3, 2, 2), | |
346 | EXTERNAL_REQUESTOR(LDO4, 2, 3), | |
347 | EXTERNAL_REQUESTOR(LDO5, 2, 4), | |
348 | EXTERNAL_REQUESTOR(LDO6, 2, 5), | |
349 | EXTERNAL_REQUESTOR(LDO7, 2, 6), | |
350 | EXTERNAL_REQUESTOR(LDO8, 2, 7), | |
351 | EXTERNAL_REQUESTOR(LDO9, 3, 0), | |
352 | EXTERNAL_REQUESTOR(LDOLN, 3, 1), | |
353 | EXTERNAL_REQUESTOR(LDOUSB, 3, 2), | |
354 | }; | |
355 | ||
d6f83370 K |
356 | #define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \ |
357 | [TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \ | |
358 | .id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \ | |
359 | .reg_offset = _offset, \ | |
360 | .bit_pos = _pos, \ | |
361 | } | |
362 | ||
363 | static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = { | |
364 | EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0), | |
365 | EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1), | |
366 | EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6), | |
367 | EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0), | |
368 | EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1), | |
369 | EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2), | |
370 | EXTERNAL_REQUESTOR_TPS65917(SMPS4, 1, 3), | |
371 | EXTERNAL_REQUESTOR_TPS65917(SMPS5, 1, 4), | |
be035303 | 372 | EXTERNAL_REQUESTOR_TPS65917(SMPS12, 1, 5), |
d6f83370 K |
373 | EXTERNAL_REQUESTOR_TPS65917(LDO1, 2, 0), |
374 | EXTERNAL_REQUESTOR_TPS65917(LDO2, 2, 1), | |
375 | EXTERNAL_REQUESTOR_TPS65917(LDO3, 2, 2), | |
376 | EXTERNAL_REQUESTOR_TPS65917(LDO4, 2, 3), | |
377 | EXTERNAL_REQUESTOR_TPS65917(LDO5, 2, 4), | |
378 | }; | |
379 | ||
ad542a52 | 380 | static const unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500}; |
28d1e8cd | 381 | |
e5ce4208 GG |
382 | #define SMPS_CTRL_MODE_OFF 0x00 |
383 | #define SMPS_CTRL_MODE_ON 0x01 | |
384 | #define SMPS_CTRL_MODE_ECO 0x02 | |
385 | #define SMPS_CTRL_MODE_PWM 0x03 | |
386 | ||
0f45aa84 | 387 | #define PALMAS_SMPS_NUM_VOLTAGES 122 |
e5ce4208 GG |
388 | #define PALMAS_SMPS10_NUM_VOLTAGES 2 |
389 | #define PALMAS_LDO_NUM_VOLTAGES 50 | |
390 | ||
391 | #define SMPS10_VSEL (1<<3) | |
392 | #define SMPS10_BOOST_EN (1<<2) | |
393 | #define SMPS10_BYPASS_EN (1<<1) | |
394 | #define SMPS10_SWITCH_EN (1<<0) | |
395 | ||
396 | #define REGULATOR_SLAVE 0 | |
397 | ||
398 | static int palmas_smps_read(struct palmas *palmas, unsigned int reg, | |
399 | unsigned int *dest) | |
400 | { | |
401 | unsigned int addr; | |
402 | ||
403 | addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg); | |
404 | ||
405 | return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest); | |
406 | } | |
407 | ||
408 | static int palmas_smps_write(struct palmas *palmas, unsigned int reg, | |
409 | unsigned int value) | |
410 | { | |
411 | unsigned int addr; | |
412 | ||
413 | addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg); | |
414 | ||
415 | return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value); | |
416 | } | |
417 | ||
418 | static int palmas_ldo_read(struct palmas *palmas, unsigned int reg, | |
419 | unsigned int *dest) | |
420 | { | |
421 | unsigned int addr; | |
422 | ||
423 | addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg); | |
424 | ||
425 | return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest); | |
426 | } | |
427 | ||
428 | static int palmas_ldo_write(struct palmas *palmas, unsigned int reg, | |
429 | unsigned int value) | |
430 | { | |
431 | unsigned int addr; | |
432 | ||
433 | addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg); | |
434 | ||
435 | return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value); | |
436 | } | |
437 | ||
e5ce4208 GG |
438 | static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode) |
439 | { | |
cf910b6b | 440 | int id = rdev_get_id(dev); |
966e927b | 441 | int ret; |
e5ce4208 | 442 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); |
cac9e916 | 443 | struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata; |
cf910b6b | 444 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
e5ce4208 | 445 | unsigned int reg; |
51d3a0c9 | 446 | bool rail_enable = true; |
e5ce4208 | 447 | |
966e927b KL |
448 | ret = palmas_smps_read(pmic->palmas, rinfo->ctrl_addr, ®); |
449 | if (ret) | |
450 | return ret; | |
cac9e916 | 451 | |
999f0c7c | 452 | reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
e5ce4208 | 453 | |
51d3a0c9 LD |
454 | if (reg == SMPS_CTRL_MODE_OFF) |
455 | rail_enable = false; | |
456 | ||
e5ce4208 GG |
457 | switch (mode) { |
458 | case REGULATOR_MODE_NORMAL: | |
459 | reg |= SMPS_CTRL_MODE_ON; | |
460 | break; | |
461 | case REGULATOR_MODE_IDLE: | |
462 | reg |= SMPS_CTRL_MODE_ECO; | |
463 | break; | |
464 | case REGULATOR_MODE_FAST: | |
465 | reg |= SMPS_CTRL_MODE_PWM; | |
466 | break; | |
467 | default: | |
468 | return -EINVAL; | |
469 | } | |
e5ce4208 | 470 | |
51d3a0c9 LD |
471 | pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
472 | if (rail_enable) | |
cf910b6b | 473 | palmas_smps_write(pmic->palmas, rinfo->ctrl_addr, reg); |
318dbb02 NM |
474 | |
475 | /* Switch the enable value to ensure this is used for enable */ | |
476 | pmic->desc[id].enable_val = pmic->current_reg_mode[id]; | |
477 | ||
e5ce4208 GG |
478 | return 0; |
479 | } | |
480 | ||
481 | static unsigned int palmas_get_mode_smps(struct regulator_dev *dev) | |
482 | { | |
483 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); | |
484 | int id = rdev_get_id(dev); | |
485 | unsigned int reg; | |
486 | ||
51d3a0c9 | 487 | reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; |
e5ce4208 GG |
488 | |
489 | switch (reg) { | |
490 | case SMPS_CTRL_MODE_ON: | |
491 | return REGULATOR_MODE_NORMAL; | |
492 | case SMPS_CTRL_MODE_ECO: | |
493 | return REGULATOR_MODE_IDLE; | |
494 | case SMPS_CTRL_MODE_PWM: | |
495 | return REGULATOR_MODE_FAST; | |
496 | } | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
28d1e8cd LD |
501 | static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev, |
502 | int ramp_delay) | |
503 | { | |
cf910b6b | 504 | int id = rdev_get_id(rdev); |
28d1e8cd | 505 | struct palmas_pmic *pmic = rdev_get_drvdata(rdev); |
cac9e916 | 506 | struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata; |
cf910b6b | 507 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
28d1e8cd | 508 | unsigned int reg = 0; |
28d1e8cd LD |
509 | int ret; |
510 | ||
f22c2bae AL |
511 | /* SMPS3 and SMPS7 do not have tstep_addr setting */ |
512 | switch (id) { | |
513 | case PALMAS_REG_SMPS3: | |
514 | case PALMAS_REG_SMPS7: | |
515 | return 0; | |
516 | } | |
517 | ||
28d1e8cd LD |
518 | if (ramp_delay <= 0) |
519 | reg = 0; | |
0ea34b57 | 520 | else if (ramp_delay <= 2500) |
28d1e8cd | 521 | reg = 3; |
0ea34b57 | 522 | else if (ramp_delay <= 5000) |
28d1e8cd LD |
523 | reg = 2; |
524 | else | |
525 | reg = 1; | |
526 | ||
cf910b6b | 527 | ret = palmas_smps_write(pmic->palmas, rinfo->tstep_addr, reg); |
28d1e8cd LD |
528 | if (ret < 0) { |
529 | dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret); | |
530 | return ret; | |
531 | } | |
532 | ||
533 | pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg]; | |
534 | return ret; | |
535 | } | |
536 | ||
0e5a7680 | 537 | static const struct regulator_ops palmas_ops_smps = { |
dbabd624 K |
538 | .is_enabled = regulator_is_enabled_regmap, |
539 | .enable = regulator_enable_regmap, | |
540 | .disable = regulator_disable_regmap, | |
e5ce4208 GG |
541 | .set_mode = palmas_set_mode_smps, |
542 | .get_mode = palmas_get_mode_smps, | |
bdc4baac AL |
543 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
544 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
dbabd624 K |
545 | .list_voltage = regulator_list_voltage_linear_range, |
546 | .map_voltage = regulator_map_voltage_linear_range, | |
547 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
28d1e8cd | 548 | .set_ramp_delay = palmas_smps_set_ramp_delay, |
e5ce4208 GG |
549 | }; |
550 | ||
0e5a7680 | 551 | static const struct regulator_ops palmas_ops_ext_control_smps = { |
32b6d3f6 LD |
552 | .set_mode = palmas_set_mode_smps, |
553 | .get_mode = palmas_get_mode_smps, | |
554 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
555 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
dbabd624 K |
556 | .list_voltage = regulator_list_voltage_linear_range, |
557 | .map_voltage = regulator_map_voltage_linear_range, | |
558 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
32b6d3f6 LD |
559 | .set_ramp_delay = palmas_smps_set_ramp_delay, |
560 | }; | |
561 | ||
0e5a7680 | 562 | static const struct regulator_ops palmas_ops_smps10 = { |
e5ce4208 GG |
563 | .is_enabled = regulator_is_enabled_regmap, |
564 | .enable = regulator_enable_regmap, | |
565 | .disable = regulator_disable_regmap, | |
566 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
567 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
8029a006 AL |
568 | .list_voltage = regulator_list_voltage_linear, |
569 | .map_voltage = regulator_map_voltage_linear, | |
77409d9b KVA |
570 | .set_bypass = regulator_set_bypass_regmap, |
571 | .get_bypass = regulator_get_bypass_regmap, | |
e5ce4208 GG |
572 | }; |
573 | ||
0e5a7680 | 574 | static const struct regulator_ops tps65917_ops_smps = { |
d6f83370 K |
575 | .is_enabled = regulator_is_enabled_regmap, |
576 | .enable = regulator_enable_regmap, | |
577 | .disable = regulator_disable_regmap, | |
578 | .set_mode = palmas_set_mode_smps, | |
579 | .get_mode = palmas_get_mode_smps, | |
580 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
581 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
582 | .list_voltage = regulator_list_voltage_linear_range, | |
583 | .map_voltage = regulator_map_voltage_linear_range, | |
584 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
585 | }; | |
586 | ||
0e5a7680 | 587 | static const struct regulator_ops tps65917_ops_ext_control_smps = { |
d6f83370 K |
588 | .set_mode = palmas_set_mode_smps, |
589 | .get_mode = palmas_get_mode_smps, | |
590 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
591 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
592 | .list_voltage = regulator_list_voltage_linear_range, | |
593 | .map_voltage = regulator_map_voltage_linear_range, | |
594 | }; | |
595 | ||
e5ce4208 GG |
596 | static int palmas_is_enabled_ldo(struct regulator_dev *dev) |
597 | { | |
cf910b6b | 598 | int id = rdev_get_id(dev); |
e5ce4208 | 599 | struct palmas_pmic *pmic = rdev_get_drvdata(dev); |
cac9e916 | 600 | struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata; |
cf910b6b | 601 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
e5ce4208 GG |
602 | unsigned int reg; |
603 | ||
cf910b6b | 604 | palmas_ldo_read(pmic->palmas, rinfo->ctrl_addr, ®); |
e5ce4208 GG |
605 | |
606 | reg &= PALMAS_LDO1_CTRL_STATUS; | |
607 | ||
608 | return !!(reg); | |
609 | } | |
610 | ||
0e5a7680 | 611 | static const struct regulator_ops palmas_ops_ldo = { |
e5ce4208 GG |
612 | .is_enabled = palmas_is_enabled_ldo, |
613 | .enable = regulator_enable_regmap, | |
614 | .disable = regulator_disable_regmap, | |
4a247a96 AL |
615 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
616 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
9119ff6a AL |
617 | .list_voltage = regulator_list_voltage_linear, |
618 | .map_voltage = regulator_map_voltage_linear, | |
e5ce4208 GG |
619 | }; |
620 | ||
0e5a7680 | 621 | static const struct regulator_ops palmas_ops_ldo9 = { |
b554e145 K |
622 | .is_enabled = palmas_is_enabled_ldo, |
623 | .enable = regulator_enable_regmap, | |
624 | .disable = regulator_disable_regmap, | |
625 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
626 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
627 | .list_voltage = regulator_list_voltage_linear, | |
628 | .map_voltage = regulator_map_voltage_linear, | |
629 | .set_bypass = regulator_set_bypass_regmap, | |
630 | .get_bypass = regulator_get_bypass_regmap, | |
631 | }; | |
632 | ||
0e5a7680 | 633 | static const struct regulator_ops palmas_ops_ext_control_ldo = { |
32b6d3f6 LD |
634 | .get_voltage_sel = regulator_get_voltage_sel_regmap, |
635 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
636 | .list_voltage = regulator_list_voltage_linear, | |
637 | .map_voltage = regulator_map_voltage_linear, | |
638 | }; | |
639 | ||
0e5a7680 | 640 | static const struct regulator_ops palmas_ops_extreg = { |
aa07f027 LD |
641 | .is_enabled = regulator_is_enabled_regmap, |
642 | .enable = regulator_enable_regmap, | |
643 | .disable = regulator_disable_regmap, | |
644 | }; | |
645 | ||
0e5a7680 | 646 | static const struct regulator_ops palmas_ops_ext_control_extreg = { |
32b6d3f6 LD |
647 | }; |
648 | ||
0e5a7680 | 649 | static const struct regulator_ops tps65917_ops_ldo = { |
d6f83370 K |
650 | .is_enabled = palmas_is_enabled_ldo, |
651 | .enable = regulator_enable_regmap, | |
652 | .disable = regulator_disable_regmap, | |
653 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
654 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
655 | .list_voltage = regulator_list_voltage_linear, | |
656 | .map_voltage = regulator_map_voltage_linear, | |
657 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
658 | }; | |
659 | ||
0e5a7680 | 660 | static const struct regulator_ops tps65917_ops_ldo_1_2 = { |
b554e145 K |
661 | .is_enabled = palmas_is_enabled_ldo, |
662 | .enable = regulator_enable_regmap, | |
663 | .disable = regulator_disable_regmap, | |
664 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
665 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
666 | .list_voltage = regulator_list_voltage_linear, | |
667 | .map_voltage = regulator_map_voltage_linear, | |
668 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
669 | .set_bypass = regulator_set_bypass_regmap, | |
670 | .get_bypass = regulator_get_bypass_regmap, | |
671 | }; | |
672 | ||
32b6d3f6 LD |
673 | static int palmas_regulator_config_external(struct palmas *palmas, int id, |
674 | struct palmas_reg_init *reg_init) | |
675 | { | |
cf910b6b NM |
676 | struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
677 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; | |
32b6d3f6 LD |
678 | int ret; |
679 | ||
cf910b6b NM |
680 | ret = palmas_ext_control_req_config(palmas, rinfo->sleep_id, |
681 | reg_init->roof_floor, true); | |
32b6d3f6 LD |
682 | if (ret < 0) |
683 | dev_err(palmas->dev, | |
684 | "Ext control config for regulator %d failed %d\n", | |
685 | id, ret); | |
686 | return ret; | |
687 | } | |
688 | ||
e5ce4208 GG |
689 | /* |
690 | * setup the hardware based sleep configuration of the SMPS/LDO regulators | |
691 | * from the platform data. This is different to the software based control | |
692 | * supported by the regulator framework as it is controlled by toggling | |
693 | * pins on the PMIC such as PREQ, SYSEN, ... | |
694 | */ | |
695 | static int palmas_smps_init(struct palmas *palmas, int id, | |
696 | struct palmas_reg_init *reg_init) | |
697 | { | |
698 | unsigned int reg; | |
e5ce4208 | 699 | int ret; |
cac9e916 | 700 | struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
cf910b6b NM |
701 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
702 | unsigned int addr = rinfo->ctrl_addr; | |
e5ce4208 GG |
703 | |
704 | ret = palmas_smps_read(palmas, addr, ®); | |
705 | if (ret) | |
706 | return ret; | |
707 | ||
fedd89b1 | 708 | switch (id) { |
77409d9b KVA |
709 | case PALMAS_REG_SMPS10_OUT1: |
710 | case PALMAS_REG_SMPS10_OUT2: | |
30590d04 LD |
711 | reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK; |
712 | if (reg_init->mode_sleep) | |
fedd89b1 AL |
713 | reg |= reg_init->mode_sleep << |
714 | PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT; | |
fedd89b1 AL |
715 | break; |
716 | default: | |
e5ce4208 GG |
717 | if (reg_init->warm_reset) |
718 | reg |= PALMAS_SMPS12_CTRL_WR_S; | |
30590d04 LD |
719 | else |
720 | reg &= ~PALMAS_SMPS12_CTRL_WR_S; | |
e5ce4208 GG |
721 | |
722 | if (reg_init->roof_floor) | |
723 | reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; | |
30590d04 LD |
724 | else |
725 | reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN; | |
e5ce4208 | 726 | |
30590d04 LD |
727 | reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK; |
728 | if (reg_init->mode_sleep) | |
e5ce4208 GG |
729 | reg |= reg_init->mode_sleep << |
730 | PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT; | |
e5ce4208 | 731 | } |
fedd89b1 | 732 | |
e5ce4208 GG |
733 | ret = palmas_smps_write(palmas, addr, reg); |
734 | if (ret) | |
735 | return ret; | |
736 | ||
cf910b6b | 737 | if (rinfo->vsel_addr && reg_init->vsel) { |
e5ce4208 GG |
738 | |
739 | reg = reg_init->vsel; | |
740 | ||
cf910b6b | 741 | ret = palmas_smps_write(palmas, rinfo->vsel_addr, reg); |
e5ce4208 GG |
742 | if (ret) |
743 | return ret; | |
744 | } | |
745 | ||
32b6d3f6 LD |
746 | if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) && |
747 | (id != PALMAS_REG_SMPS10_OUT2)) { | |
748 | /* Enable externally controlled regulator */ | |
32b6d3f6 LD |
749 | ret = palmas_smps_read(palmas, addr, ®); |
750 | if (ret < 0) | |
751 | return ret; | |
e5ce4208 | 752 | |
32b6d3f6 LD |
753 | if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) { |
754 | reg |= SMPS_CTRL_MODE_ON; | |
755 | ret = palmas_smps_write(palmas, addr, reg); | |
756 | if (ret < 0) | |
757 | return ret; | |
758 | } | |
759 | return palmas_regulator_config_external(palmas, id, reg_init); | |
760 | } | |
e5ce4208 GG |
761 | return 0; |
762 | } | |
763 | ||
764 | static int palmas_ldo_init(struct palmas *palmas, int id, | |
765 | struct palmas_reg_init *reg_init) | |
766 | { | |
767 | unsigned int reg; | |
768 | unsigned int addr; | |
769 | int ret; | |
cac9e916 | 770 | struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
cf910b6b | 771 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
cac9e916 | 772 | |
cf910b6b | 773 | addr = rinfo->ctrl_addr; |
e5ce4208 | 774 | |
2735daeb | 775 | ret = palmas_ldo_read(palmas, addr, ®); |
e5ce4208 GG |
776 | if (ret) |
777 | return ret; | |
778 | ||
779 | if (reg_init->warm_reset) | |
780 | reg |= PALMAS_LDO1_CTRL_WR_S; | |
30590d04 LD |
781 | else |
782 | reg &= ~PALMAS_LDO1_CTRL_WR_S; | |
e5ce4208 GG |
783 | |
784 | if (reg_init->mode_sleep) | |
785 | reg |= PALMAS_LDO1_CTRL_MODE_SLEEP; | |
30590d04 LD |
786 | else |
787 | reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP; | |
e5ce4208 | 788 | |
2735daeb | 789 | ret = palmas_ldo_write(palmas, addr, reg); |
e5ce4208 GG |
790 | if (ret) |
791 | return ret; | |
792 | ||
32b6d3f6 LD |
793 | if (reg_init->roof_floor) { |
794 | /* Enable externally controlled regulator */ | |
32b6d3f6 LD |
795 | ret = palmas_update_bits(palmas, PALMAS_LDO_BASE, |
796 | addr, PALMAS_LDO1_CTRL_MODE_ACTIVE, | |
797 | PALMAS_LDO1_CTRL_MODE_ACTIVE); | |
798 | if (ret < 0) { | |
799 | dev_err(palmas->dev, | |
800 | "LDO Register 0x%02x update failed %d\n", | |
801 | addr, ret); | |
802 | return ret; | |
803 | } | |
804 | return palmas_regulator_config_external(palmas, id, reg_init); | |
805 | } | |
e5ce4208 GG |
806 | return 0; |
807 | } | |
808 | ||
aa07f027 LD |
809 | static int palmas_extreg_init(struct palmas *palmas, int id, |
810 | struct palmas_reg_init *reg_init) | |
811 | { | |
812 | unsigned int addr; | |
813 | int ret; | |
814 | unsigned int val = 0; | |
cac9e916 | 815 | struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
cf910b6b | 816 | struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id]; |
cac9e916 | 817 | |
cf910b6b | 818 | addr = rinfo->ctrl_addr; |
aa07f027 LD |
819 | |
820 | if (reg_init->mode_sleep) | |
821 | val = PALMAS_REGEN1_CTRL_MODE_SLEEP; | |
822 | ||
823 | ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, | |
824 | addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val); | |
825 | if (ret < 0) { | |
826 | dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n", | |
827 | addr, ret); | |
828 | return ret; | |
829 | } | |
32b6d3f6 LD |
830 | |
831 | if (reg_init->roof_floor) { | |
832 | /* Enable externally controlled regulator */ | |
32b6d3f6 LD |
833 | ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE, |
834 | addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE, | |
835 | PALMAS_REGEN1_CTRL_MODE_ACTIVE); | |
836 | if (ret < 0) { | |
837 | dev_err(palmas->dev, | |
838 | "Resource Register 0x%02x update failed %d\n", | |
839 | addr, ret); | |
840 | return ret; | |
841 | } | |
842 | return palmas_regulator_config_external(palmas, id, reg_init); | |
843 | } | |
aa07f027 LD |
844 | return 0; |
845 | } | |
846 | ||
17c11a76 LD |
847 | static void palmas_enable_ldo8_track(struct palmas *palmas) |
848 | { | |
849 | unsigned int reg; | |
850 | unsigned int addr; | |
851 | int ret; | |
cac9e916 | 852 | struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata; |
cf910b6b | 853 | struct palmas_regs_info *rinfo; |
cac9e916 | 854 | |
cf910b6b NM |
855 | rinfo = &ddata->palmas_regs_info[PALMAS_REG_LDO8]; |
856 | addr = rinfo->ctrl_addr; | |
17c11a76 LD |
857 | |
858 | ret = palmas_ldo_read(palmas, addr, ®); | |
859 | if (ret) { | |
860 | dev_err(palmas->dev, "Error in reading ldo8 control reg\n"); | |
861 | return; | |
862 | } | |
863 | ||
864 | reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN; | |
865 | ret = palmas_ldo_write(palmas, addr, reg); | |
866 | if (ret < 0) { | |
867 | dev_err(palmas->dev, "Error in enabling tracking mode\n"); | |
868 | return; | |
869 | } | |
870 | /* | |
871 | * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8 | |
872 | * output is defined by the LDO8_VOLTAGE.VSEL register divided by two, | |
873 | * and can be set from 0.45 to 1.65 V. | |
874 | */ | |
cf910b6b | 875 | addr = rinfo->vsel_addr; |
17c11a76 LD |
876 | ret = palmas_ldo_read(palmas, addr, ®); |
877 | if (ret) { | |
878 | dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n"); | |
879 | return; | |
880 | } | |
881 | ||
882 | reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK; | |
883 | ret = palmas_ldo_write(palmas, addr, reg); | |
884 | if (ret < 0) | |
885 | dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n"); | |
886 | ||
887 | return; | |
888 | } | |
889 | ||
cac9e916 K |
890 | static int palmas_ldo_registration(struct palmas_pmic *pmic, |
891 | struct palmas_pmic_driver_data *ddata, | |
892 | struct palmas_pmic_platform_data *pdata, | |
893 | const char *pdev_name, | |
894 | struct regulator_config config) | |
a361cd9f | 895 | { |
cac9e916 K |
896 | int id, ret; |
897 | struct regulator_dev *rdev; | |
898 | struct palmas_reg_init *reg_init; | |
cf910b6b | 899 | struct palmas_regs_info *rinfo; |
429222d0 | 900 | struct regulator_desc *desc; |
a361cd9f | 901 | |
cac9e916 K |
902 | for (id = ddata->ldo_begin; id < ddata->max_reg; id++) { |
903 | if (pdata && pdata->reg_init[id]) | |
904 | reg_init = pdata->reg_init[id]; | |
905 | else | |
906 | reg_init = NULL; | |
a361cd9f | 907 | |
cf910b6b | 908 | rinfo = &ddata->palmas_regs_info[id]; |
cac9e916 K |
909 | /* Miss out regulators which are not available due |
910 | * to alternate functions. | |
911 | */ | |
a361cd9f | 912 | |
cac9e916 | 913 | /* Register the regulators */ |
429222d0 NM |
914 | desc = &pmic->desc[id]; |
915 | desc->name = rinfo->name; | |
916 | desc->id = id; | |
917 | desc->type = REGULATOR_VOLTAGE; | |
918 | desc->owner = THIS_MODULE; | |
a361cd9f | 919 | |
cac9e916 | 920 | if (id < PALMAS_REG_REGEN1) { |
429222d0 | 921 | desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES; |
cac9e916 | 922 | if (reg_init && reg_init->roof_floor) |
429222d0 | 923 | desc->ops = &palmas_ops_ext_control_ldo; |
cac9e916 | 924 | else |
429222d0 NM |
925 | desc->ops = &palmas_ops_ldo; |
926 | desc->min_uV = 900000; | |
927 | desc->uV_step = 50000; | |
928 | desc->linear_min_sel = 1; | |
929 | desc->enable_time = 500; | |
930 | desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, | |
931 | rinfo->vsel_addr); | |
932 | desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK; | |
933 | desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, | |
934 | rinfo->ctrl_addr); | |
935 | desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE; | |
a361cd9f | 936 | |
cac9e916 K |
937 | /* Check if LDO8 is in tracking mode or not */ |
938 | if (pdata && (id == PALMAS_REG_LDO8) && | |
939 | pdata->enable_ldo8_tracking) { | |
940 | palmas_enable_ldo8_track(pmic->palmas); | |
429222d0 NM |
941 | desc->min_uV = 450000; |
942 | desc->uV_step = 25000; | |
cac9e916 | 943 | } |
a361cd9f | 944 | |
cac9e916 K |
945 | /* LOD6 in vibrator mode will have enable time 2000us */ |
946 | if (pdata && pdata->ldo6_vibrator && | |
947 | (id == PALMAS_REG_LDO6)) | |
429222d0 | 948 | desc->enable_time = 2000; |
b554e145 K |
949 | |
950 | if (id == PALMAS_REG_LDO9) { | |
951 | desc->ops = &palmas_ops_ldo9; | |
952 | desc->bypass_reg = desc->enable_reg; | |
e0341f17 NM |
953 | desc->bypass_val_on = |
954 | PALMAS_LDO9_CTRL_LDO_BYPASS_EN; | |
b554e145 K |
955 | desc->bypass_mask = |
956 | PALMAS_LDO9_CTRL_LDO_BYPASS_EN; | |
957 | } | |
cac9e916 | 958 | } else { |
e999c728 K |
959 | if (!ddata->has_regen3 && id == PALMAS_REG_REGEN3) |
960 | continue; | |
961 | ||
429222d0 | 962 | desc->n_voltages = 1; |
cac9e916 | 963 | if (reg_init && reg_init->roof_floor) |
429222d0 | 964 | desc->ops = &palmas_ops_ext_control_extreg; |
cac9e916 | 965 | else |
429222d0 NM |
966 | desc->ops = &palmas_ops_extreg; |
967 | desc->enable_reg = | |
cac9e916 | 968 | PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, |
cf910b6b | 969 | rinfo->ctrl_addr); |
429222d0 | 970 | desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE; |
cac9e916 | 971 | } |
a361cd9f | 972 | |
cac9e916 K |
973 | if (pdata) |
974 | config.init_data = pdata->reg_data[id]; | |
975 | else | |
976 | config.init_data = NULL; | |
32b6d3f6 | 977 | |
429222d0 | 978 | desc->supply_name = rinfo->sname; |
cac9e916 | 979 | config.of_node = ddata->palmas_matches[id].of_node; |
a361cd9f | 980 | |
429222d0 | 981 | rdev = devm_regulator_register(pmic->dev, desc, &config); |
cac9e916 K |
982 | if (IS_ERR(rdev)) { |
983 | dev_err(pmic->dev, | |
984 | "failed to register %s regulator\n", | |
985 | pdev_name); | |
986 | return PTR_ERR(rdev); | |
987 | } | |
a361cd9f | 988 | |
cac9e916 K |
989 | /* Initialise sleep/init values from platform data */ |
990 | if (pdata) { | |
991 | reg_init = pdata->reg_init[id]; | |
992 | if (reg_init) { | |
993 | if (id <= ddata->ldo_end) | |
994 | ret = palmas_ldo_init(pmic->palmas, id, | |
995 | reg_init); | |
996 | else | |
997 | ret = palmas_extreg_init(pmic->palmas, | |
998 | id, reg_init); | |
999 | if (ret) | |
1000 | return ret; | |
1001 | } | |
1002 | } | |
a361cd9f GG |
1003 | } |
1004 | ||
cac9e916 | 1005 | return 0; |
a361cd9f GG |
1006 | } |
1007 | ||
d6f83370 K |
1008 | static int tps65917_ldo_registration(struct palmas_pmic *pmic, |
1009 | struct palmas_pmic_driver_data *ddata, | |
1010 | struct palmas_pmic_platform_data *pdata, | |
1011 | const char *pdev_name, | |
1012 | struct regulator_config config) | |
1013 | { | |
1014 | int id, ret; | |
1015 | struct regulator_dev *rdev; | |
1016 | struct palmas_reg_init *reg_init; | |
cf910b6b | 1017 | struct palmas_regs_info *rinfo; |
429222d0 | 1018 | struct regulator_desc *desc; |
d6f83370 K |
1019 | |
1020 | for (id = ddata->ldo_begin; id < ddata->max_reg; id++) { | |
1021 | if (pdata && pdata->reg_init[id]) | |
1022 | reg_init = pdata->reg_init[id]; | |
1023 | else | |
1024 | reg_init = NULL; | |
1025 | ||
1026 | /* Miss out regulators which are not available due | |
1027 | * to alternate functions. | |
1028 | */ | |
cf910b6b | 1029 | rinfo = &ddata->palmas_regs_info[id]; |
d6f83370 K |
1030 | |
1031 | /* Register the regulators */ | |
429222d0 NM |
1032 | desc = &pmic->desc[id]; |
1033 | desc->name = rinfo->name; | |
1034 | desc->id = id; | |
1035 | desc->type = REGULATOR_VOLTAGE; | |
1036 | desc->owner = THIS_MODULE; | |
d6f83370 K |
1037 | |
1038 | if (id < TPS65917_REG_REGEN1) { | |
429222d0 | 1039 | desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES; |
d6f83370 | 1040 | if (reg_init && reg_init->roof_floor) |
429222d0 | 1041 | desc->ops = &palmas_ops_ext_control_ldo; |
d6f83370 | 1042 | else |
429222d0 NM |
1043 | desc->ops = &tps65917_ops_ldo; |
1044 | desc->min_uV = 900000; | |
1045 | desc->uV_step = 50000; | |
1046 | desc->linear_min_sel = 1; | |
1047 | desc->enable_time = 500; | |
1048 | desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, | |
1049 | rinfo->vsel_addr); | |
1050 | desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK; | |
1051 | desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, | |
1052 | rinfo->ctrl_addr); | |
1053 | desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE; | |
d6f83370 K |
1054 | /* |
1055 | * To be confirmed. Discussion on going with PMIC Team. | |
1056 | * It is of the order of ~60mV/uS. | |
1057 | */ | |
429222d0 | 1058 | desc->ramp_delay = 2500; |
b554e145 K |
1059 | if (id == TPS65917_REG_LDO1 || |
1060 | id == TPS65917_REG_LDO2) { | |
1061 | desc->ops = &tps65917_ops_ldo_1_2; | |
1062 | desc->bypass_reg = desc->enable_reg; | |
e0341f17 NM |
1063 | desc->bypass_val_on = |
1064 | TPS65917_LDO1_CTRL_BYPASS_EN; | |
b554e145 K |
1065 | desc->bypass_mask = |
1066 | TPS65917_LDO1_CTRL_BYPASS_EN; | |
1067 | } | |
d6f83370 | 1068 | } else { |
429222d0 | 1069 | desc->n_voltages = 1; |
d6f83370 | 1070 | if (reg_init && reg_init->roof_floor) |
429222d0 | 1071 | desc->ops = &palmas_ops_ext_control_extreg; |
d6f83370 | 1072 | else |
429222d0 NM |
1073 | desc->ops = &palmas_ops_extreg; |
1074 | desc->enable_reg = | |
d6f83370 | 1075 | PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, |
cf910b6b | 1076 | rinfo->ctrl_addr); |
429222d0 | 1077 | desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE; |
d6f83370 K |
1078 | } |
1079 | ||
1080 | if (pdata) | |
1081 | config.init_data = pdata->reg_data[id]; | |
1082 | else | |
1083 | config.init_data = NULL; | |
1084 | ||
429222d0 | 1085 | desc->supply_name = rinfo->sname; |
d6f83370 K |
1086 | config.of_node = ddata->palmas_matches[id].of_node; |
1087 | ||
429222d0 | 1088 | rdev = devm_regulator_register(pmic->dev, desc, &config); |
d6f83370 K |
1089 | if (IS_ERR(rdev)) { |
1090 | dev_err(pmic->dev, | |
1091 | "failed to register %s regulator\n", | |
1092 | pdev_name); | |
1093 | return PTR_ERR(rdev); | |
1094 | } | |
1095 | ||
d6f83370 K |
1096 | /* Initialise sleep/init values from platform data */ |
1097 | if (pdata) { | |
1098 | reg_init = pdata->reg_init[id]; | |
1099 | if (reg_init) { | |
1100 | if (id < TPS65917_REG_REGEN1) | |
1101 | ret = palmas_ldo_init(pmic->palmas, | |
1102 | id, reg_init); | |
1103 | else | |
1104 | ret = palmas_extreg_init(pmic->palmas, | |
1105 | id, reg_init); | |
1106 | if (ret) | |
1107 | return ret; | |
1108 | } | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
cac9e916 K |
1115 | static int palmas_smps_registration(struct palmas_pmic *pmic, |
1116 | struct palmas_pmic_driver_data *ddata, | |
1117 | struct palmas_pmic_platform_data *pdata, | |
1118 | const char *pdev_name, | |
1119 | struct regulator_config config) | |
e5ce4208 | 1120 | { |
cac9e916 K |
1121 | int id, ret; |
1122 | unsigned int addr, reg; | |
e5ce4208 | 1123 | struct regulator_dev *rdev; |
e5ce4208 | 1124 | struct palmas_reg_init *reg_init; |
cf910b6b | 1125 | struct palmas_regs_info *rinfo; |
429222d0 | 1126 | struct regulator_desc *desc; |
e5ce4208 | 1127 | |
cac9e916 | 1128 | for (id = ddata->smps_start; id <= ddata->smps_end; id++) { |
28d1e8cd | 1129 | bool ramp_delay_support = false; |
e5ce4208 GG |
1130 | |
1131 | /* | |
1132 | * Miss out regulators which are not available due | |
1133 | * to slaving configurations. | |
1134 | */ | |
1135 | switch (id) { | |
1136 | case PALMAS_REG_SMPS12: | |
1137 | case PALMAS_REG_SMPS3: | |
1138 | if (pmic->smps123) | |
1139 | continue; | |
28d1e8cd LD |
1140 | if (id == PALMAS_REG_SMPS12) |
1141 | ramp_delay_support = true; | |
e5ce4208 GG |
1142 | break; |
1143 | case PALMAS_REG_SMPS123: | |
1144 | if (!pmic->smps123) | |
1145 | continue; | |
28d1e8cd | 1146 | ramp_delay_support = true; |
e5ce4208 GG |
1147 | break; |
1148 | case PALMAS_REG_SMPS45: | |
1149 | case PALMAS_REG_SMPS7: | |
1150 | if (pmic->smps457) | |
1151 | continue; | |
28d1e8cd LD |
1152 | if (id == PALMAS_REG_SMPS45) |
1153 | ramp_delay_support = true; | |
e5ce4208 GG |
1154 | break; |
1155 | case PALMAS_REG_SMPS457: | |
1156 | if (!pmic->smps457) | |
1157 | continue; | |
28d1e8cd LD |
1158 | ramp_delay_support = true; |
1159 | break; | |
77409d9b KVA |
1160 | case PALMAS_REG_SMPS10_OUT1: |
1161 | case PALMAS_REG_SMPS10_OUT2: | |
cac9e916 | 1162 | if (!PALMAS_PMIC_HAS(pmic->palmas, SMPS10_BOOST)) |
1ffb0be3 | 1163 | continue; |
28d1e8cd | 1164 | } |
cf910b6b | 1165 | rinfo = &ddata->palmas_regs_info[id]; |
429222d0 | 1166 | desc = &pmic->desc[id]; |
28d1e8cd | 1167 | |
3f4d6364 | 1168 | if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8)) |
28d1e8cd LD |
1169 | ramp_delay_support = true; |
1170 | ||
1171 | if (ramp_delay_support) { | |
cf910b6b | 1172 | addr = rinfo->tstep_addr; |
28d1e8cd LD |
1173 | ret = palmas_smps_read(pmic->palmas, addr, ®); |
1174 | if (ret < 0) { | |
cac9e916 | 1175 | dev_err(pmic->dev, |
28d1e8cd | 1176 | "reading TSTEP reg failed: %d\n", ret); |
51c86b3e | 1177 | return ret; |
28d1e8cd | 1178 | } |
429222d0 NM |
1179 | desc->ramp_delay = palmas_smps_ramp_delay[reg & 0x3]; |
1180 | pmic->ramp_delay[id] = desc->ramp_delay; | |
e5ce4208 GG |
1181 | } |
1182 | ||
bdc4baac AL |
1183 | /* Initialise sleep/init values from platform data */ |
1184 | if (pdata && pdata->reg_init[id]) { | |
1185 | reg_init = pdata->reg_init[id]; | |
cac9e916 | 1186 | ret = palmas_smps_init(pmic->palmas, id, reg_init); |
bdc4baac | 1187 | if (ret) |
51c86b3e | 1188 | return ret; |
32b6d3f6 LD |
1189 | } else { |
1190 | reg_init = NULL; | |
bdc4baac AL |
1191 | } |
1192 | ||
e5ce4208 | 1193 | /* Register the regulators */ |
429222d0 NM |
1194 | desc->name = rinfo->name; |
1195 | desc->id = id; | |
e5ce4208 | 1196 | |
fedd89b1 | 1197 | switch (id) { |
77409d9b KVA |
1198 | case PALMAS_REG_SMPS10_OUT1: |
1199 | case PALMAS_REG_SMPS10_OUT2: | |
429222d0 NM |
1200 | desc->n_voltages = PALMAS_SMPS10_NUM_VOLTAGES; |
1201 | desc->ops = &palmas_ops_smps10; | |
1202 | desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
1203 | PALMAS_SMPS10_CTRL); | |
1204 | desc->vsel_mask = SMPS10_VSEL; | |
1205 | desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
1206 | PALMAS_SMPS10_CTRL); | |
77409d9b | 1207 | if (id == PALMAS_REG_SMPS10_OUT1) |
429222d0 | 1208 | desc->enable_mask = SMPS10_SWITCH_EN; |
77409d9b | 1209 | else |
429222d0 NM |
1210 | desc->enable_mask = SMPS10_BOOST_EN; |
1211 | desc->bypass_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
1212 | PALMAS_SMPS10_CTRL); | |
e0341f17 | 1213 | desc->bypass_val_on = SMPS10_BYPASS_EN; |
429222d0 NM |
1214 | desc->bypass_mask = SMPS10_BYPASS_EN; |
1215 | desc->min_uV = 3750000; | |
1216 | desc->uV_step = 1250000; | |
fedd89b1 AL |
1217 | break; |
1218 | default: | |
bdc4baac AL |
1219 | /* |
1220 | * Read and store the RANGE bit for later use | |
1221 | * This must be done before regulator is probed, | |
51d3a0c9 LD |
1222 | * otherwise we error in probe with unsupportable |
1223 | * ranges. Read the current smps mode for later use. | |
bdc4baac | 1224 | */ |
cf910b6b | 1225 | addr = rinfo->vsel_addr; |
429222d0 | 1226 | desc->n_linear_ranges = 3; |
e5ce4208 GG |
1227 | |
1228 | ret = palmas_smps_read(pmic->palmas, addr, ®); | |
1229 | if (ret) | |
51c86b3e | 1230 | return ret; |
e5ce4208 GG |
1231 | if (reg & PALMAS_SMPS12_VOLTAGE_RANGE) |
1232 | pmic->range[id] = 1; | |
dbabd624 | 1233 | if (pmic->range[id]) |
429222d0 | 1234 | desc->linear_ranges = smps_high_ranges; |
dbabd624 | 1235 | else |
429222d0 | 1236 | desc->linear_ranges = smps_low_ranges; |
bdc4baac | 1237 | |
32b6d3f6 | 1238 | if (reg_init && reg_init->roof_floor) |
429222d0 | 1239 | desc->ops = &palmas_ops_ext_control_smps; |
32b6d3f6 | 1240 | else |
429222d0 NM |
1241 | desc->ops = &palmas_ops_smps; |
1242 | desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES; | |
1243 | desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
1244 | rinfo->vsel_addr); | |
1245 | desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK; | |
51d3a0c9 LD |
1246 | |
1247 | /* Read the smps mode for later use. */ | |
cf910b6b | 1248 | addr = rinfo->ctrl_addr; |
51d3a0c9 LD |
1249 | ret = palmas_smps_read(pmic->palmas, addr, ®); |
1250 | if (ret) | |
51c86b3e | 1251 | return ret; |
51d3a0c9 LD |
1252 | pmic->current_reg_mode[id] = reg & |
1253 | PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; | |
318dbb02 | 1254 | |
429222d0 NM |
1255 | desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, |
1256 | rinfo->ctrl_addr); | |
1257 | desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; | |
318dbb02 | 1258 | /* set_mode overrides this value */ |
429222d0 | 1259 | desc->enable_val = SMPS_CTRL_MODE_ON; |
e5ce4208 GG |
1260 | } |
1261 | ||
429222d0 NM |
1262 | desc->type = REGULATOR_VOLTAGE; |
1263 | desc->owner = THIS_MODULE; | |
bdc4baac | 1264 | |
a361cd9f | 1265 | if (pdata) |
e5ce4208 GG |
1266 | config.init_data = pdata->reg_data[id]; |
1267 | else | |
1268 | config.init_data = NULL; | |
1269 | ||
429222d0 | 1270 | desc->supply_name = rinfo->sname; |
cac9e916 | 1271 | config.of_node = ddata->palmas_matches[id].of_node; |
a361cd9f | 1272 | |
429222d0 | 1273 | rdev = devm_regulator_register(pmic->dev, desc, &config); |
e5ce4208 | 1274 | if (IS_ERR(rdev)) { |
cac9e916 | 1275 | dev_err(pmic->dev, |
e5ce4208 | 1276 | "failed to register %s regulator\n", |
cac9e916 | 1277 | pdev_name); |
51c86b3e | 1278 | return PTR_ERR(rdev); |
e5ce4208 | 1279 | } |
e5ce4208 GG |
1280 | } |
1281 | ||
cac9e916 K |
1282 | return 0; |
1283 | } | |
e5ce4208 | 1284 | |
d6f83370 K |
1285 | static int tps65917_smps_registration(struct palmas_pmic *pmic, |
1286 | struct palmas_pmic_driver_data *ddata, | |
1287 | struct palmas_pmic_platform_data *pdata, | |
1288 | const char *pdev_name, | |
1289 | struct regulator_config config) | |
1290 | { | |
1291 | int id, ret; | |
1292 | unsigned int addr, reg; | |
1293 | struct regulator_dev *rdev; | |
1294 | struct palmas_reg_init *reg_init; | |
cf910b6b | 1295 | struct palmas_regs_info *rinfo; |
429222d0 | 1296 | struct regulator_desc *desc; |
d6f83370 K |
1297 | |
1298 | for (id = ddata->smps_start; id <= ddata->smps_end; id++) { | |
1299 | /* | |
1300 | * Miss out regulators which are not available due | |
1301 | * to slaving configurations. | |
1302 | */ | |
429222d0 NM |
1303 | desc = &pmic->desc[id]; |
1304 | desc->n_linear_ranges = 3; | |
be035303 K |
1305 | if ((id == TPS65917_REG_SMPS2 || id == TPS65917_REG_SMPS1) && |
1306 | pmic->smps12) | |
d6f83370 K |
1307 | continue; |
1308 | ||
1309 | /* Initialise sleep/init values from platform data */ | |
1310 | if (pdata && pdata->reg_init[id]) { | |
1311 | reg_init = pdata->reg_init[id]; | |
1312 | ret = palmas_smps_init(pmic->palmas, id, reg_init); | |
1313 | if (ret) | |
1314 | return ret; | |
1315 | } else { | |
1316 | reg_init = NULL; | |
1317 | } | |
cf910b6b | 1318 | rinfo = &ddata->palmas_regs_info[id]; |
d6f83370 K |
1319 | |
1320 | /* Register the regulators */ | |
429222d0 NM |
1321 | desc->name = rinfo->name; |
1322 | desc->id = id; | |
d6f83370 K |
1323 | |
1324 | /* | |
1325 | * Read and store the RANGE bit for later use | |
1326 | * This must be done before regulator is probed, | |
1327 | * otherwise we error in probe with unsupportable | |
1328 | * ranges. Read the current smps mode for later use. | |
1329 | */ | |
cf910b6b | 1330 | addr = rinfo->vsel_addr; |
d6f83370 K |
1331 | |
1332 | ret = palmas_smps_read(pmic->palmas, addr, ®); | |
1333 | if (ret) | |
1334 | return ret; | |
1335 | if (reg & TPS65917_SMPS1_VOLTAGE_RANGE) | |
1336 | pmic->range[id] = 1; | |
1337 | ||
1338 | if (pmic->range[id]) | |
429222d0 NM |
1339 | desc->linear_ranges = smps_high_ranges; |
1340 | else | |
1341 | desc->linear_ranges = smps_low_ranges; | |
d6f83370 K |
1342 | |
1343 | if (reg_init && reg_init->roof_floor) | |
429222d0 | 1344 | desc->ops = &tps65917_ops_ext_control_smps; |
d6f83370 | 1345 | else |
429222d0 NM |
1346 | desc->ops = &tps65917_ops_smps; |
1347 | desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES; | |
1348 | desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, | |
1349 | rinfo->vsel_addr); | |
1350 | desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK; | |
1351 | desc->ramp_delay = 2500; | |
d6f83370 K |
1352 | |
1353 | /* Read the smps mode for later use. */ | |
cf910b6b | 1354 | addr = rinfo->ctrl_addr; |
d6f83370 K |
1355 | ret = palmas_smps_read(pmic->palmas, addr, ®); |
1356 | if (ret) | |
1357 | return ret; | |
1358 | pmic->current_reg_mode[id] = reg & | |
1359 | PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; | |
b632815e NM |
1360 | desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, |
1361 | rinfo->ctrl_addr); | |
1362 | desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK; | |
1363 | /* set_mode overrides this value */ | |
1364 | desc->enable_val = SMPS_CTRL_MODE_ON; | |
d6f83370 | 1365 | |
429222d0 NM |
1366 | desc->type = REGULATOR_VOLTAGE; |
1367 | desc->owner = THIS_MODULE; | |
d6f83370 K |
1368 | |
1369 | if (pdata) | |
1370 | config.init_data = pdata->reg_data[id]; | |
1371 | else | |
1372 | config.init_data = NULL; | |
1373 | ||
429222d0 | 1374 | desc->supply_name = rinfo->sname; |
d6f83370 K |
1375 | config.of_node = ddata->palmas_matches[id].of_node; |
1376 | ||
429222d0 | 1377 | rdev = devm_regulator_register(pmic->dev, desc, &config); |
d6f83370 K |
1378 | if (IS_ERR(rdev)) { |
1379 | dev_err(pmic->dev, | |
1380 | "failed to register %s regulator\n", | |
1381 | pdev_name); | |
1382 | return PTR_ERR(rdev); | |
1383 | } | |
d6f83370 K |
1384 | } |
1385 | ||
1386 | return 0; | |
1387 | } | |
1388 | ||
cac9e916 K |
1389 | static struct of_regulator_match palmas_matches[] = { |
1390 | { .name = "smps12", }, | |
1391 | { .name = "smps123", }, | |
1392 | { .name = "smps3", }, | |
1393 | { .name = "smps45", }, | |
1394 | { .name = "smps457", }, | |
1395 | { .name = "smps6", }, | |
1396 | { .name = "smps7", }, | |
1397 | { .name = "smps8", }, | |
1398 | { .name = "smps9", }, | |
1399 | { .name = "smps10_out2", }, | |
1400 | { .name = "smps10_out1", }, | |
1401 | { .name = "ldo1", }, | |
1402 | { .name = "ldo2", }, | |
1403 | { .name = "ldo3", }, | |
1404 | { .name = "ldo4", }, | |
1405 | { .name = "ldo5", }, | |
1406 | { .name = "ldo6", }, | |
1407 | { .name = "ldo7", }, | |
1408 | { .name = "ldo8", }, | |
1409 | { .name = "ldo9", }, | |
1410 | { .name = "ldoln", }, | |
1411 | { .name = "ldousb", }, | |
1412 | { .name = "regen1", }, | |
1413 | { .name = "regen2", }, | |
1414 | { .name = "regen3", }, | |
1415 | { .name = "sysen1", }, | |
1416 | { .name = "sysen2", }, | |
1417 | }; | |
e5ce4208 | 1418 | |
d6f83370 K |
1419 | static struct of_regulator_match tps65917_matches[] = { |
1420 | { .name = "smps1", }, | |
1421 | { .name = "smps2", }, | |
1422 | { .name = "smps3", }, | |
1423 | { .name = "smps4", }, | |
1424 | { .name = "smps5", }, | |
be035303 | 1425 | { .name = "smps12",}, |
d6f83370 K |
1426 | { .name = "ldo1", }, |
1427 | { .name = "ldo2", }, | |
1428 | { .name = "ldo3", }, | |
1429 | { .name = "ldo4", }, | |
1430 | { .name = "ldo5", }, | |
1431 | { .name = "regen1", }, | |
1432 | { .name = "regen2", }, | |
1433 | { .name = "regen3", }, | |
1434 | { .name = "sysen1", }, | |
1435 | { .name = "sysen2", }, | |
1436 | }; | |
1437 | ||
4b09e17b | 1438 | static struct palmas_pmic_driver_data palmas_ddata = { |
cac9e916 K |
1439 | .smps_start = PALMAS_REG_SMPS12, |
1440 | .smps_end = PALMAS_REG_SMPS10_OUT1, | |
1441 | .ldo_begin = PALMAS_REG_LDO1, | |
1442 | .ldo_end = PALMAS_REG_LDOUSB, | |
1443 | .max_reg = PALMAS_NUM_REGS, | |
e999c728 | 1444 | .has_regen3 = true, |
6839cd6f | 1445 | .palmas_regs_info = palmas_generic_regs_info, |
cac9e916 K |
1446 | .palmas_matches = palmas_matches, |
1447 | .sleep_req_info = palma_sleep_req_info, | |
1448 | .smps_register = palmas_smps_registration, | |
1449 | .ldo_register = palmas_ldo_registration, | |
1450 | }; | |
aa07f027 | 1451 | |
4b09e17b | 1452 | static struct palmas_pmic_driver_data tps65917_ddata = { |
d6f83370 | 1453 | .smps_start = TPS65917_REG_SMPS1, |
be035303 | 1454 | .smps_end = TPS65917_REG_SMPS12, |
d6f83370 K |
1455 | .ldo_begin = TPS65917_REG_LDO1, |
1456 | .ldo_end = TPS65917_REG_LDO5, | |
1457 | .max_reg = TPS65917_NUM_REGS, | |
e999c728 | 1458 | .has_regen3 = true, |
d6f83370 K |
1459 | .palmas_regs_info = tps65917_regs_info, |
1460 | .palmas_matches = tps65917_matches, | |
1461 | .sleep_req_info = tps65917_sleep_req_info, | |
1462 | .smps_register = tps65917_smps_registration, | |
1463 | .ldo_register = tps65917_ldo_registration, | |
1464 | }; | |
1465 | ||
7f091e53 NM |
1466 | static int palmas_dt_to_pdata(struct device *dev, |
1467 | struct device_node *node, | |
1468 | struct palmas_pmic_platform_data *pdata, | |
1469 | struct palmas_pmic_driver_data *ddata) | |
cac9e916 K |
1470 | { |
1471 | struct device_node *regulators; | |
1472 | u32 prop; | |
1473 | int idx, ret; | |
17c11a76 | 1474 | |
cac9e916 K |
1475 | regulators = of_get_child_by_name(node, "regulators"); |
1476 | if (!regulators) { | |
1477 | dev_info(dev, "regulator node not found\n"); | |
7f091e53 | 1478 | return 0; |
cac9e916 | 1479 | } |
087d30e3 | 1480 | |
cac9e916 K |
1481 | ret = of_regulator_match(dev, regulators, ddata->palmas_matches, |
1482 | ddata->max_reg); | |
1483 | of_node_put(regulators); | |
1484 | if (ret < 0) { | |
1485 | dev_err(dev, "Error parsing regulator init data: %d\n", ret); | |
7f091e53 | 1486 | return 0; |
cac9e916 | 1487 | } |
e5ce4208 | 1488 | |
cac9e916 | 1489 | for (idx = 0; idx < ddata->max_reg; idx++) { |
96e4f523 | 1490 | struct of_regulator_match *match; |
1b42443d | 1491 | struct palmas_reg_init *rinit; |
6c7d614f | 1492 | struct device_node *np; |
036d193d NM |
1493 | |
1494 | match = &ddata->palmas_matches[idx]; | |
6c7d614f | 1495 | np = match->of_node; |
036d193d | 1496 | |
6c7d614f | 1497 | if (!match->init_data || !np) |
cac9e916 | 1498 | continue; |
e5ce4208 | 1499 | |
1b42443d | 1500 | rinit = devm_kzalloc(dev, sizeof(*rinit), GFP_KERNEL); |
7f091e53 NM |
1501 | if (!rinit) |
1502 | return -ENOMEM; | |
1503 | ||
036d193d | 1504 | pdata->reg_data[idx] = match->init_data; |
1b42443d | 1505 | pdata->reg_init[idx] = rinit; |
a361cd9f | 1506 | |
6c7d614f NM |
1507 | rinit->warm_reset = of_property_read_bool(np, "ti,warm-reset"); |
1508 | ret = of_property_read_u32(np, "ti,roof-floor", &prop); | |
cac9e916 K |
1509 | /* EINVAL: Property not found */ |
1510 | if (ret != -EINVAL) { | |
1511 | int econtrol; | |
1512 | ||
1513 | /* use default value, when no value is specified */ | |
1514 | econtrol = PALMAS_EXT_CONTROL_NSLEEP; | |
1515 | if (!ret) { | |
1516 | switch (prop) { | |
1517 | case 1: | |
1518 | econtrol = PALMAS_EXT_CONTROL_ENABLE1; | |
1519 | break; | |
1520 | case 2: | |
1521 | econtrol = PALMAS_EXT_CONTROL_ENABLE2; | |
1522 | break; | |
1523 | case 3: | |
1524 | econtrol = PALMAS_EXT_CONTROL_NSLEEP; | |
1525 | break; | |
1526 | default: | |
1527 | WARN_ON(1); | |
1528 | dev_warn(dev, | |
1529 | "%s: Invalid roof-floor option: %u\n", | |
036d193d | 1530 | match->name, prop); |
cac9e916 K |
1531 | break; |
1532 | } | |
e5ce4208 | 1533 | } |
1b42443d | 1534 | rinit->roof_floor = econtrol; |
e5ce4208 | 1535 | } |
e5ce4208 | 1536 | |
6c7d614f | 1537 | ret = of_property_read_u32(np, "ti,mode-sleep", &prop); |
cac9e916 | 1538 | if (!ret) |
1b42443d | 1539 | rinit->mode_sleep = prop; |
17c11a76 | 1540 | |
6c7d614f | 1541 | ret = of_property_read_bool(np, "ti,smps-range"); |
cac9e916 | 1542 | if (ret) |
1b42443d | 1543 | rinit->vsel = PALMAS_SMPS12_VOLTAGE_RANGE; |
cac9e916 K |
1544 | |
1545 | if (idx == PALMAS_REG_LDO8) | |
1546 | pdata->enable_ldo8_tracking = of_property_read_bool( | |
6c7d614f | 1547 | np, "ti,enable-ldo8-tracking"); |
cac9e916 K |
1548 | } |
1549 | ||
1550 | pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator"); | |
7f091e53 NM |
1551 | |
1552 | return 0; | |
e5ce4208 GG |
1553 | } |
1554 | ||
cdbf6f0e | 1555 | static const struct of_device_id of_palmas_match_tbl[] = { |
cac9e916 K |
1556 | { |
1557 | .compatible = "ti,palmas-pmic", | |
1558 | .data = &palmas_ddata, | |
1559 | }, | |
1560 | { | |
1561 | .compatible = "ti,twl6035-pmic", | |
1562 | .data = &palmas_ddata, | |
1563 | }, | |
1564 | { | |
1565 | .compatible = "ti,twl6036-pmic", | |
1566 | .data = &palmas_ddata, | |
1567 | }, | |
1568 | { | |
1569 | .compatible = "ti,twl6037-pmic", | |
1570 | .data = &palmas_ddata, | |
1571 | }, | |
1572 | { | |
1573 | .compatible = "ti,tps65913-pmic", | |
1574 | .data = &palmas_ddata, | |
1575 | }, | |
1576 | { | |
1577 | .compatible = "ti,tps65914-pmic", | |
1578 | .data = &palmas_ddata, | |
1579 | }, | |
1580 | { | |
1581 | .compatible = "ti,tps80036-pmic", | |
1582 | .data = &palmas_ddata, | |
1583 | }, | |
1584 | { | |
1585 | .compatible = "ti,tps659038-pmic", | |
1586 | .data = &palmas_ddata, | |
d6f83370 K |
1587 | }, |
1588 | { | |
1589 | .compatible = "ti,tps65917-pmic", | |
1590 | .data = &tps65917_ddata, | |
cac9e916 | 1591 | }, |
a361cd9f GG |
1592 | { /* end */ } |
1593 | }; | |
1594 | ||
cac9e916 K |
1595 | static int palmas_regulators_probe(struct platform_device *pdev) |
1596 | { | |
1597 | struct palmas *palmas = dev_get_drvdata(pdev->dev.parent); | |
1598 | struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev); | |
1599 | struct device_node *node = pdev->dev.of_node; | |
1600 | struct palmas_pmic_driver_data *driver_data; | |
1601 | struct regulator_config config = { }; | |
1602 | struct palmas_pmic *pmic; | |
1603 | const char *pdev_name; | |
1604 | const struct of_device_id *match; | |
1605 | int ret = 0; | |
1606 | unsigned int reg; | |
1607 | ||
1608 | match = of_match_device(of_match_ptr(of_palmas_match_tbl), &pdev->dev); | |
1609 | ||
1610 | if (!match) | |
1611 | return -ENODATA; | |
1612 | ||
1613 | driver_data = (struct palmas_pmic_driver_data *)match->data; | |
1614 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1615 | if (!pdata) | |
1616 | return -ENOMEM; | |
1617 | ||
1618 | pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); | |
1619 | if (!pmic) | |
1620 | return -ENOMEM; | |
1621 | ||
e999c728 | 1622 | if (of_device_is_compatible(node, "ti,tps659038-pmic")) { |
e03826d5 K |
1623 | palmas_generic_regs_info[PALMAS_REG_REGEN2].ctrl_addr = |
1624 | TPS659038_REGEN2_CTRL; | |
e999c728 K |
1625 | palmas_ddata.has_regen3 = false; |
1626 | } | |
e03826d5 | 1627 | |
cac9e916 K |
1628 | pmic->dev = &pdev->dev; |
1629 | pmic->palmas = palmas; | |
1630 | palmas->pmic = pmic; | |
1631 | platform_set_drvdata(pdev, pmic); | |
1632 | pmic->palmas->pmic_ddata = driver_data; | |
1633 | ||
7f091e53 NM |
1634 | ret = palmas_dt_to_pdata(&pdev->dev, node, pdata, driver_data); |
1635 | if (ret) | |
1636 | return ret; | |
cac9e916 K |
1637 | |
1638 | ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, ®); | |
1639 | if (ret) | |
1640 | return ret; | |
1641 | ||
be035303 | 1642 | if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN) { |
cac9e916 | 1643 | pmic->smps123 = 1; |
be035303 K |
1644 | pmic->smps12 = 1; |
1645 | } | |
cac9e916 K |
1646 | |
1647 | if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN) | |
1648 | pmic->smps457 = 1; | |
1649 | ||
1650 | config.regmap = palmas->regmap[REGULATOR_SLAVE]; | |
1651 | config.dev = &pdev->dev; | |
1652 | config.driver_data = pmic; | |
1653 | pdev_name = pdev->name; | |
1654 | ||
1655 | ret = driver_data->smps_register(pmic, driver_data, pdata, pdev_name, | |
1656 | config); | |
1657 | if (ret) | |
1658 | return ret; | |
1659 | ||
1660 | ret = driver_data->ldo_register(pmic, driver_data, pdata, pdev_name, | |
1661 | config); | |
1662 | ||
1663 | return ret; | |
1664 | } | |
1665 | ||
e5ce4208 GG |
1666 | static struct platform_driver palmas_driver = { |
1667 | .driver = { | |
1668 | .name = "palmas-pmic", | |
a361cd9f | 1669 | .of_match_table = of_palmas_match_tbl, |
e5ce4208 | 1670 | }, |
bbcf50b1 | 1671 | .probe = palmas_regulators_probe, |
e5ce4208 GG |
1672 | }; |
1673 | ||
1674 | static int __init palmas_init(void) | |
1675 | { | |
1676 | return platform_driver_register(&palmas_driver); | |
1677 | } | |
1678 | subsys_initcall(palmas_init); | |
1679 | ||
1680 | static void __exit palmas_exit(void) | |
1681 | { | |
1682 | platform_driver_unregister(&palmas_driver); | |
1683 | } | |
1684 | module_exit(palmas_exit); | |
1685 | ||
1686 | MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>"); | |
1687 | MODULE_DESCRIPTION("Palmas voltage regulator driver"); | |
1688 | MODULE_LICENSE("GPL"); | |
1689 | MODULE_ALIAS("platform:palmas-pmic"); | |
a361cd9f | 1690 | MODULE_DEVICE_TABLE(of, of_palmas_match_tbl); |