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regulator: palmas: remove redundant initialization of pointer pdata
[linux-2.6-block.git] / drivers / regulator / palmas-regulator.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
e5ce4208
GG		 2/*
3 * Driver for Regulator part of Palmas PMIC Chips
4 *
7be859f7 5 * Copyright 2011-2013 Texas Instruments Inc.
e5ce4208
GG		 6 *
7 * Author: Graeme Gregory <gg@slimlogic.co.uk>
a7dddf27 8 * Author: Ian Lartey <ian@slimlogic.co.uk>
e5ce4208
GG		 9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/err.h>
15#include <linux/platform_device.h>
16#include <linux/regulator/driver.h>
17#include <linux/regulator/machine.h>
18#include <linux/slab.h>
19#include <linux/regmap.h>
20#include <linux/mfd/palmas.h>
a361cd9f 21#include <linux/of.h>
a361cd9f 22#include <linux/regulator/of_regulator.h>
e5ce4208 23
60ab7f41 24static const struct linear_range smps_low_ranges[] = {
6b7f2d82 25 REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
dbabd624
K		 26 REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0),
27 REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000),
28 REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0),
29};
30
60ab7f41 31static const struct linear_range smps_high_ranges[] = {
6b7f2d82 32 REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
dbabd624
K		 33 REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0),
34 REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000),
35 REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0),
36};
37
6839cd6f 38static struct palmas_regs_info palmas_generic_regs_info[] = {
e5ce4208
GG		 39 {
40 .name = "SMPS12",
504382c9 41 .sname = "smps1-in",
e5ce4208
GG		 42 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
43 .ctrl_addr = PALMAS_SMPS12_CTRL,
44 .tstep_addr = PALMAS_SMPS12_TSTEP,
32b6d3f6 45 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
e5ce4208
GG		 46 },
47 {
48 .name = "SMPS123",
504382c9 49 .sname = "smps1-in",
e5ce4208
GG		 50 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
51 .ctrl_addr = PALMAS_SMPS12_CTRL,
52 .tstep_addr = PALMAS_SMPS12_TSTEP,
32b6d3f6 53 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
e5ce4208
GG		 54 },
55 {
56 .name = "SMPS3",
504382c9 57 .sname = "smps3-in",
e5ce4208
GG		 58 .vsel_addr = PALMAS_SMPS3_VOLTAGE,
59 .ctrl_addr = PALMAS_SMPS3_CTRL,
32b6d3f6 60 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
e5ce4208
GG		 61 },
62 {
63 .name = "SMPS45",
504382c9 64 .sname = "smps4-in",
e5ce4208
GG		 65 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
66 .ctrl_addr = PALMAS_SMPS45_CTRL,
67 .tstep_addr = PALMAS_SMPS45_TSTEP,
32b6d3f6 68 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
e5ce4208
GG		 69 },
70 {
71 .name = "SMPS457",
504382c9 72 .sname = "smps4-in",
e5ce4208
GG		 73 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
74 .ctrl_addr = PALMAS_SMPS45_CTRL,
75 .tstep_addr = PALMAS_SMPS45_TSTEP,
32b6d3f6 76 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
e5ce4208
GG		 77 },
78 {
79 .name = "SMPS6",
504382c9 80 .sname = "smps6-in",
e5ce4208
GG		 81 .vsel_addr = PALMAS_SMPS6_VOLTAGE,
82 .ctrl_addr = PALMAS_SMPS6_CTRL,
83 .tstep_addr = PALMAS_SMPS6_TSTEP,
32b6d3f6 84 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
e5ce4208
GG		 85 },
86 {
87 .name = "SMPS7",
504382c9 88 .sname = "smps7-in",
e5ce4208
GG		 89 .vsel_addr = PALMAS_SMPS7_VOLTAGE,
90 .ctrl_addr = PALMAS_SMPS7_CTRL,
32b6d3f6 91 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
e5ce4208
GG		 92 },
93 {
94 .name = "SMPS8",
504382c9 95 .sname = "smps8-in",
e5ce4208
GG		 96 .vsel_addr = PALMAS_SMPS8_VOLTAGE,
97 .ctrl_addr = PALMAS_SMPS8_CTRL,
98 .tstep_addr = PALMAS_SMPS8_TSTEP,
32b6d3f6 99 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
e5ce4208
GG		 100 },
101 {
102 .name = "SMPS9",
504382c9 103 .sname = "smps9-in",
e5ce4208
GG		 104 .vsel_addr = PALMAS_SMPS9_VOLTAGE,
105 .ctrl_addr = PALMAS_SMPS9_CTRL,
32b6d3f6 106 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
e5ce4208
GG		 107 },
108 {
77409d9b 109 .name = "SMPS10_OUT2",
504382c9 110 .sname = "smps10-in",
e31089c6 111 .ctrl_addr = PALMAS_SMPS10_CTRL,
32b6d3f6 112 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
e5ce4208 113 },
77409d9b
KVA		 114 {
115 .name = "SMPS10_OUT1",
116 .sname = "smps10-out2",
117 .ctrl_addr = PALMAS_SMPS10_CTRL,
32b6d3f6 118 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
77409d9b 119 },
e5ce4208
GG		 120 {
121 .name = "LDO1",
504382c9 122 .sname = "ldo1-in",
e5ce4208
GG		 123 .vsel_addr = PALMAS_LDO1_VOLTAGE,
124 .ctrl_addr = PALMAS_LDO1_CTRL,
32b6d3f6 125 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO1,
e5ce4208
GG		 126 },
127 {
128 .name = "LDO2",
504382c9 129 .sname = "ldo2-in",
e5ce4208
GG		 130 .vsel_addr = PALMAS_LDO2_VOLTAGE,
131 .ctrl_addr = PALMAS_LDO2_CTRL,
32b6d3f6 132 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO2,
e5ce4208
GG		 133 },
134 {
135 .name = "LDO3",
504382c9 136 .sname = "ldo3-in",
e5ce4208
GG		 137 .vsel_addr = PALMAS_LDO3_VOLTAGE,
138 .ctrl_addr = PALMAS_LDO3_CTRL,
32b6d3f6 139 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO3,
e5ce4208
GG		 140 },
141 {
142 .name = "LDO4",
504382c9 143 .sname = "ldo4-in",
e5ce4208
GG		 144 .vsel_addr = PALMAS_LDO4_VOLTAGE,
145 .ctrl_addr = PALMAS_LDO4_CTRL,
32b6d3f6 146 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO4,
e5ce4208
GG		 147 },
148 {
149 .name = "LDO5",
504382c9 150 .sname = "ldo5-in",
e5ce4208
GG		 151 .vsel_addr = PALMAS_LDO5_VOLTAGE,
152 .ctrl_addr = PALMAS_LDO5_CTRL,
32b6d3f6 153 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO5,
e5ce4208
GG		 154 },
155 {
156 .name = "LDO6",
504382c9 157 .sname = "ldo6-in",
e5ce4208
GG		 158 .vsel_addr = PALMAS_LDO6_VOLTAGE,
159 .ctrl_addr = PALMAS_LDO6_CTRL,
32b6d3f6 160 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO6,
e5ce4208
GG		 161 },
162 {
163 .name = "LDO7",
504382c9 164 .sname = "ldo7-in",
e5ce4208
GG		 165 .vsel_addr = PALMAS_LDO7_VOLTAGE,
166 .ctrl_addr = PALMAS_LDO7_CTRL,
32b6d3f6 167 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO7,
e5ce4208
GG		 168 },
169 {
170 .name = "LDO8",
504382c9 171 .sname = "ldo8-in",
e5ce4208
GG		 172 .vsel_addr = PALMAS_LDO8_VOLTAGE,
173 .ctrl_addr = PALMAS_LDO8_CTRL,
32b6d3f6 174 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO8,
e5ce4208
GG		 175 },
176 {
177 .name = "LDO9",
504382c9 178 .sname = "ldo9-in",
e5ce4208
GG		 179 .vsel_addr = PALMAS_LDO9_VOLTAGE,
180 .ctrl_addr = PALMAS_LDO9_CTRL,
32b6d3f6 181 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO9,
e5ce4208
GG		 182 },
183 {
184 .name = "LDOLN",
504382c9 185 .sname = "ldoln-in",
e5ce4208
GG		 186 .vsel_addr = PALMAS_LDOLN_VOLTAGE,
187 .ctrl_addr = PALMAS_LDOLN_CTRL,
32b6d3f6 188 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
e5ce4208
GG		 189 },
190 {
191 .name = "LDOUSB",
504382c9 192 .sname = "ldousb-in",
e5ce4208
GG		 193 .vsel_addr = PALMAS_LDOUSB_VOLTAGE,
194 .ctrl_addr = PALMAS_LDOUSB_CTRL,
32b6d3f6 195 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
e5ce4208 196 },
aa07f027
LD		 197 {
198 .name = "REGEN1",
199 .ctrl_addr = PALMAS_REGEN1_CTRL,
32b6d3f6 200 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
aa07f027
LD		 201 },
202 {
203 .name = "REGEN2",
204 .ctrl_addr = PALMAS_REGEN2_CTRL,
32b6d3f6 205 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
aa07f027
LD		 206 },
207 {
208 .name = "REGEN3",
209 .ctrl_addr = PALMAS_REGEN3_CTRL,
32b6d3f6 210 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
aa07f027
LD		 211 },
212 {
213 .name = "SYSEN1",
214 .ctrl_addr = PALMAS_SYSEN1_CTRL,
32b6d3f6 215 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
aa07f027
LD		 216 },
217 {
218 .name = "SYSEN2",
219 .ctrl_addr = PALMAS_SYSEN2_CTRL,
32b6d3f6 220 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
aa07f027 221 },
e5ce4208
GG		 222};
223
e7cf34ef 224static struct palmas_regs_info tps65917_regs_info[] = {
d6f83370
K		 225 {
226 .name = "SMPS1",
227 .sname = "smps1-in",
228 .vsel_addr = TPS65917_SMPS1_VOLTAGE,
229 .ctrl_addr = TPS65917_SMPS1_CTRL,
230 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
231 },
232 {
233 .name = "SMPS2",
234 .sname = "smps2-in",
235 .vsel_addr = TPS65917_SMPS2_VOLTAGE,
236 .ctrl_addr = TPS65917_SMPS2_CTRL,
237 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
238 },
239 {
240 .name = "SMPS3",
241 .sname = "smps3-in",
242 .vsel_addr = TPS65917_SMPS3_VOLTAGE,
243 .ctrl_addr = TPS65917_SMPS3_CTRL,
244 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
245 },
246 {
247 .name = "SMPS4",
248 .sname = "smps4-in",
249 .vsel_addr = TPS65917_SMPS4_VOLTAGE,
250 .ctrl_addr = TPS65917_SMPS4_CTRL,
251 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
252 },
253 {
254 .name = "SMPS5",
255 .sname = "smps5-in",
256 .vsel_addr = TPS65917_SMPS5_VOLTAGE,
257 .ctrl_addr = TPS65917_SMPS5_CTRL,
258 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
259 },
be035303
K		 260 {
261 .name = "SMPS12",
262 .sname = "smps1-in",
263 .vsel_addr = TPS65917_SMPS1_VOLTAGE,
264 .ctrl_addr = TPS65917_SMPS1_CTRL,
265 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS12,
266 },
d6f83370
K		 267 {
268 .name = "LDO1",
269 .sname = "ldo1-in",
270 .vsel_addr = TPS65917_LDO1_VOLTAGE,
271 .ctrl_addr = TPS65917_LDO1_CTRL,
272 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1,
273 },
274 {
275 .name = "LDO2",
276 .sname = "ldo2-in",
277 .vsel_addr = TPS65917_LDO2_VOLTAGE,
278 .ctrl_addr = TPS65917_LDO2_CTRL,
279 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2,
280 },
281 {
282 .name = "LDO3",
283 .sname = "ldo3-in",
284 .vsel_addr = TPS65917_LDO3_VOLTAGE,
285 .ctrl_addr = TPS65917_LDO3_CTRL,
286 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3,
287 },
288 {
289 .name = "LDO4",
290 .sname = "ldo4-in",
291 .vsel_addr = TPS65917_LDO4_VOLTAGE,
292 .ctrl_addr = TPS65917_LDO4_CTRL,
293 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4,
294 },
295 {
296 .name = "LDO5",
297 .sname = "ldo5-in",
298 .vsel_addr = TPS65917_LDO5_VOLTAGE,
299 .ctrl_addr = TPS65917_LDO5_CTRL,
300 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5,
301 },
302 {
303 .name = "REGEN1",
304 .ctrl_addr = TPS65917_REGEN1_CTRL,
305 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
306 },
307 {
308 .name = "REGEN2",
309 .ctrl_addr = TPS65917_REGEN2_CTRL,
310 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
311 },
312 {
313 .name = "REGEN3",
314 .ctrl_addr = TPS65917_REGEN3_CTRL,
315 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
316 },
317};
318
cac9e916
K		 319#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
320 [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
321 .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
322 .reg_offset = _offset, \
323 .bit_pos = _pos, \
324 }
325
4b09e17b 326static struct palmas_sleep_requestor_info palma_sleep_req_info[] = {
cac9e916
K		 327 EXTERNAL_REQUESTOR(REGEN1, 0, 0),
328 EXTERNAL_REQUESTOR(REGEN2, 0, 1),
329 EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
330 EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
331 EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
332 EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
333 EXTERNAL_REQUESTOR(REGEN3, 0, 6),
334 EXTERNAL_REQUESTOR(SMPS12, 1, 0),
335 EXTERNAL_REQUESTOR(SMPS3, 1, 1),
336 EXTERNAL_REQUESTOR(SMPS45, 1, 2),
337 EXTERNAL_REQUESTOR(SMPS6, 1, 3),
338 EXTERNAL_REQUESTOR(SMPS7, 1, 4),
339 EXTERNAL_REQUESTOR(SMPS8, 1, 5),
340 EXTERNAL_REQUESTOR(SMPS9, 1, 6),
341 EXTERNAL_REQUESTOR(SMPS10, 1, 7),
342 EXTERNAL_REQUESTOR(LDO1, 2, 0),
343 EXTERNAL_REQUESTOR(LDO2, 2, 1),
344 EXTERNAL_REQUESTOR(LDO3, 2, 2),
345 EXTERNAL_REQUESTOR(LDO4, 2, 3),
346 EXTERNAL_REQUESTOR(LDO5, 2, 4),
347 EXTERNAL_REQUESTOR(LDO6, 2, 5),
348 EXTERNAL_REQUESTOR(LDO7, 2, 6),
349 EXTERNAL_REQUESTOR(LDO8, 2, 7),
350 EXTERNAL_REQUESTOR(LDO9, 3, 0),
351 EXTERNAL_REQUESTOR(LDOLN, 3, 1),
352 EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
353};
354
d6f83370
K		 355#define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \
356 [TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \
357 .id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \
358 .reg_offset = _offset, \
359 .bit_pos = _pos, \
360 }
361
362static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = {
363 EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0),
364 EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1),
365 EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6),
366 EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0),
367 EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1),
368 EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2),
369 EXTERNAL_REQUESTOR_TPS65917(SMPS4, 1, 3),
370 EXTERNAL_REQUESTOR_TPS65917(SMPS5, 1, 4),
be035303 371 EXTERNAL_REQUESTOR_TPS65917(SMPS12, 1, 5),
d6f83370
K		 372 EXTERNAL_REQUESTOR_TPS65917(LDO1, 2, 0),
373 EXTERNAL_REQUESTOR_TPS65917(LDO2, 2, 1),
374 EXTERNAL_REQUESTOR_TPS65917(LDO3, 2, 2),
375 EXTERNAL_REQUESTOR_TPS65917(LDO4, 2, 3),
376 EXTERNAL_REQUESTOR_TPS65917(LDO5, 2, 4),
377};
378
ad542a52 379static const unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
28d1e8cd 380
e5ce4208
GG		 381#define SMPS_CTRL_MODE_OFF 0x00
382#define SMPS_CTRL_MODE_ON 0x01
383#define SMPS_CTRL_MODE_ECO 0x02
384#define SMPS_CTRL_MODE_PWM 0x03
385
0f45aa84 386#define PALMAS_SMPS_NUM_VOLTAGES 122
e5ce4208
GG		 387#define PALMAS_SMPS10_NUM_VOLTAGES 2
388#define PALMAS_LDO_NUM_VOLTAGES 50
389
390#define SMPS10_VSEL (1<<3)
391#define SMPS10_BOOST_EN (1<<2)
392#define SMPS10_BYPASS_EN (1<<1)
393#define SMPS10_SWITCH_EN (1<<0)
394
395#define REGULATOR_SLAVE 0
396
397static int palmas_smps_read(struct palmas *palmas, unsigned int reg,
398 unsigned int *dest)
399{
400 unsigned int addr;
401
402 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
403
404 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
405}
406
407static int palmas_smps_write(struct palmas *palmas, unsigned int reg,
408 unsigned int value)
409{
410 unsigned int addr;
411
412 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
413
414 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
415}
416
417static int palmas_ldo_read(struct palmas *palmas, unsigned int reg,
418 unsigned int *dest)
419{
420 unsigned int addr;
421
422 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
423
424 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
425}
426
427static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
428 unsigned int value)
429{
430 unsigned int addr;
431
432 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
433
434 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
435}
436
e5ce4208
GG		 437static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
438{
cf910b6b 439 int id = rdev_get_id(dev);
966e927b 440 int ret;
e5ce4208 441 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
cac9e916 442 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
cf910b6b 443 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
e5ce4208 444 unsigned int reg;
51d3a0c9 445 bool rail_enable = true;
e5ce4208 446
966e927b
KL		 447 ret = palmas_smps_read(pmic->palmas, rinfo->ctrl_addr, &reg);
448 if (ret)
449 return ret;
cac9e916 450
999f0c7c 451 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208 452
51d3a0c9
LD		 453 if (reg == SMPS_CTRL_MODE_OFF)
454 rail_enable = false;
455
e5ce4208
GG		 456 switch (mode) {
457 case REGULATOR_MODE_NORMAL:
458 reg |= SMPS_CTRL_MODE_ON;
459 break;
460 case REGULATOR_MODE_IDLE:
461 reg |= SMPS_CTRL_MODE_ECO;
462 break;
463 case REGULATOR_MODE_FAST:
464 reg |= SMPS_CTRL_MODE_PWM;
465 break;
466 default:
467 return -EINVAL;
468 }
e5ce4208 469
51d3a0c9
LD		 470 pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
471 if (rail_enable)
cf910b6b 472 palmas_smps_write(pmic->palmas, rinfo->ctrl_addr, reg);
318dbb02
NM		 473
474 /* Switch the enable value to ensure this is used for enable */
475 pmic->desc[id].enable_val = pmic->current_reg_mode[id];
476
e5ce4208
GG		 477 return 0;
478}
479
480static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
481{
482 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
483 int id = rdev_get_id(dev);
484 unsigned int reg;
485
51d3a0c9 486 reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
e5ce4208
GG		 487
488 switch (reg) {
489 case SMPS_CTRL_MODE_ON:
490 return REGULATOR_MODE_NORMAL;
491 case SMPS_CTRL_MODE_ECO:
492 return REGULATOR_MODE_IDLE;
493 case SMPS_CTRL_MODE_PWM:
494 return REGULATOR_MODE_FAST;
495 }
496
497 return 0;
498}
499
28d1e8cd
LD		 500static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
501 int ramp_delay)
502{
cf910b6b 503 int id = rdev_get_id(rdev);
28d1e8cd 504 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
cac9e916 505 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
cf910b6b 506 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
28d1e8cd 507 unsigned int reg = 0;
28d1e8cd
LD		 508 int ret;
509
f22c2bae
AL		 510 /* SMPS3 and SMPS7 do not have tstep_addr setting */
511 switch (id) {
512 case PALMAS_REG_SMPS3:
513 case PALMAS_REG_SMPS7:
514 return 0;
515 }
516
28d1e8cd
LD		 517 if (ramp_delay <= 0)
518 reg = 0;
0ea34b57 519 else if (ramp_delay <= 2500)
28d1e8cd 520 reg = 3;
0ea34b57 521 else if (ramp_delay <= 5000)
28d1e8cd
LD		 522 reg = 2;
523 else
524 reg = 1;
525
cf910b6b 526 ret = palmas_smps_write(pmic->palmas, rinfo->tstep_addr, reg);
28d1e8cd
LD		 527 if (ret < 0) {
528 dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
529 return ret;
530 }
531
532 pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg];
533 return ret;
534}
535
0e5a7680 536static const struct regulator_ops palmas_ops_smps = {
dbabd624
K		 537 .is_enabled = regulator_is_enabled_regmap,
538 .enable = regulator_enable_regmap,
539 .disable = regulator_disable_regmap,
e5ce4208
GG		 540 .set_mode = palmas_set_mode_smps,
541 .get_mode = palmas_get_mode_smps,
bdc4baac
AL		 542 .get_voltage_sel = regulator_get_voltage_sel_regmap,
543 .set_voltage_sel = regulator_set_voltage_sel_regmap,
dbabd624
K		 544 .list_voltage = regulator_list_voltage_linear_range,
545 .map_voltage = regulator_map_voltage_linear_range,
546 .set_voltage_time_sel = regulator_set_voltage_time_sel,
28d1e8cd 547 .set_ramp_delay = palmas_smps_set_ramp_delay,
e5ce4208
GG		 548};
549
0e5a7680 550static const struct regulator_ops palmas_ops_ext_control_smps = {
32b6d3f6
LD		 551 .set_mode = palmas_set_mode_smps,
552 .get_mode = palmas_get_mode_smps,
553 .get_voltage_sel = regulator_get_voltage_sel_regmap,
554 .set_voltage_sel = regulator_set_voltage_sel_regmap,
dbabd624
K		 555 .list_voltage = regulator_list_voltage_linear_range,
556 .map_voltage = regulator_map_voltage_linear_range,
557 .set_voltage_time_sel = regulator_set_voltage_time_sel,
32b6d3f6
LD		 558 .set_ramp_delay = palmas_smps_set_ramp_delay,
559};
560
0e5a7680 561static const struct regulator_ops palmas_ops_smps10 = {
e5ce4208
GG		 562 .is_enabled = regulator_is_enabled_regmap,
563 .enable = regulator_enable_regmap,
564 .disable = regulator_disable_regmap,
565 .get_voltage_sel = regulator_get_voltage_sel_regmap,
566 .set_voltage_sel = regulator_set_voltage_sel_regmap,
8029a006
AL		 567 .list_voltage = regulator_list_voltage_linear,
568 .map_voltage = regulator_map_voltage_linear,
77409d9b
KVA		 569 .set_bypass = regulator_set_bypass_regmap,
570 .get_bypass = regulator_get_bypass_regmap,
e5ce4208
GG		 571};
572
0e5a7680 573static const struct regulator_ops tps65917_ops_smps = {
d6f83370
K		 574 .is_enabled = regulator_is_enabled_regmap,
575 .enable = regulator_enable_regmap,
576 .disable = regulator_disable_regmap,
577 .set_mode = palmas_set_mode_smps,
578 .get_mode = palmas_get_mode_smps,
579 .get_voltage_sel = regulator_get_voltage_sel_regmap,
580 .set_voltage_sel = regulator_set_voltage_sel_regmap,
581 .list_voltage = regulator_list_voltage_linear_range,
582 .map_voltage = regulator_map_voltage_linear_range,
583 .set_voltage_time_sel = regulator_set_voltage_time_sel,
584};
585
0e5a7680 586static const struct regulator_ops tps65917_ops_ext_control_smps = {
d6f83370
K		 587 .set_mode = palmas_set_mode_smps,
588 .get_mode = palmas_get_mode_smps,
589 .get_voltage_sel = regulator_get_voltage_sel_regmap,
590 .set_voltage_sel = regulator_set_voltage_sel_regmap,
591 .list_voltage = regulator_list_voltage_linear_range,
592 .map_voltage = regulator_map_voltage_linear_range,
593};
594
e5ce4208
GG		 595static int palmas_is_enabled_ldo(struct regulator_dev *dev)
596{
cf910b6b 597 int id = rdev_get_id(dev);
e5ce4208 598 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
cac9e916 599 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
cf910b6b 600 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
e5ce4208
GG		 601 unsigned int reg;
602
cf910b6b 603 palmas_ldo_read(pmic->palmas, rinfo->ctrl_addr, &reg);
e5ce4208
GG		 604
605 reg &= PALMAS_LDO1_CTRL_STATUS;
606
607 return !!(reg);
608}
609
0e5a7680 610static const struct regulator_ops palmas_ops_ldo = {
e5ce4208
GG		 611 .is_enabled = palmas_is_enabled_ldo,
612 .enable = regulator_enable_regmap,
613 .disable = regulator_disable_regmap,
4a247a96
AL		 614 .get_voltage_sel = regulator_get_voltage_sel_regmap,
615 .set_voltage_sel = regulator_set_voltage_sel_regmap,
9119ff6a
AL		 616 .list_voltage = regulator_list_voltage_linear,
617 .map_voltage = regulator_map_voltage_linear,
e5ce4208
GG		 618};
619
0e5a7680 620static const struct regulator_ops palmas_ops_ldo9 = {
b554e145
K		 621 .is_enabled = palmas_is_enabled_ldo,
622 .enable = regulator_enable_regmap,
623 .disable = regulator_disable_regmap,
624 .get_voltage_sel = regulator_get_voltage_sel_regmap,
625 .set_voltage_sel = regulator_set_voltage_sel_regmap,
626 .list_voltage = regulator_list_voltage_linear,
627 .map_voltage = regulator_map_voltage_linear,
628 .set_bypass = regulator_set_bypass_regmap,
629 .get_bypass = regulator_get_bypass_regmap,
630};
631
0e5a7680 632static const struct regulator_ops palmas_ops_ext_control_ldo = {
32b6d3f6
LD		 633 .get_voltage_sel = regulator_get_voltage_sel_regmap,
634 .set_voltage_sel = regulator_set_voltage_sel_regmap,
635 .list_voltage = regulator_list_voltage_linear,
636 .map_voltage = regulator_map_voltage_linear,
637};
638
0e5a7680 639static const struct regulator_ops palmas_ops_extreg = {
aa07f027
LD		 640 .is_enabled = regulator_is_enabled_regmap,
641 .enable = regulator_enable_regmap,
642 .disable = regulator_disable_regmap,
643};
644
0e5a7680 645static const struct regulator_ops palmas_ops_ext_control_extreg = {
32b6d3f6
LD		 646};
647
0e5a7680 648static const struct regulator_ops tps65917_ops_ldo = {
d6f83370
K		 649 .is_enabled = palmas_is_enabled_ldo,
650 .enable = regulator_enable_regmap,
651 .disable = regulator_disable_regmap,
652 .get_voltage_sel = regulator_get_voltage_sel_regmap,
653 .set_voltage_sel = regulator_set_voltage_sel_regmap,
654 .list_voltage = regulator_list_voltage_linear,
655 .map_voltage = regulator_map_voltage_linear,
656 .set_voltage_time_sel = regulator_set_voltage_time_sel,
657};
658
0e5a7680 659static const struct regulator_ops tps65917_ops_ldo_1_2 = {
b554e145
K		 660 .is_enabled = palmas_is_enabled_ldo,
661 .enable = regulator_enable_regmap,
662 .disable = regulator_disable_regmap,
663 .get_voltage_sel = regulator_get_voltage_sel_regmap,
664 .set_voltage_sel = regulator_set_voltage_sel_regmap,
665 .list_voltage = regulator_list_voltage_linear,
666 .map_voltage = regulator_map_voltage_linear,
667 .set_voltage_time_sel = regulator_set_voltage_time_sel,
668 .set_bypass = regulator_set_bypass_regmap,
669 .get_bypass = regulator_get_bypass_regmap,
670};
671
32b6d3f6
LD		 672static int palmas_regulator_config_external(struct palmas *palmas, int id,
673 struct palmas_reg_init *reg_init)
674{
cf910b6b
NM		 675 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
676 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
32b6d3f6
LD		 677 int ret;
678
cf910b6b
NM		 679 ret = palmas_ext_control_req_config(palmas, rinfo->sleep_id,
680 reg_init->roof_floor, true);
32b6d3f6
LD		 681 if (ret < 0)
682 dev_err(palmas->dev,
683 "Ext control config for regulator %d failed %d\n",
684 id, ret);
685 return ret;
686}
687
e5ce4208
GG		 688/*
689 * setup the hardware based sleep configuration of the SMPS/LDO regulators
690 * from the platform data. This is different to the software based control
691 * supported by the regulator framework as it is controlled by toggling
692 * pins on the PMIC such as PREQ, SYSEN, ...
693 */
694static int palmas_smps_init(struct palmas *palmas, int id,
695 struct palmas_reg_init *reg_init)
696{
697 unsigned int reg;
e5ce4208 698 int ret;
cac9e916 699 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
cf910b6b
NM		 700 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
701 unsigned int addr = rinfo->ctrl_addr;
e5ce4208
GG		 702
703 ret = palmas_smps_read(palmas, addr, &reg);
704 if (ret)
705 return ret;
706
fedd89b1 707 switch (id) {
77409d9b
KVA		 708 case PALMAS_REG_SMPS10_OUT1:
709 case PALMAS_REG_SMPS10_OUT2:
30590d04
LD		 710 reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK;
711 if (reg_init->mode_sleep)
fedd89b1
AL		 712 reg |= reg_init->mode_sleep <<
713 PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT;
fedd89b1
AL		 714 break;
715 default:
e5ce4208
GG		 716 if (reg_init->warm_reset)
717 reg |= PALMAS_SMPS12_CTRL_WR_S;
30590d04
LD		 718 else
719 reg &= ~PALMAS_SMPS12_CTRL_WR_S;
e5ce4208
GG		 720
721 if (reg_init->roof_floor)
722 reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
30590d04
LD		 723 else
724 reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
e5ce4208 725
30590d04
LD		 726 reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK;
727 if (reg_init->mode_sleep)
e5ce4208
GG		 728 reg |= reg_init->mode_sleep <<
729 PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT;
e5ce4208 730 }
fedd89b1 731
e5ce4208
GG		 732 ret = palmas_smps_write(palmas, addr, reg);
733 if (ret)
734 return ret;
735
cf910b6b 736 if (rinfo->vsel_addr && reg_init->vsel) {
e5ce4208
GG		 737
738 reg = reg_init->vsel;
739
cf910b6b 740 ret = palmas_smps_write(palmas, rinfo->vsel_addr, reg);
e5ce4208
GG		 741 if (ret)
742 return ret;
743 }
744
32b6d3f6
LD		 745 if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) &&
746 (id != PALMAS_REG_SMPS10_OUT2)) {
747 /* Enable externally controlled regulator */
32b6d3f6
LD		 748 ret = palmas_smps_read(palmas, addr, &reg);
749 if (ret < 0)
750 return ret;
e5ce4208 751
32b6d3f6
LD		 752 if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) {
753 reg |= SMPS_CTRL_MODE_ON;
754 ret = palmas_smps_write(palmas, addr, reg);
755 if (ret < 0)
756 return ret;
757 }
758 return palmas_regulator_config_external(palmas, id, reg_init);
759 }
e5ce4208
GG		 760 return 0;
761}
762
763static int palmas_ldo_init(struct palmas *palmas, int id,
764 struct palmas_reg_init *reg_init)
765{
766 unsigned int reg;
767 unsigned int addr;
768 int ret;
cac9e916 769 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
cf910b6b 770 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
cac9e916 771
cf910b6b 772 addr = rinfo->ctrl_addr;
e5ce4208 773
2735daeb 774 ret = palmas_ldo_read(palmas, addr, &reg);
e5ce4208
GG		 775 if (ret)
776 return ret;
777
778 if (reg_init->warm_reset)
779 reg |= PALMAS_LDO1_CTRL_WR_S;
30590d04
LD		 780 else
781 reg &= ~PALMAS_LDO1_CTRL_WR_S;
e5ce4208
GG		 782
783 if (reg_init->mode_sleep)
784 reg |= PALMAS_LDO1_CTRL_MODE_SLEEP;
30590d04
LD		 785 else
786 reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP;
e5ce4208 787
2735daeb 788 ret = palmas_ldo_write(palmas, addr, reg);
e5ce4208
GG		 789 if (ret)
790 return ret;
791
32b6d3f6
LD		 792 if (reg_init->roof_floor) {
793 /* Enable externally controlled regulator */
32b6d3f6
LD		 794 ret = palmas_update_bits(palmas, PALMAS_LDO_BASE,
795 addr, PALMAS_LDO1_CTRL_MODE_ACTIVE,
796 PALMAS_LDO1_CTRL_MODE_ACTIVE);
797 if (ret < 0) {
798 dev_err(palmas->dev,
799 "LDO Register 0x%02x update failed %d\n",
800 addr, ret);
801 return ret;
802 }
803 return palmas_regulator_config_external(palmas, id, reg_init);
804 }
e5ce4208
GG		 805 return 0;
806}
807
aa07f027
LD		 808static int palmas_extreg_init(struct palmas *palmas, int id,
809 struct palmas_reg_init *reg_init)
810{
811 unsigned int addr;
812 int ret;
813 unsigned int val = 0;
cac9e916 814 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
cf910b6b 815 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
cac9e916 816
cf910b6b 817 addr = rinfo->ctrl_addr;
aa07f027
LD		 818
819 if (reg_init->mode_sleep)
820 val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
821
822 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
823 addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val);
824 if (ret < 0) {
825 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
826 addr, ret);
827 return ret;
828 }
32b6d3f6
LD		 829
830 if (reg_init->roof_floor) {
831 /* Enable externally controlled regulator */
32b6d3f6
LD		 832 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
833 addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE,
834 PALMAS_REGEN1_CTRL_MODE_ACTIVE);
835 if (ret < 0) {
836 dev_err(palmas->dev,
837 "Resource Register 0x%02x update failed %d\n",
838 addr, ret);
839 return ret;
840 }
841 return palmas_regulator_config_external(palmas, id, reg_init);
842 }
aa07f027
LD		 843 return 0;
844}
845
17c11a76
LD		 846static void palmas_enable_ldo8_track(struct palmas *palmas)
847{
848 unsigned int reg;
849 unsigned int addr;
850 int ret;
cac9e916 851 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
cf910b6b 852 struct palmas_regs_info *rinfo;
cac9e916 853
cf910b6b
NM		 854 rinfo = &ddata->palmas_regs_info[PALMAS_REG_LDO8];
855 addr = rinfo->ctrl_addr;
17c11a76
LD		 856
857 ret = palmas_ldo_read(palmas, addr, &reg);
858 if (ret) {
859 dev_err(palmas->dev, "Error in reading ldo8 control reg\n");
860 return;
861 }
862
863 reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN;
864 ret = palmas_ldo_write(palmas, addr, reg);
865 if (ret < 0) {
866 dev_err(palmas->dev, "Error in enabling tracking mode\n");
867 return;
868 }
869 /*
870 * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8
871 * output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
872 * and can be set from 0.45 to 1.65 V.
873 */
cf910b6b 874 addr = rinfo->vsel_addr;
17c11a76
LD		 875 ret = palmas_ldo_read(palmas, addr, &reg);
876 if (ret) {
877 dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
878 return;
879 }
880
881 reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK;
882 ret = palmas_ldo_write(palmas, addr, reg);
883 if (ret < 0)
884 dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n");
885
886 return;
887}
888
cac9e916
K		 889static int palmas_ldo_registration(struct palmas_pmic *pmic,
890 struct palmas_pmic_driver_data *ddata,
891 struct palmas_pmic_platform_data *pdata,
892 const char *pdev_name,
893 struct regulator_config config)
a361cd9f 894{
cac9e916
K		 895 int id, ret;
896 struct regulator_dev *rdev;
897 struct palmas_reg_init *reg_init;
cf910b6b 898 struct palmas_regs_info *rinfo;
429222d0 899 struct regulator_desc *desc;
a361cd9f 900
cac9e916
K		 901 for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
902 if (pdata && pdata->reg_init[id])
903 reg_init = pdata->reg_init[id];
904 else
905 reg_init = NULL;
a361cd9f 906
cf910b6b 907 rinfo = &ddata->palmas_regs_info[id];
cac9e916
K		 908 /* Miss out regulators which are not available due
909 * to alternate functions.
910 */
a361cd9f 911
cac9e916 912 /* Register the regulators */
429222d0
NM		 913 desc = &pmic->desc[id];
914 desc->name = rinfo->name;
915 desc->id = id;
916 desc->type = REGULATOR_VOLTAGE;
917 desc->owner = THIS_MODULE;
a361cd9f 918
cac9e916 919 if (id < PALMAS_REG_REGEN1) {
429222d0 920 desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
cac9e916 921 if (reg_init && reg_init->roof_floor)
429222d0 922 desc->ops = &palmas_ops_ext_control_ldo;
cac9e916 923 else
429222d0
NM		 924 desc->ops = &palmas_ops_ldo;
925 desc->min_uV = 900000;
926 desc->uV_step = 50000;
927 desc->linear_min_sel = 1;
928 desc->enable_time = 500;
929 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
930 rinfo->vsel_addr);
931 desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
932 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
933 rinfo->ctrl_addr);
934 desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
a361cd9f 935
cac9e916
K		 936 /* Check if LDO8 is in tracking mode or not */
937 if (pdata && (id == PALMAS_REG_LDO8) &&
938 pdata->enable_ldo8_tracking) {
939 palmas_enable_ldo8_track(pmic->palmas);
429222d0
NM		 940 desc->min_uV = 450000;
941 desc->uV_step = 25000;
cac9e916 942 }
a361cd9f 943
cac9e916
K		 944 /* LOD6 in vibrator mode will have enable time 2000us */
945 if (pdata && pdata->ldo6_vibrator &&
946 (id == PALMAS_REG_LDO6))
429222d0 947 desc->enable_time = 2000;
b554e145
K		 948
949 if (id == PALMAS_REG_LDO9) {
950 desc->ops = &palmas_ops_ldo9;
951 desc->bypass_reg = desc->enable_reg;
e0341f17
NM		 952 desc->bypass_val_on =
953 PALMAS_LDO9_CTRL_LDO_BYPASS_EN;
b554e145
K		 954 desc->bypass_mask =
955 PALMAS_LDO9_CTRL_LDO_BYPASS_EN;
956 }
cac9e916 957 } else {
e999c728
K		 958 if (!ddata->has_regen3 && id == PALMAS_REG_REGEN3)
959 continue;
960
429222d0 961 desc->n_voltages = 1;
cac9e916 962 if (reg_init && reg_init->roof_floor)
429222d0 963 desc->ops = &palmas_ops_ext_control_extreg;
cac9e916 964 else
429222d0
NM		 965 desc->ops = &palmas_ops_extreg;
966 desc->enable_reg =
cac9e916 967 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
cf910b6b 968 rinfo->ctrl_addr);
429222d0 969 desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
cac9e916 970 }
a361cd9f 971
cac9e916
K		 972 if (pdata)
973 config.init_data = pdata->reg_data[id];
974 else
975 config.init_data = NULL;
32b6d3f6 976
429222d0 977 desc->supply_name = rinfo->sname;
cac9e916 978 config.of_node = ddata->palmas_matches[id].of_node;
a361cd9f 979
429222d0 980 rdev = devm_regulator_register(pmic->dev, desc, &config);
cac9e916
K		 981 if (IS_ERR(rdev)) {
982 dev_err(pmic->dev,
983 "failed to register %s regulator\n",
984 pdev_name);
985 return PTR_ERR(rdev);
986 }
a361cd9f 987
cac9e916
K		 988 /* Initialise sleep/init values from platform data */
989 if (pdata) {
990 reg_init = pdata->reg_init[id];
991 if (reg_init) {
992 if (id <= ddata->ldo_end)
993 ret = palmas_ldo_init(pmic->palmas, id,
994 reg_init);
995 else
996 ret = palmas_extreg_init(pmic->palmas,
997 id, reg_init);
998 if (ret)
999 return ret;
1000 }
1001 }
a361cd9f
GG		 1002 }
1003
cac9e916 1004 return 0;
a361cd9f
GG		 1005}
1006
d6f83370
K		 1007static int tps65917_ldo_registration(struct palmas_pmic *pmic,
1008 struct palmas_pmic_driver_data *ddata,
1009 struct palmas_pmic_platform_data *pdata,
1010 const char *pdev_name,
1011 struct regulator_config config)
1012{
1013 int id, ret;
1014 struct regulator_dev *rdev;
1015 struct palmas_reg_init *reg_init;
cf910b6b 1016 struct palmas_regs_info *rinfo;
429222d0 1017 struct regulator_desc *desc;
d6f83370
K		 1018
1019 for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
1020 if (pdata && pdata->reg_init[id])
1021 reg_init = pdata->reg_init[id];
1022 else
1023 reg_init = NULL;
1024
1025 /* Miss out regulators which are not available due
1026 * to alternate functions.
1027 */
cf910b6b 1028 rinfo = &ddata->palmas_regs_info[id];
d6f83370
K		 1029
1030 /* Register the regulators */
429222d0
NM		 1031 desc = &pmic->desc[id];
1032 desc->name = rinfo->name;
1033 desc->id = id;
1034 desc->type = REGULATOR_VOLTAGE;
1035 desc->owner = THIS_MODULE;
d6f83370
K		 1036
1037 if (id < TPS65917_REG_REGEN1) {
429222d0 1038 desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
d6f83370 1039 if (reg_init && reg_init->roof_floor)
429222d0 1040 desc->ops = &palmas_ops_ext_control_ldo;
d6f83370 1041 else
429222d0
NM		 1042 desc->ops = &tps65917_ops_ldo;
1043 desc->min_uV = 900000;
1044 desc->uV_step = 50000;
1045 desc->linear_min_sel = 1;
1046 desc->enable_time = 500;
1047 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1048 rinfo->vsel_addr);
1049 desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
1050 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1051 rinfo->ctrl_addr);
1052 desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
d6f83370
K		 1053 /*
1054 * To be confirmed. Discussion on going with PMIC Team.
1055 * It is of the order of ~60mV/uS.
1056 */
429222d0 1057 desc->ramp_delay = 2500;
b554e145
K		 1058 if (id == TPS65917_REG_LDO1 ||
1059 id == TPS65917_REG_LDO2) {
1060 desc->ops = &tps65917_ops_ldo_1_2;
1061 desc->bypass_reg = desc->enable_reg;
e0341f17
NM		 1062 desc->bypass_val_on =
1063 TPS65917_LDO1_CTRL_BYPASS_EN;
b554e145
K		 1064 desc->bypass_mask =
1065 TPS65917_LDO1_CTRL_BYPASS_EN;
1066 }
d6f83370 1067 } else {
429222d0 1068 desc->n_voltages = 1;
d6f83370 1069 if (reg_init && reg_init->roof_floor)
429222d0 1070 desc->ops = &palmas_ops_ext_control_extreg;
d6f83370 1071 else
429222d0
NM		 1072 desc->ops = &palmas_ops_extreg;
1073 desc->enable_reg =
d6f83370 1074 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
cf910b6b 1075 rinfo->ctrl_addr);
429222d0 1076 desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
d6f83370
K		 1077 }
1078
1079 if (pdata)
1080 config.init_data = pdata->reg_data[id];
1081 else
1082 config.init_data = NULL;
1083
429222d0 1084 desc->supply_name = rinfo->sname;
d6f83370
K		 1085 config.of_node = ddata->palmas_matches[id].of_node;
1086
429222d0 1087 rdev = devm_regulator_register(pmic->dev, desc, &config);
d6f83370
K		 1088 if (IS_ERR(rdev)) {
1089 dev_err(pmic->dev,
1090 "failed to register %s regulator\n",
1091 pdev_name);
1092 return PTR_ERR(rdev);
1093 }
1094
d6f83370
K		 1095 /* Initialise sleep/init values from platform data */
1096 if (pdata) {
1097 reg_init = pdata->reg_init[id];
1098 if (reg_init) {
1099 if (id < TPS65917_REG_REGEN1)
1100 ret = palmas_ldo_init(pmic->palmas,
1101 id, reg_init);
1102 else
1103 ret = palmas_extreg_init(pmic->palmas,
1104 id, reg_init);
1105 if (ret)
1106 return ret;
1107 }
1108 }
1109 }
1110
1111 return 0;
1112}
1113
cac9e916
K		 1114static int palmas_smps_registration(struct palmas_pmic *pmic,
1115 struct palmas_pmic_driver_data *ddata,
1116 struct palmas_pmic_platform_data *pdata,
1117 const char *pdev_name,
1118 struct regulator_config config)
e5ce4208 1119{
cac9e916
K		 1120 int id, ret;
1121 unsigned int addr, reg;
e5ce4208 1122 struct regulator_dev *rdev;
e5ce4208 1123 struct palmas_reg_init *reg_init;
cf910b6b 1124 struct palmas_regs_info *rinfo;
429222d0 1125 struct regulator_desc *desc;
e5ce4208 1126
cac9e916 1127 for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
28d1e8cd 1128 bool ramp_delay_support = false;
e5ce4208
GG		 1129
1130 /*
1131 * Miss out regulators which are not available due
1132 * to slaving configurations.
1133 */
1134 switch (id) {
1135 case PALMAS_REG_SMPS12:
1136 case PALMAS_REG_SMPS3:
1137 if (pmic->smps123)
1138 continue;
28d1e8cd
LD		 1139 if (id == PALMAS_REG_SMPS12)
1140 ramp_delay_support = true;
e5ce4208
GG		 1141 break;
1142 case PALMAS_REG_SMPS123:
1143 if (!pmic->smps123)
1144 continue;
28d1e8cd 1145 ramp_delay_support = true;
e5ce4208
GG		 1146 break;
1147 case PALMAS_REG_SMPS45:
1148 case PALMAS_REG_SMPS7:
1149 if (pmic->smps457)
1150 continue;
28d1e8cd
LD		 1151 if (id == PALMAS_REG_SMPS45)
1152 ramp_delay_support = true;
e5ce4208
GG		 1153 break;
1154 case PALMAS_REG_SMPS457:
1155 if (!pmic->smps457)
1156 continue;
28d1e8cd
LD		 1157 ramp_delay_support = true;
1158 break;
77409d9b
KVA		 1159 case PALMAS_REG_SMPS10_OUT1:
1160 case PALMAS_REG_SMPS10_OUT2:
cac9e916 1161 if (!PALMAS_PMIC_HAS(pmic->palmas, SMPS10_BOOST))
1ffb0be3 1162 continue;
28d1e8cd 1163 }
cf910b6b 1164 rinfo = &ddata->palmas_regs_info[id];
429222d0 1165 desc = &pmic->desc[id];
28d1e8cd 1166
3f4d6364 1167 if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
28d1e8cd
LD		 1168 ramp_delay_support = true;
1169
1170 if (ramp_delay_support) {
cf910b6b 1171 addr = rinfo->tstep_addr;
28d1e8cd
LD		 1172 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1173 if (ret < 0) {
cac9e916 1174 dev_err(pmic->dev,
28d1e8cd 1175 "reading TSTEP reg failed: %d\n", ret);
51c86b3e 1176 return ret;
28d1e8cd 1177 }
429222d0
NM		 1178 desc->ramp_delay = palmas_smps_ramp_delay[reg & 0x3];
1179 pmic->ramp_delay[id] = desc->ramp_delay;
e5ce4208
GG		 1180 }
1181
bdc4baac
AL		 1182 /* Initialise sleep/init values from platform data */
1183 if (pdata && pdata->reg_init[id]) {
1184 reg_init = pdata->reg_init[id];
cac9e916 1185 ret = palmas_smps_init(pmic->palmas, id, reg_init);
bdc4baac 1186 if (ret)
51c86b3e 1187 return ret;
32b6d3f6
LD		 1188 } else {
1189 reg_init = NULL;
bdc4baac
AL		 1190 }
1191
e5ce4208 1192 /* Register the regulators */
429222d0
NM		 1193 desc->name = rinfo->name;
1194 desc->id = id;
e5ce4208 1195
fedd89b1 1196 switch (id) {
77409d9b
KVA		 1197 case PALMAS_REG_SMPS10_OUT1:
1198 case PALMAS_REG_SMPS10_OUT2:
429222d0
NM		 1199 desc->n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
1200 desc->ops = &palmas_ops_smps10;
1201 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1202 PALMAS_SMPS10_CTRL);
1203 desc->vsel_mask = SMPS10_VSEL;
1204 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1205 PALMAS_SMPS10_CTRL);
77409d9b 1206 if (id == PALMAS_REG_SMPS10_OUT1)
429222d0 1207 desc->enable_mask = SMPS10_SWITCH_EN;
77409d9b 1208 else
429222d0
NM		 1209 desc->enable_mask = SMPS10_BOOST_EN;
1210 desc->bypass_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1211 PALMAS_SMPS10_CTRL);
e0341f17 1212 desc->bypass_val_on = SMPS10_BYPASS_EN;
429222d0
NM		 1213 desc->bypass_mask = SMPS10_BYPASS_EN;
1214 desc->min_uV = 3750000;
1215 desc->uV_step = 1250000;
fedd89b1
AL		 1216 break;
1217 default:
bdc4baac
AL		 1218 /*
1219 * Read and store the RANGE bit for later use
1220 * This must be done before regulator is probed,
51d3a0c9
LD		 1221 * otherwise we error in probe with unsupportable
1222 * ranges. Read the current smps mode for later use.
bdc4baac 1223 */
cf910b6b 1224 addr = rinfo->vsel_addr;
429222d0 1225 desc->n_linear_ranges = 3;
e5ce4208
GG		 1226
1227 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1228 if (ret)
51c86b3e 1229 return ret;
e5ce4208
GG		 1230 if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
1231 pmic->range[id] = 1;
dbabd624 1232 if (pmic->range[id])
429222d0 1233 desc->linear_ranges = smps_high_ranges;
dbabd624 1234 else
429222d0 1235 desc->linear_ranges = smps_low_ranges;
bdc4baac 1236
32b6d3f6 1237 if (reg_init && reg_init->roof_floor)
429222d0 1238 desc->ops = &palmas_ops_ext_control_smps;
32b6d3f6 1239 else
429222d0
NM		 1240 desc->ops = &palmas_ops_smps;
1241 desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1242 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1243 rinfo->vsel_addr);
1244 desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
51d3a0c9
LD		 1245
1246 /* Read the smps mode for later use. */
cf910b6b 1247 addr = rinfo->ctrl_addr;
51d3a0c9
LD		 1248 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1249 if (ret)
51c86b3e 1250 return ret;
51d3a0c9
LD		 1251 pmic->current_reg_mode[id] = reg &
1252 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
318dbb02 1253
429222d0
NM		 1254 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1255 rinfo->ctrl_addr);
1256 desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
318dbb02 1257 /* set_mode overrides this value */
429222d0 1258 desc->enable_val = SMPS_CTRL_MODE_ON;
e5ce4208
GG		 1259 }
1260
429222d0
NM		 1261 desc->type = REGULATOR_VOLTAGE;
1262 desc->owner = THIS_MODULE;
bdc4baac 1263
a361cd9f 1264 if (pdata)
e5ce4208
GG		 1265 config.init_data = pdata->reg_data[id];
1266 else
1267 config.init_data = NULL;
1268
429222d0 1269 desc->supply_name = rinfo->sname;
cac9e916 1270 config.of_node = ddata->palmas_matches[id].of_node;
a361cd9f 1271
429222d0 1272 rdev = devm_regulator_register(pmic->dev, desc, &config);
e5ce4208 1273 if (IS_ERR(rdev)) {
cac9e916 1274 dev_err(pmic->dev,
e5ce4208 1275 "failed to register %s regulator\n",
cac9e916 1276 pdev_name);
51c86b3e 1277 return PTR_ERR(rdev);
e5ce4208 1278 }
e5ce4208
GG		 1279 }
1280
cac9e916
K		 1281 return 0;
1282}
e5ce4208 1283
d6f83370
K		 1284static int tps65917_smps_registration(struct palmas_pmic *pmic,
1285 struct palmas_pmic_driver_data *ddata,
1286 struct palmas_pmic_platform_data *pdata,
1287 const char *pdev_name,
1288 struct regulator_config config)
1289{
1290 int id, ret;
1291 unsigned int addr, reg;
1292 struct regulator_dev *rdev;
1293 struct palmas_reg_init *reg_init;
cf910b6b 1294 struct palmas_regs_info *rinfo;
429222d0 1295 struct regulator_desc *desc;
d6f83370
K		 1296
1297 for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
1298 /*
1299 * Miss out regulators which are not available due
1300 * to slaving configurations.
1301 */
429222d0
NM		 1302 desc = &pmic->desc[id];
1303 desc->n_linear_ranges = 3;
be035303
K		 1304 if ((id == TPS65917_REG_SMPS2 || id == TPS65917_REG_SMPS1) &&
1305 pmic->smps12)
d6f83370
K		 1306 continue;
1307
1308 /* Initialise sleep/init values from platform data */
1309 if (pdata && pdata->reg_init[id]) {
1310 reg_init = pdata->reg_init[id];
1311 ret = palmas_smps_init(pmic->palmas, id, reg_init);
1312 if (ret)
1313 return ret;
1314 } else {
1315 reg_init = NULL;
1316 }
cf910b6b 1317 rinfo = &ddata->palmas_regs_info[id];
d6f83370
K		 1318
1319 /* Register the regulators */
429222d0
NM		 1320 desc->name = rinfo->name;
1321 desc->id = id;
d6f83370
K		 1322
1323 /*
1324 * Read and store the RANGE bit for later use
1325 * This must be done before regulator is probed,
1326 * otherwise we error in probe with unsupportable
1327 * ranges. Read the current smps mode for later use.
1328 */
cf910b6b 1329 addr = rinfo->vsel_addr;
d6f83370
K		 1330
1331 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1332 if (ret)
1333 return ret;
1334 if (reg & TPS65917_SMPS1_VOLTAGE_RANGE)
1335 pmic->range[id] = 1;
1336
1337 if (pmic->range[id])
429222d0
NM		 1338 desc->linear_ranges = smps_high_ranges;
1339 else
1340 desc->linear_ranges = smps_low_ranges;
d6f83370
K		 1341
1342 if (reg_init && reg_init->roof_floor)
429222d0 1343 desc->ops = &tps65917_ops_ext_control_smps;
d6f83370 1344 else
429222d0
NM		 1345 desc->ops = &tps65917_ops_smps;
1346 desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1347 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1348 rinfo->vsel_addr);
1349 desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
1350 desc->ramp_delay = 2500;
d6f83370
K		 1351
1352 /* Read the smps mode for later use. */
cf910b6b 1353 addr = rinfo->ctrl_addr;
d6f83370
K		 1354 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1355 if (ret)
1356 return ret;
1357 pmic->current_reg_mode[id] = reg &
1358 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
b632815e
NM		 1359 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1360 rinfo->ctrl_addr);
1361 desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
1362 /* set_mode overrides this value */
1363 desc->enable_val = SMPS_CTRL_MODE_ON;
d6f83370 1364
429222d0
NM		 1365 desc->type = REGULATOR_VOLTAGE;
1366 desc->owner = THIS_MODULE;
d6f83370
K		 1367
1368 if (pdata)
1369 config.init_data = pdata->reg_data[id];
1370 else
1371 config.init_data = NULL;
1372
429222d0 1373 desc->supply_name = rinfo->sname;
d6f83370
K		 1374 config.of_node = ddata->palmas_matches[id].of_node;
1375
429222d0 1376 rdev = devm_regulator_register(pmic->dev, desc, &config);
d6f83370
K		 1377 if (IS_ERR(rdev)) {
1378 dev_err(pmic->dev,
1379 "failed to register %s regulator\n",
1380 pdev_name);
1381 return PTR_ERR(rdev);
1382 }
d6f83370
K		 1383 }
1384
1385 return 0;
1386}
1387
cac9e916
K		 1388static struct of_regulator_match palmas_matches[] = {
1389 { .name = "smps12", },
1390 { .name = "smps123", },
1391 { .name = "smps3", },
1392 { .name = "smps45", },
1393 { .name = "smps457", },
1394 { .name = "smps6", },
1395 { .name = "smps7", },
1396 { .name = "smps8", },
1397 { .name = "smps9", },
1398 { .name = "smps10_out2", },
1399 { .name = "smps10_out1", },
1400 { .name = "ldo1", },
1401 { .name = "ldo2", },
1402 { .name = "ldo3", },
1403 { .name = "ldo4", },
1404 { .name = "ldo5", },
1405 { .name = "ldo6", },
1406 { .name = "ldo7", },
1407 { .name = "ldo8", },
1408 { .name = "ldo9", },
1409 { .name = "ldoln", },
1410 { .name = "ldousb", },
1411 { .name = "regen1", },
1412 { .name = "regen2", },
1413 { .name = "regen3", },
1414 { .name = "sysen1", },
1415 { .name = "sysen2", },
1416};
e5ce4208 1417
d6f83370
K		 1418static struct of_regulator_match tps65917_matches[] = {
1419 { .name = "smps1", },
1420 { .name = "smps2", },
1421 { .name = "smps3", },
1422 { .name = "smps4", },
1423 { .name = "smps5", },
be035303 1424 { .name = "smps12",},
d6f83370
K		 1425 { .name = "ldo1", },
1426 { .name = "ldo2", },
1427 { .name = "ldo3", },
1428 { .name = "ldo4", },
1429 { .name = "ldo5", },
1430 { .name = "regen1", },
1431 { .name = "regen2", },
1432 { .name = "regen3", },
1433 { .name = "sysen1", },
1434 { .name = "sysen2", },
1435};
1436
4b09e17b 1437static struct palmas_pmic_driver_data palmas_ddata = {
cac9e916
K		 1438 .smps_start = PALMAS_REG_SMPS12,
1439 .smps_end = PALMAS_REG_SMPS10_OUT1,
1440 .ldo_begin = PALMAS_REG_LDO1,
1441 .ldo_end = PALMAS_REG_LDOUSB,
1442 .max_reg = PALMAS_NUM_REGS,
e999c728 1443 .has_regen3 = true,
6839cd6f 1444 .palmas_regs_info = palmas_generic_regs_info,
cac9e916
K		 1445 .palmas_matches = palmas_matches,
1446 .sleep_req_info = palma_sleep_req_info,
1447 .smps_register = palmas_smps_registration,
1448 .ldo_register = palmas_ldo_registration,
1449};
aa07f027 1450
4b09e17b 1451static struct palmas_pmic_driver_data tps65917_ddata = {
d6f83370 1452 .smps_start = TPS65917_REG_SMPS1,
be035303 1453 .smps_end = TPS65917_REG_SMPS12,
d6f83370
K		 1454 .ldo_begin = TPS65917_REG_LDO1,
1455 .ldo_end = TPS65917_REG_LDO5,
1456 .max_reg = TPS65917_NUM_REGS,
e999c728 1457 .has_regen3 = true,
d6f83370
K		 1458 .palmas_regs_info = tps65917_regs_info,
1459 .palmas_matches = tps65917_matches,
1460 .sleep_req_info = tps65917_sleep_req_info,
1461 .smps_register = tps65917_smps_registration,
1462 .ldo_register = tps65917_ldo_registration,
1463};
1464
7f091e53
NM		 1465static int palmas_dt_to_pdata(struct device *dev,
1466 struct device_node *node,
1467 struct palmas_pmic_platform_data *pdata,
1468 struct palmas_pmic_driver_data *ddata)
cac9e916
K		 1469{
1470 struct device_node *regulators;
1471 u32 prop;
1472 int idx, ret;
17c11a76 1473
cac9e916
K		 1474 regulators = of_get_child_by_name(node, "regulators");
1475 if (!regulators) {
1476 dev_info(dev, "regulator node not found\n");
7f091e53 1477 return 0;
cac9e916 1478 }
087d30e3 1479
cac9e916
K		 1480 ret = of_regulator_match(dev, regulators, ddata->palmas_matches,
1481 ddata->max_reg);
1482 of_node_put(regulators);
1483 if (ret < 0) {
1484 dev_err(dev, "Error parsing regulator init data: %d\n", ret);
7f091e53 1485 return 0;
cac9e916 1486 }
e5ce4208 1487
cac9e916 1488 for (idx = 0; idx < ddata->max_reg; idx++) {
96e4f523 1489 struct of_regulator_match *match;
1b42443d 1490 struct palmas_reg_init *rinit;
6c7d614f 1491 struct device_node *np;
036d193d
NM		 1492
1493 match = &ddata->palmas_matches[idx];
6c7d614f 1494 np = match->of_node;
036d193d 1495
6c7d614f 1496 if (!match->init_data || !np)
cac9e916 1497 continue;
e5ce4208 1498
1b42443d 1499 rinit = devm_kzalloc(dev, sizeof(*rinit), GFP_KERNEL);
7f091e53
NM		 1500 if (!rinit)
1501 return -ENOMEM;
1502
036d193d 1503 pdata->reg_data[idx] = match->init_data;
1b42443d 1504 pdata->reg_init[idx] = rinit;
a361cd9f 1505
6c7d614f
NM		 1506 rinit->warm_reset = of_property_read_bool(np, "ti,warm-reset");
1507 ret = of_property_read_u32(np, "ti,roof-floor", &prop);
cac9e916
K		 1508 /* EINVAL: Property not found */
1509 if (ret != -EINVAL) {
1510 int econtrol;
1511
1512 /* use default value, when no value is specified */
1513 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1514 if (!ret) {
1515 switch (prop) {
1516 case 1:
1517 econtrol = PALMAS_EXT_CONTROL_ENABLE1;
1518 break;
1519 case 2:
1520 econtrol = PALMAS_EXT_CONTROL_ENABLE2;
1521 break;
1522 case 3:
1523 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1524 break;
1525 default:
1526 WARN_ON(1);
1527 dev_warn(dev,
1528 "%s: Invalid roof-floor option: %u\n",
036d193d 1529 match->name, prop);
cac9e916
K		 1530 break;
1531 }
e5ce4208 1532 }
1b42443d 1533 rinit->roof_floor = econtrol;
e5ce4208 1534 }
e5ce4208 1535
6c7d614f 1536 ret = of_property_read_u32(np, "ti,mode-sleep", &prop);
cac9e916 1537 if (!ret)
1b42443d 1538 rinit->mode_sleep = prop;
17c11a76 1539
6c7d614f 1540 ret = of_property_read_bool(np, "ti,smps-range");
cac9e916 1541 if (ret)
1b42443d 1542 rinit->vsel = PALMAS_SMPS12_VOLTAGE_RANGE;
cac9e916
K		 1543
1544 if (idx == PALMAS_REG_LDO8)
1545 pdata->enable_ldo8_tracking = of_property_read_bool(
6c7d614f 1546 np, "ti,enable-ldo8-tracking");
cac9e916
K		 1547 }
1548
1549 pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
7f091e53
NM		 1550
1551 return 0;
e5ce4208
GG		 1552}
1553
cdbf6f0e 1554static const struct of_device_id of_palmas_match_tbl[] = {
cac9e916
K		 1555 {
1556 .compatible = "ti,palmas-pmic",
1557 .data = &palmas_ddata,
1558 },
1559 {
1560 .compatible = "ti,twl6035-pmic",
1561 .data = &palmas_ddata,
1562 },
1563 {
1564 .compatible = "ti,twl6036-pmic",
1565 .data = &palmas_ddata,
1566 },
1567 {
1568 .compatible = "ti,twl6037-pmic",
1569 .data = &palmas_ddata,
1570 },
1571 {
1572 .compatible = "ti,tps65913-pmic",
1573 .data = &palmas_ddata,
1574 },
1575 {
1576 .compatible = "ti,tps65914-pmic",
1577 .data = &palmas_ddata,
1578 },
1579 {
1580 .compatible = "ti,tps80036-pmic",
1581 .data = &palmas_ddata,
1582 },
1583 {
1584 .compatible = "ti,tps659038-pmic",
1585 .data = &palmas_ddata,
d6f83370
K		 1586 },
1587 {
1588 .compatible = "ti,tps65917-pmic",
1589 .data = &tps65917_ddata,
cac9e916 1590 },
a361cd9f
GG		 1591 { /* end */ }
1592};
1593
cac9e916
K		 1594static int palmas_regulators_probe(struct platform_device *pdev)
1595{
1596 struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
1fc2e768 1597 struct palmas_pmic_platform_data *pdata;
cac9e916
K		 1598 struct device_node *node = pdev->dev.of_node;
1599 struct palmas_pmic_driver_data *driver_data;
1600 struct regulator_config config = { };
1601 struct palmas_pmic *pmic;
1602 const char *pdev_name;
cac9e916
K		 1603 int ret = 0;
1604 unsigned int reg;
1605
8f7e17d8
RH		 1606 driver_data = (struct palmas_pmic_driver_data *)device_get_match_data(&pdev->dev);
1607 if (!driver_data)
cac9e916
K		 1608 return -ENODATA;
1609
cac9e916
K		 1610 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1611 if (!pdata)
1612 return -ENOMEM;
1613
1614 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
1615 if (!pmic)
1616 return -ENOMEM;
1617
e999c728 1618 if (of_device_is_compatible(node, "ti,tps659038-pmic")) {
e03826d5
K		 1619 palmas_generic_regs_info[PALMAS_REG_REGEN2].ctrl_addr =
1620 TPS659038_REGEN2_CTRL;
e999c728
K		 1621 palmas_ddata.has_regen3 = false;
1622 }
e03826d5 1623
cac9e916
K		 1624 pmic->dev = &pdev->dev;
1625 pmic->palmas = palmas;
1626 palmas->pmic = pmic;
1627 platform_set_drvdata(pdev, pmic);
1628 pmic->palmas->pmic_ddata = driver_data;
1629
7f091e53
NM		 1630 ret = palmas_dt_to_pdata(&pdev->dev, node, pdata, driver_data);
1631 if (ret)
1632 return ret;
cac9e916
K		 1633
1634 ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg);
1635 if (ret)
1636 return ret;
1637
be035303 1638 if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN) {
cac9e916 1639 pmic->smps123 = 1;
be035303
K		 1640 pmic->smps12 = 1;
1641 }
cac9e916
K		 1642
1643 if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
1644 pmic->smps457 = 1;
1645
1646 config.regmap = palmas->regmap[REGULATOR_SLAVE];
1647 config.dev = &pdev->dev;
1648 config.driver_data = pmic;
1649 pdev_name = pdev->name;
1650
1651 ret = driver_data->smps_register(pmic, driver_data, pdata, pdev_name,
1652 config);
1653 if (ret)
1654 return ret;
1655
1656 ret = driver_data->ldo_register(pmic, driver_data, pdata, pdev_name,
1657 config);
1658
1659 return ret;
1660}
1661
e5ce4208
GG		 1662static struct platform_driver palmas_driver = {
1663 .driver = {
1664 .name = "palmas-pmic",
259b93b2 1665 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
a361cd9f 1666 .of_match_table = of_palmas_match_tbl,
e5ce4208 1667 },
bbcf50b1 1668 .probe = palmas_regulators_probe,
e5ce4208
GG		 1669};
1670
1671static int __init palmas_init(void)
1672{
1673 return platform_driver_register(&palmas_driver);
1674}
1675subsys_initcall(palmas_init);
1676
1677static void __exit palmas_exit(void)
1678{
1679 platform_driver_unregister(&palmas_driver);
1680}
1681module_exit(palmas_exit);
1682
1683MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1684MODULE_DESCRIPTION("Palmas voltage regulator driver");
1685MODULE_LICENSE("GPL");
1686MODULE_ALIAS("platform:palmas-pmic");
a361cd9f 1687MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
Linux 6.x block layer and io_uring tree(s)