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1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // | |
3 | // Copyright (c) 2014 MediaTek Inc. | |
4 | // Author: Flora Fu <flora.fu@mediatek.com> | |
0425e242 FF |
5 | |
6 | #include <linux/module.h> | |
7 | #include <linux/of.h> | |
8 | #include <linux/platform_device.h> | |
9 | #include <linux/regmap.h> | |
10 | #include <linux/mfd/mt6397/core.h> | |
11 | #include <linux/mfd/mt6397/registers.h> | |
12 | #include <linux/regulator/driver.h> | |
13 | #include <linux/regulator/machine.h> | |
14 | #include <linux/regulator/mt6397-regulator.h> | |
15 | #include <linux/regulator/of_regulator.h> | |
16 | ||
05692513 HC |
17 | #define MT6397_BUCK_MODE_AUTO 0 |
18 | #define MT6397_BUCK_MODE_FORCE_PWM 1 | |
19 | ||
0425e242 FF |
20 | /* |
21 | * MT6397 regulators' information | |
22 | * | |
23 | * @desc: standard fields of regulator description. | |
24 | * @qi: Mask for query enable signal status of regulators | |
25 | * @vselon_reg: Register sections for hardware control mode of bucks | |
26 | * @vselctrl_reg: Register for controlling the buck control mode. | |
27 | * @vselctrl_mask: Mask for query buck's voltage control mode. | |
28 | */ | |
29 | struct mt6397_regulator_info { | |
30 | struct regulator_desc desc; | |
31 | u32 qi; | |
32 | u32 vselon_reg; | |
33 | u32 vselctrl_reg; | |
34 | u32 vselctrl_mask; | |
05692513 HC |
35 | u32 modeset_reg; |
36 | u32 modeset_mask; | |
37 | u32 modeset_shift; | |
0425e242 FF |
38 | }; |
39 | ||
40 | #define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ | |
05692513 HC |
41 | vosel, vosel_mask, voselon, vosel_ctrl, _modeset_reg, \ |
42 | _modeset_shift) \ | |
0425e242 FF |
43 | [MT6397_ID_##vreg] = { \ |
44 | .desc = { \ | |
45 | .name = #vreg, \ | |
46 | .of_match = of_match_ptr(match), \ | |
47 | .ops = &mt6397_volt_range_ops, \ | |
48 | .type = REGULATOR_VOLTAGE, \ | |
49 | .id = MT6397_ID_##vreg, \ | |
50 | .owner = THIS_MODULE, \ | |
51 | .n_voltages = (max - min)/step + 1, \ | |
52 | .linear_ranges = volt_ranges, \ | |
53 | .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ | |
54 | .vsel_reg = vosel, \ | |
55 | .vsel_mask = vosel_mask, \ | |
56 | .enable_reg = enreg, \ | |
57 | .enable_mask = BIT(0), \ | |
58 | }, \ | |
59 | .qi = BIT(13), \ | |
60 | .vselon_reg = voselon, \ | |
61 | .vselctrl_reg = vosel_ctrl, \ | |
62 | .vselctrl_mask = BIT(1), \ | |
05692513 HC |
63 | .modeset_reg = _modeset_reg, \ |
64 | .modeset_mask = BIT(_modeset_shift), \ | |
65 | .modeset_shift = _modeset_shift \ | |
0425e242 FF |
66 | } |
67 | ||
68 | #define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ | |
69 | vosel_mask) \ | |
70 | [MT6397_ID_##vreg] = { \ | |
71 | .desc = { \ | |
72 | .name = #vreg, \ | |
73 | .of_match = of_match_ptr(match), \ | |
74 | .ops = &mt6397_volt_table_ops, \ | |
75 | .type = REGULATOR_VOLTAGE, \ | |
76 | .id = MT6397_ID_##vreg, \ | |
77 | .owner = THIS_MODULE, \ | |
78 | .n_voltages = ARRAY_SIZE(ldo_volt_table), \ | |
79 | .volt_table = ldo_volt_table, \ | |
80 | .vsel_reg = vosel, \ | |
81 | .vsel_mask = vosel_mask, \ | |
82 | .enable_reg = enreg, \ | |
83 | .enable_mask = BIT(enbit), \ | |
84 | }, \ | |
85 | .qi = BIT(15), \ | |
86 | } | |
87 | ||
88 | #define MT6397_REG_FIXED(match, vreg, enreg, enbit, volt) \ | |
89 | [MT6397_ID_##vreg] = { \ | |
90 | .desc = { \ | |
91 | .name = #vreg, \ | |
92 | .of_match = of_match_ptr(match), \ | |
93 | .ops = &mt6397_volt_fixed_ops, \ | |
94 | .type = REGULATOR_VOLTAGE, \ | |
95 | .id = MT6397_ID_##vreg, \ | |
96 | .owner = THIS_MODULE, \ | |
97 | .n_voltages = 1, \ | |
98 | .enable_reg = enreg, \ | |
99 | .enable_mask = BIT(enbit), \ | |
100 | .min_uV = volt, \ | |
101 | }, \ | |
102 | .qi = BIT(15), \ | |
103 | } | |
104 | ||
105 | static const struct regulator_linear_range buck_volt_range1[] = { | |
106 | REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250), | |
107 | }; | |
108 | ||
109 | static const struct regulator_linear_range buck_volt_range2[] = { | |
110 | REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250), | |
111 | }; | |
112 | ||
113 | static const struct regulator_linear_range buck_volt_range3[] = { | |
114 | REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000), | |
115 | }; | |
116 | ||
dc3b2881 | 117 | static const unsigned int ldo_volt_table1[] = { |
0425e242 FF |
118 | 1500000, 1800000, 2500000, 2800000, |
119 | }; | |
120 | ||
dc3b2881 | 121 | static const unsigned int ldo_volt_table2[] = { |
0425e242 FF |
122 | 1800000, 3300000, |
123 | }; | |
124 | ||
dc3b2881 | 125 | static const unsigned int ldo_volt_table3[] = { |
0425e242 FF |
126 | 3000000, 3300000, |
127 | }; | |
128 | ||
dc3b2881 | 129 | static const unsigned int ldo_volt_table4[] = { |
0425e242 FF |
130 | 1220000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, |
131 | }; | |
132 | ||
dc3b2881 | 133 | static const unsigned int ldo_volt_table5[] = { |
0425e242 FF |
134 | 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, |
135 | }; | |
136 | ||
dc3b2881 | 137 | static const unsigned int ldo_volt_table5_v2[] = { |
0425e242 FF |
138 | 1200000, 1000000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, |
139 | }; | |
140 | ||
dc3b2881 | 141 | static const unsigned int ldo_volt_table6[] = { |
0425e242 FF |
142 | 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000, |
143 | }; | |
144 | ||
dc3b2881 | 145 | static const unsigned int ldo_volt_table7[] = { |
0425e242 FF |
146 | 1300000, 1500000, 1800000, 2000000, 2500000, 2800000, 3000000, 3300000, |
147 | }; | |
148 | ||
05692513 HC |
149 | static int mt6397_regulator_set_mode(struct regulator_dev *rdev, |
150 | unsigned int mode) | |
151 | { | |
152 | struct mt6397_regulator_info *info = rdev_get_drvdata(rdev); | |
153 | int ret, val; | |
154 | ||
155 | switch (mode) { | |
156 | case REGULATOR_MODE_FAST: | |
157 | val = MT6397_BUCK_MODE_FORCE_PWM; | |
158 | break; | |
159 | case REGULATOR_MODE_NORMAL: | |
160 | val = MT6397_BUCK_MODE_AUTO; | |
161 | break; | |
162 | default: | |
163 | ret = -EINVAL; | |
164 | goto err_mode; | |
165 | } | |
166 | ||
167 | dev_dbg(&rdev->dev, "mt6397 buck set_mode %#x, %#x, %#x, %#x\n", | |
168 | info->modeset_reg, info->modeset_mask, | |
169 | info->modeset_shift, val); | |
170 | ||
171 | val <<= info->modeset_shift; | |
172 | ret = regmap_update_bits(rdev->regmap, info->modeset_reg, | |
173 | info->modeset_mask, val); | |
174 | err_mode: | |
175 | if (ret != 0) { | |
176 | dev_err(&rdev->dev, | |
177 | "Failed to set mt6397 buck mode: %d\n", ret); | |
178 | return ret; | |
179 | } | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
184 | static unsigned int mt6397_regulator_get_mode(struct regulator_dev *rdev) | |
185 | { | |
186 | struct mt6397_regulator_info *info = rdev_get_drvdata(rdev); | |
187 | int ret, regval; | |
188 | ||
189 | ret = regmap_read(rdev->regmap, info->modeset_reg, ®val); | |
190 | if (ret != 0) { | |
191 | dev_err(&rdev->dev, | |
192 | "Failed to get mt6397 buck mode: %d\n", ret); | |
193 | return ret; | |
194 | } | |
195 | ||
196 | switch ((regval & info->modeset_mask) >> info->modeset_shift) { | |
197 | case MT6397_BUCK_MODE_AUTO: | |
198 | return REGULATOR_MODE_NORMAL; | |
199 | case MT6397_BUCK_MODE_FORCE_PWM: | |
200 | return REGULATOR_MODE_FAST; | |
201 | default: | |
202 | return -EINVAL; | |
203 | } | |
204 | } | |
205 | ||
0425e242 FF |
206 | static int mt6397_get_status(struct regulator_dev *rdev) |
207 | { | |
208 | int ret; | |
209 | u32 regval; | |
210 | struct mt6397_regulator_info *info = rdev_get_drvdata(rdev); | |
211 | ||
212 | ret = regmap_read(rdev->regmap, info->desc.enable_reg, ®val); | |
213 | if (ret != 0) { | |
214 | dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret); | |
215 | return ret; | |
216 | } | |
217 | ||
218 | return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; | |
219 | } | |
220 | ||
fb69114b | 221 | static const struct regulator_ops mt6397_volt_range_ops = { |
0425e242 FF |
222 | .list_voltage = regulator_list_voltage_linear_range, |
223 | .map_voltage = regulator_map_voltage_linear_range, | |
224 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
225 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
226 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
227 | .enable = regulator_enable_regmap, | |
228 | .disable = regulator_disable_regmap, | |
229 | .is_enabled = regulator_is_enabled_regmap, | |
230 | .get_status = mt6397_get_status, | |
05692513 HC |
231 | .set_mode = mt6397_regulator_set_mode, |
232 | .get_mode = mt6397_regulator_get_mode, | |
0425e242 FF |
233 | }; |
234 | ||
fb69114b | 235 | static const struct regulator_ops mt6397_volt_table_ops = { |
0425e242 FF |
236 | .list_voltage = regulator_list_voltage_table, |
237 | .map_voltage = regulator_map_voltage_iterate, | |
238 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
239 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
240 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
241 | .enable = regulator_enable_regmap, | |
242 | .disable = regulator_disable_regmap, | |
243 | .is_enabled = regulator_is_enabled_regmap, | |
244 | .get_status = mt6397_get_status, | |
245 | }; | |
246 | ||
fb69114b | 247 | static const struct regulator_ops mt6397_volt_fixed_ops = { |
0425e242 FF |
248 | .list_voltage = regulator_list_voltage_linear, |
249 | .enable = regulator_enable_regmap, | |
250 | .disable = regulator_disable_regmap, | |
251 | .is_enabled = regulator_is_enabled_regmap, | |
252 | .get_status = mt6397_get_status, | |
253 | }; | |
254 | ||
255 | /* The array is indexed by id(MT6397_ID_XXX) */ | |
256 | static struct mt6397_regulator_info mt6397_regulators[] = { | |
257 | MT6397_BUCK("buck_vpca15", VPCA15, 700000, 1493750, 6250, | |
258 | buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f, | |
05692513 | 259 | MT6397_VCA15_CON10, MT6397_VCA15_CON5, MT6397_VCA15_CON2, 11), |
0425e242 FF |
260 | MT6397_BUCK("buck_vpca7", VPCA7, 700000, 1493750, 6250, |
261 | buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f, | |
05692513 | 262 | MT6397_VPCA7_CON10, MT6397_VPCA7_CON5, MT6397_VPCA7_CON2, 8), |
0425e242 FF |
263 | MT6397_BUCK("buck_vsramca15", VSRAMCA15, 700000, 1493750, 6250, |
264 | buck_volt_range1, MT6397_VSRMCA15_CON7, MT6397_VSRMCA15_CON9, | |
05692513 HC |
265 | 0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5, |
266 | MT6397_VSRMCA15_CON2, 8), | |
0425e242 FF |
267 | MT6397_BUCK("buck_vsramca7", VSRAMCA7, 700000, 1493750, 6250, |
268 | buck_volt_range1, MT6397_VSRMCA7_CON7, MT6397_VSRMCA7_CON9, | |
05692513 HC |
269 | 0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5, |
270 | MT6397_VSRMCA7_CON2, 8), | |
0425e242 FF |
271 | MT6397_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250, |
272 | buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f, | |
05692513 | 273 | MT6397_VCORE_CON10, MT6397_VCORE_CON5, MT6397_VCORE_CON2, 8), |
0425e242 FF |
274 | MT6397_BUCK("buck_vgpu", VGPU, 700000, 1493750, 6250, buck_volt_range1, |
275 | MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f, | |
05692513 | 276 | MT6397_VGPU_CON10, MT6397_VGPU_CON5, MT6397_VGPU_CON2, 8), |
0425e242 FF |
277 | MT6397_BUCK("buck_vdrm", VDRM, 800000, 1593750, 6250, buck_volt_range2, |
278 | MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f, | |
05692513 | 279 | MT6397_VDRM_CON10, MT6397_VDRM_CON5, MT6397_VDRM_CON2, 8), |
0425e242 FF |
280 | MT6397_BUCK("buck_vio18", VIO18, 1500000, 2120000, 20000, |
281 | buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f, | |
05692513 | 282 | MT6397_VIO18_CON10, MT6397_VIO18_CON5, MT6397_VIO18_CON2, 8), |
0425e242 FF |
283 | MT6397_REG_FIXED("ldo_vtcxo", VTCXO, MT6397_ANALDO_CON0, 10, 2800000), |
284 | MT6397_REG_FIXED("ldo_va28", VA28, MT6397_ANALDO_CON1, 14, 2800000), | |
285 | MT6397_LDO("ldo_vcama", VCAMA, ldo_volt_table1, | |
286 | MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0), | |
287 | MT6397_REG_FIXED("ldo_vio28", VIO28, MT6397_DIGLDO_CON0, 14, 2800000), | |
288 | MT6397_REG_FIXED("ldo_vusb", VUSB, MT6397_DIGLDO_CON1, 14, 3300000), | |
289 | MT6397_LDO("ldo_vmc", VMC, ldo_volt_table2, | |
290 | MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10), | |
291 | MT6397_LDO("ldo_vmch", VMCH, ldo_volt_table3, | |
292 | MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80), | |
293 | MT6397_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table3, | |
294 | MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10), | |
295 | MT6397_LDO("ldo_vgp1", VGP1, ldo_volt_table4, | |
296 | MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0), | |
297 | MT6397_LDO("ldo_vgp2", VGP2, ldo_volt_table5, | |
298 | MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0), | |
299 | MT6397_LDO("ldo_vgp3", VGP3, ldo_volt_table5, | |
300 | MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0), | |
301 | MT6397_LDO("ldo_vgp4", VGP4, ldo_volt_table5, | |
302 | MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0), | |
303 | MT6397_LDO("ldo_vgp5", VGP5, ldo_volt_table6, | |
304 | MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0), | |
305 | MT6397_LDO("ldo_vgp6", VGP6, ldo_volt_table5, | |
306 | MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0), | |
307 | MT6397_LDO("ldo_vibr", VIBR, ldo_volt_table7, | |
308 | MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00), | |
309 | }; | |
310 | ||
311 | static int mt6397_set_buck_vosel_reg(struct platform_device *pdev) | |
312 | { | |
313 | struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); | |
314 | int i; | |
315 | u32 regval; | |
316 | ||
317 | for (i = 0; i < MT6397_MAX_REGULATOR; i++) { | |
318 | if (mt6397_regulators[i].vselctrl_reg) { | |
319 | if (regmap_read(mt6397->regmap, | |
320 | mt6397_regulators[i].vselctrl_reg, | |
321 | ®val) < 0) { | |
322 | dev_err(&pdev->dev, | |
323 | "Failed to read buck ctrl\n"); | |
324 | return -EIO; | |
325 | } | |
326 | ||
327 | if (regval & mt6397_regulators[i].vselctrl_mask) { | |
328 | mt6397_regulators[i].desc.vsel_reg = | |
329 | mt6397_regulators[i].vselon_reg; | |
330 | } | |
331 | } | |
332 | } | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | static int mt6397_regulator_probe(struct platform_device *pdev) | |
338 | { | |
339 | struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); | |
340 | struct regulator_config config = {}; | |
341 | struct regulator_dev *rdev; | |
342 | int i; | |
343 | u32 reg_value, version; | |
344 | ||
345 | /* Query buck controller to select activated voltage register part */ | |
346 | if (mt6397_set_buck_vosel_reg(pdev)) | |
347 | return -EIO; | |
348 | ||
349 | /* Read PMIC chip revision to update constraints and voltage table */ | |
350 | if (regmap_read(mt6397->regmap, MT6397_CID, ®_value) < 0) { | |
351 | dev_err(&pdev->dev, "Failed to read Chip ID\n"); | |
352 | return -EIO; | |
353 | } | |
354 | dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value); | |
355 | ||
356 | version = (reg_value & 0xFF); | |
357 | switch (version) { | |
358 | case MT6397_REGULATOR_ID91: | |
359 | mt6397_regulators[MT6397_ID_VGP2].desc.volt_table = | |
360 | ldo_volt_table5_v2; | |
361 | break; | |
362 | default: | |
363 | break; | |
364 | } | |
365 | ||
366 | for (i = 0; i < MT6397_MAX_REGULATOR; i++) { | |
367 | config.dev = &pdev->dev; | |
368 | config.driver_data = &mt6397_regulators[i]; | |
369 | config.regmap = mt6397->regmap; | |
370 | rdev = devm_regulator_register(&pdev->dev, | |
371 | &mt6397_regulators[i].desc, &config); | |
372 | if (IS_ERR(rdev)) { | |
373 | dev_err(&pdev->dev, "failed to register %s\n", | |
374 | mt6397_regulators[i].desc.name); | |
375 | return PTR_ERR(rdev); | |
376 | } | |
377 | } | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
288a89bf JMC |
382 | static const struct platform_device_id mt6397_platform_ids[] = { |
383 | {"mt6397-regulator", 0}, | |
384 | { /* sentinel */ }, | |
385 | }; | |
386 | MODULE_DEVICE_TABLE(platform, mt6397_platform_ids); | |
387 | ||
abbf043b JMC |
388 | static const struct of_device_id mt6397_of_match[] = { |
389 | { .compatible = "mediatek,mt6397-regulator", }, | |
390 | { /* sentinel */ }, | |
391 | }; | |
392 | MODULE_DEVICE_TABLE(of, mt6397_of_match); | |
393 | ||
0425e242 FF |
394 | static struct platform_driver mt6397_regulator_driver = { |
395 | .driver = { | |
396 | .name = "mt6397-regulator", | |
abbf043b | 397 | .of_match_table = of_match_ptr(mt6397_of_match), |
0425e242 FF |
398 | }, |
399 | .probe = mt6397_regulator_probe, | |
288a89bf | 400 | .id_table = mt6397_platform_ids, |
0425e242 FF |
401 | }; |
402 | ||
403 | module_platform_driver(mt6397_regulator_driver); | |
404 | ||
405 | MODULE_AUTHOR("Flora Fu <flora.fu@mediatek.com>"); | |
406 | MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC"); | |
407 | MODULE_LICENSE("GPL"); |