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0425e242 FF |
1 | /* |
2 | * Copyright (c) 2014 MediaTek Inc. | |
3 | * Author: Flora Fu <flora.fu@mediatek.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/regmap.h> | |
19 | #include <linux/mfd/mt6397/core.h> | |
20 | #include <linux/mfd/mt6397/registers.h> | |
21 | #include <linux/regulator/driver.h> | |
22 | #include <linux/regulator/machine.h> | |
23 | #include <linux/regulator/mt6397-regulator.h> | |
24 | #include <linux/regulator/of_regulator.h> | |
25 | ||
05692513 HC |
26 | #define MT6397_BUCK_MODE_AUTO 0 |
27 | #define MT6397_BUCK_MODE_FORCE_PWM 1 | |
28 | ||
0425e242 FF |
29 | /* |
30 | * MT6397 regulators' information | |
31 | * | |
32 | * @desc: standard fields of regulator description. | |
33 | * @qi: Mask for query enable signal status of regulators | |
34 | * @vselon_reg: Register sections for hardware control mode of bucks | |
35 | * @vselctrl_reg: Register for controlling the buck control mode. | |
36 | * @vselctrl_mask: Mask for query buck's voltage control mode. | |
37 | */ | |
38 | struct mt6397_regulator_info { | |
39 | struct regulator_desc desc; | |
40 | u32 qi; | |
41 | u32 vselon_reg; | |
42 | u32 vselctrl_reg; | |
43 | u32 vselctrl_mask; | |
05692513 HC |
44 | u32 modeset_reg; |
45 | u32 modeset_mask; | |
46 | u32 modeset_shift; | |
0425e242 FF |
47 | }; |
48 | ||
49 | #define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ | |
05692513 HC |
50 | vosel, vosel_mask, voselon, vosel_ctrl, _modeset_reg, \ |
51 | _modeset_shift) \ | |
0425e242 FF |
52 | [MT6397_ID_##vreg] = { \ |
53 | .desc = { \ | |
54 | .name = #vreg, \ | |
55 | .of_match = of_match_ptr(match), \ | |
56 | .ops = &mt6397_volt_range_ops, \ | |
57 | .type = REGULATOR_VOLTAGE, \ | |
58 | .id = MT6397_ID_##vreg, \ | |
59 | .owner = THIS_MODULE, \ | |
60 | .n_voltages = (max - min)/step + 1, \ | |
61 | .linear_ranges = volt_ranges, \ | |
62 | .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ | |
63 | .vsel_reg = vosel, \ | |
64 | .vsel_mask = vosel_mask, \ | |
65 | .enable_reg = enreg, \ | |
66 | .enable_mask = BIT(0), \ | |
67 | }, \ | |
68 | .qi = BIT(13), \ | |
69 | .vselon_reg = voselon, \ | |
70 | .vselctrl_reg = vosel_ctrl, \ | |
71 | .vselctrl_mask = BIT(1), \ | |
05692513 HC |
72 | .modeset_reg = _modeset_reg, \ |
73 | .modeset_mask = BIT(_modeset_shift), \ | |
74 | .modeset_shift = _modeset_shift \ | |
0425e242 FF |
75 | } |
76 | ||
77 | #define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ | |
78 | vosel_mask) \ | |
79 | [MT6397_ID_##vreg] = { \ | |
80 | .desc = { \ | |
81 | .name = #vreg, \ | |
82 | .of_match = of_match_ptr(match), \ | |
83 | .ops = &mt6397_volt_table_ops, \ | |
84 | .type = REGULATOR_VOLTAGE, \ | |
85 | .id = MT6397_ID_##vreg, \ | |
86 | .owner = THIS_MODULE, \ | |
87 | .n_voltages = ARRAY_SIZE(ldo_volt_table), \ | |
88 | .volt_table = ldo_volt_table, \ | |
89 | .vsel_reg = vosel, \ | |
90 | .vsel_mask = vosel_mask, \ | |
91 | .enable_reg = enreg, \ | |
92 | .enable_mask = BIT(enbit), \ | |
93 | }, \ | |
94 | .qi = BIT(15), \ | |
95 | } | |
96 | ||
97 | #define MT6397_REG_FIXED(match, vreg, enreg, enbit, volt) \ | |
98 | [MT6397_ID_##vreg] = { \ | |
99 | .desc = { \ | |
100 | .name = #vreg, \ | |
101 | .of_match = of_match_ptr(match), \ | |
102 | .ops = &mt6397_volt_fixed_ops, \ | |
103 | .type = REGULATOR_VOLTAGE, \ | |
104 | .id = MT6397_ID_##vreg, \ | |
105 | .owner = THIS_MODULE, \ | |
106 | .n_voltages = 1, \ | |
107 | .enable_reg = enreg, \ | |
108 | .enable_mask = BIT(enbit), \ | |
109 | .min_uV = volt, \ | |
110 | }, \ | |
111 | .qi = BIT(15), \ | |
112 | } | |
113 | ||
114 | static const struct regulator_linear_range buck_volt_range1[] = { | |
115 | REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250), | |
116 | }; | |
117 | ||
118 | static const struct regulator_linear_range buck_volt_range2[] = { | |
119 | REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250), | |
120 | }; | |
121 | ||
122 | static const struct regulator_linear_range buck_volt_range3[] = { | |
123 | REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000), | |
124 | }; | |
125 | ||
126 | static const u32 ldo_volt_table1[] = { | |
127 | 1500000, 1800000, 2500000, 2800000, | |
128 | }; | |
129 | ||
130 | static const u32 ldo_volt_table2[] = { | |
131 | 1800000, 3300000, | |
132 | }; | |
133 | ||
134 | static const u32 ldo_volt_table3[] = { | |
135 | 3000000, 3300000, | |
136 | }; | |
137 | ||
138 | static const u32 ldo_volt_table4[] = { | |
139 | 1220000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, | |
140 | }; | |
141 | ||
142 | static const u32 ldo_volt_table5[] = { | |
143 | 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, | |
144 | }; | |
145 | ||
146 | static const u32 ldo_volt_table5_v2[] = { | |
147 | 1200000, 1000000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, | |
148 | }; | |
149 | ||
150 | static const u32 ldo_volt_table6[] = { | |
151 | 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000, | |
152 | }; | |
153 | ||
154 | static const u32 ldo_volt_table7[] = { | |
155 | 1300000, 1500000, 1800000, 2000000, 2500000, 2800000, 3000000, 3300000, | |
156 | }; | |
157 | ||
05692513 HC |
158 | static int mt6397_regulator_set_mode(struct regulator_dev *rdev, |
159 | unsigned int mode) | |
160 | { | |
161 | struct mt6397_regulator_info *info = rdev_get_drvdata(rdev); | |
162 | int ret, val; | |
163 | ||
164 | switch (mode) { | |
165 | case REGULATOR_MODE_FAST: | |
166 | val = MT6397_BUCK_MODE_FORCE_PWM; | |
167 | break; | |
168 | case REGULATOR_MODE_NORMAL: | |
169 | val = MT6397_BUCK_MODE_AUTO; | |
170 | break; | |
171 | default: | |
172 | ret = -EINVAL; | |
173 | goto err_mode; | |
174 | } | |
175 | ||
176 | dev_dbg(&rdev->dev, "mt6397 buck set_mode %#x, %#x, %#x, %#x\n", | |
177 | info->modeset_reg, info->modeset_mask, | |
178 | info->modeset_shift, val); | |
179 | ||
180 | val <<= info->modeset_shift; | |
181 | ret = regmap_update_bits(rdev->regmap, info->modeset_reg, | |
182 | info->modeset_mask, val); | |
183 | err_mode: | |
184 | if (ret != 0) { | |
185 | dev_err(&rdev->dev, | |
186 | "Failed to set mt6397 buck mode: %d\n", ret); | |
187 | return ret; | |
188 | } | |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
193 | static unsigned int mt6397_regulator_get_mode(struct regulator_dev *rdev) | |
194 | { | |
195 | struct mt6397_regulator_info *info = rdev_get_drvdata(rdev); | |
196 | int ret, regval; | |
197 | ||
198 | ret = regmap_read(rdev->regmap, info->modeset_reg, ®val); | |
199 | if (ret != 0) { | |
200 | dev_err(&rdev->dev, | |
201 | "Failed to get mt6397 buck mode: %d\n", ret); | |
202 | return ret; | |
203 | } | |
204 | ||
205 | switch ((regval & info->modeset_mask) >> info->modeset_shift) { | |
206 | case MT6397_BUCK_MODE_AUTO: | |
207 | return REGULATOR_MODE_NORMAL; | |
208 | case MT6397_BUCK_MODE_FORCE_PWM: | |
209 | return REGULATOR_MODE_FAST; | |
210 | default: | |
211 | return -EINVAL; | |
212 | } | |
213 | } | |
214 | ||
0425e242 FF |
215 | static int mt6397_get_status(struct regulator_dev *rdev) |
216 | { | |
217 | int ret; | |
218 | u32 regval; | |
219 | struct mt6397_regulator_info *info = rdev_get_drvdata(rdev); | |
220 | ||
221 | ret = regmap_read(rdev->regmap, info->desc.enable_reg, ®val); | |
222 | if (ret != 0) { | |
223 | dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret); | |
224 | return ret; | |
225 | } | |
226 | ||
227 | return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; | |
228 | } | |
229 | ||
fb69114b | 230 | static const struct regulator_ops mt6397_volt_range_ops = { |
0425e242 FF |
231 | .list_voltage = regulator_list_voltage_linear_range, |
232 | .map_voltage = regulator_map_voltage_linear_range, | |
233 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
234 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
235 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
236 | .enable = regulator_enable_regmap, | |
237 | .disable = regulator_disable_regmap, | |
238 | .is_enabled = regulator_is_enabled_regmap, | |
239 | .get_status = mt6397_get_status, | |
05692513 HC |
240 | .set_mode = mt6397_regulator_set_mode, |
241 | .get_mode = mt6397_regulator_get_mode, | |
0425e242 FF |
242 | }; |
243 | ||
fb69114b | 244 | static const struct regulator_ops mt6397_volt_table_ops = { |
0425e242 FF |
245 | .list_voltage = regulator_list_voltage_table, |
246 | .map_voltage = regulator_map_voltage_iterate, | |
247 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
248 | .get_voltage_sel = regulator_get_voltage_sel_regmap, | |
249 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
250 | .enable = regulator_enable_regmap, | |
251 | .disable = regulator_disable_regmap, | |
252 | .is_enabled = regulator_is_enabled_regmap, | |
253 | .get_status = mt6397_get_status, | |
254 | }; | |
255 | ||
fb69114b | 256 | static const struct regulator_ops mt6397_volt_fixed_ops = { |
0425e242 FF |
257 | .list_voltage = regulator_list_voltage_linear, |
258 | .enable = regulator_enable_regmap, | |
259 | .disable = regulator_disable_regmap, | |
260 | .is_enabled = regulator_is_enabled_regmap, | |
261 | .get_status = mt6397_get_status, | |
262 | }; | |
263 | ||
264 | /* The array is indexed by id(MT6397_ID_XXX) */ | |
265 | static struct mt6397_regulator_info mt6397_regulators[] = { | |
266 | MT6397_BUCK("buck_vpca15", VPCA15, 700000, 1493750, 6250, | |
267 | buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f, | |
05692513 | 268 | MT6397_VCA15_CON10, MT6397_VCA15_CON5, MT6397_VCA15_CON2, 11), |
0425e242 FF |
269 | MT6397_BUCK("buck_vpca7", VPCA7, 700000, 1493750, 6250, |
270 | buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f, | |
05692513 | 271 | MT6397_VPCA7_CON10, MT6397_VPCA7_CON5, MT6397_VPCA7_CON2, 8), |
0425e242 FF |
272 | MT6397_BUCK("buck_vsramca15", VSRAMCA15, 700000, 1493750, 6250, |
273 | buck_volt_range1, MT6397_VSRMCA15_CON7, MT6397_VSRMCA15_CON9, | |
05692513 HC |
274 | 0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5, |
275 | MT6397_VSRMCA15_CON2, 8), | |
0425e242 FF |
276 | MT6397_BUCK("buck_vsramca7", VSRAMCA7, 700000, 1493750, 6250, |
277 | buck_volt_range1, MT6397_VSRMCA7_CON7, MT6397_VSRMCA7_CON9, | |
05692513 HC |
278 | 0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5, |
279 | MT6397_VSRMCA7_CON2, 8), | |
0425e242 FF |
280 | MT6397_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250, |
281 | buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f, | |
05692513 | 282 | MT6397_VCORE_CON10, MT6397_VCORE_CON5, MT6397_VCORE_CON2, 8), |
0425e242 FF |
283 | MT6397_BUCK("buck_vgpu", VGPU, 700000, 1493750, 6250, buck_volt_range1, |
284 | MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f, | |
05692513 | 285 | MT6397_VGPU_CON10, MT6397_VGPU_CON5, MT6397_VGPU_CON2, 8), |
0425e242 FF |
286 | MT6397_BUCK("buck_vdrm", VDRM, 800000, 1593750, 6250, buck_volt_range2, |
287 | MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f, | |
05692513 | 288 | MT6397_VDRM_CON10, MT6397_VDRM_CON5, MT6397_VDRM_CON2, 8), |
0425e242 FF |
289 | MT6397_BUCK("buck_vio18", VIO18, 1500000, 2120000, 20000, |
290 | buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f, | |
05692513 | 291 | MT6397_VIO18_CON10, MT6397_VIO18_CON5, MT6397_VIO18_CON2, 8), |
0425e242 FF |
292 | MT6397_REG_FIXED("ldo_vtcxo", VTCXO, MT6397_ANALDO_CON0, 10, 2800000), |
293 | MT6397_REG_FIXED("ldo_va28", VA28, MT6397_ANALDO_CON1, 14, 2800000), | |
294 | MT6397_LDO("ldo_vcama", VCAMA, ldo_volt_table1, | |
295 | MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0), | |
296 | MT6397_REG_FIXED("ldo_vio28", VIO28, MT6397_DIGLDO_CON0, 14, 2800000), | |
297 | MT6397_REG_FIXED("ldo_vusb", VUSB, MT6397_DIGLDO_CON1, 14, 3300000), | |
298 | MT6397_LDO("ldo_vmc", VMC, ldo_volt_table2, | |
299 | MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10), | |
300 | MT6397_LDO("ldo_vmch", VMCH, ldo_volt_table3, | |
301 | MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80), | |
302 | MT6397_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table3, | |
303 | MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10), | |
304 | MT6397_LDO("ldo_vgp1", VGP1, ldo_volt_table4, | |
305 | MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0), | |
306 | MT6397_LDO("ldo_vgp2", VGP2, ldo_volt_table5, | |
307 | MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0), | |
308 | MT6397_LDO("ldo_vgp3", VGP3, ldo_volt_table5, | |
309 | MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0), | |
310 | MT6397_LDO("ldo_vgp4", VGP4, ldo_volt_table5, | |
311 | MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0), | |
312 | MT6397_LDO("ldo_vgp5", VGP5, ldo_volt_table6, | |
313 | MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0), | |
314 | MT6397_LDO("ldo_vgp6", VGP6, ldo_volt_table5, | |
315 | MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0), | |
316 | MT6397_LDO("ldo_vibr", VIBR, ldo_volt_table7, | |
317 | MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00), | |
318 | }; | |
319 | ||
320 | static int mt6397_set_buck_vosel_reg(struct platform_device *pdev) | |
321 | { | |
322 | struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); | |
323 | int i; | |
324 | u32 regval; | |
325 | ||
326 | for (i = 0; i < MT6397_MAX_REGULATOR; i++) { | |
327 | if (mt6397_regulators[i].vselctrl_reg) { | |
328 | if (regmap_read(mt6397->regmap, | |
329 | mt6397_regulators[i].vselctrl_reg, | |
330 | ®val) < 0) { | |
331 | dev_err(&pdev->dev, | |
332 | "Failed to read buck ctrl\n"); | |
333 | return -EIO; | |
334 | } | |
335 | ||
336 | if (regval & mt6397_regulators[i].vselctrl_mask) { | |
337 | mt6397_regulators[i].desc.vsel_reg = | |
338 | mt6397_regulators[i].vselon_reg; | |
339 | } | |
340 | } | |
341 | } | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | static int mt6397_regulator_probe(struct platform_device *pdev) | |
347 | { | |
348 | struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); | |
349 | struct regulator_config config = {}; | |
350 | struct regulator_dev *rdev; | |
351 | int i; | |
352 | u32 reg_value, version; | |
353 | ||
354 | /* Query buck controller to select activated voltage register part */ | |
355 | if (mt6397_set_buck_vosel_reg(pdev)) | |
356 | return -EIO; | |
357 | ||
358 | /* Read PMIC chip revision to update constraints and voltage table */ | |
359 | if (regmap_read(mt6397->regmap, MT6397_CID, ®_value) < 0) { | |
360 | dev_err(&pdev->dev, "Failed to read Chip ID\n"); | |
361 | return -EIO; | |
362 | } | |
363 | dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value); | |
364 | ||
365 | version = (reg_value & 0xFF); | |
366 | switch (version) { | |
367 | case MT6397_REGULATOR_ID91: | |
368 | mt6397_regulators[MT6397_ID_VGP2].desc.volt_table = | |
369 | ldo_volt_table5_v2; | |
370 | break; | |
371 | default: | |
372 | break; | |
373 | } | |
374 | ||
375 | for (i = 0; i < MT6397_MAX_REGULATOR; i++) { | |
376 | config.dev = &pdev->dev; | |
377 | config.driver_data = &mt6397_regulators[i]; | |
378 | config.regmap = mt6397->regmap; | |
379 | rdev = devm_regulator_register(&pdev->dev, | |
380 | &mt6397_regulators[i].desc, &config); | |
381 | if (IS_ERR(rdev)) { | |
382 | dev_err(&pdev->dev, "failed to register %s\n", | |
383 | mt6397_regulators[i].desc.name); | |
384 | return PTR_ERR(rdev); | |
385 | } | |
386 | } | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
288a89bf JMC |
391 | static const struct platform_device_id mt6397_platform_ids[] = { |
392 | {"mt6397-regulator", 0}, | |
393 | { /* sentinel */ }, | |
394 | }; | |
395 | MODULE_DEVICE_TABLE(platform, mt6397_platform_ids); | |
396 | ||
abbf043b JMC |
397 | static const struct of_device_id mt6397_of_match[] = { |
398 | { .compatible = "mediatek,mt6397-regulator", }, | |
399 | { /* sentinel */ }, | |
400 | }; | |
401 | MODULE_DEVICE_TABLE(of, mt6397_of_match); | |
402 | ||
0425e242 FF |
403 | static struct platform_driver mt6397_regulator_driver = { |
404 | .driver = { | |
405 | .name = "mt6397-regulator", | |
abbf043b | 406 | .of_match_table = of_match_ptr(mt6397_of_match), |
0425e242 FF |
407 | }, |
408 | .probe = mt6397_regulator_probe, | |
288a89bf | 409 | .id_table = mt6397_platform_ids, |
0425e242 FF |
410 | }; |
411 | ||
412 | module_platform_driver(mt6397_regulator_driver); | |
413 | ||
414 | MODULE_AUTHOR("Flora Fu <flora.fu@mediatek.com>"); | |
415 | MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC"); | |
416 | MODULE_LICENSE("GPL"); |