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f67ff1bd HHW |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // | |
3 | // Copyright (c) 2019 MediaTek Inc. | |
4 | ||
5 | #include <linux/mfd/mt6358/registers.h> | |
6 | #include <linux/mfd/mt6397/core.h> | |
7 | #include <linux/module.h> | |
8 | #include <linux/of.h> | |
9 | #include <linux/platform_device.h> | |
10 | #include <linux/regmap.h> | |
11 | #include <linux/regulator/driver.h> | |
12 | #include <linux/regulator/machine.h> | |
13 | #include <linux/regulator/mt6358-regulator.h> | |
14 | #include <linux/regulator/of_regulator.h> | |
15 | ||
16 | #define MT6358_BUCK_MODE_AUTO 0 | |
17 | #define MT6358_BUCK_MODE_FORCE_PWM 1 | |
18 | ||
19 | /* | |
20 | * MT6358 regulators' information | |
21 | * | |
22 | * @desc: standard fields of regulator description. | |
23 | * @qi: Mask for query enable signal status of regulators | |
24 | */ | |
25 | struct mt6358_regulator_info { | |
26 | struct regulator_desc desc; | |
27 | u32 status_reg; | |
28 | u32 qi; | |
29 | const u32 *index_table; | |
30 | unsigned int n_table; | |
f67ff1bd HHW |
31 | u32 da_vsel_reg; |
32 | u32 da_vsel_mask; | |
f67ff1bd HHW |
33 | u32 modeset_reg; |
34 | u32 modeset_mask; | |
f67ff1bd HHW |
35 | }; |
36 | ||
37 | #define MT6358_BUCK(match, vreg, min, max, step, \ | |
38 | volt_ranges, vosel_mask, _da_vsel_reg, _da_vsel_mask, \ | |
b99b7b79 | 39 | _modeset_reg, _modeset_shift) \ |
f67ff1bd HHW |
40 | [MT6358_ID_##vreg] = { \ |
41 | .desc = { \ | |
42 | .name = #vreg, \ | |
43 | .of_match = of_match_ptr(match), \ | |
44 | .ops = &mt6358_volt_range_ops, \ | |
45 | .type = REGULATOR_VOLTAGE, \ | |
46 | .id = MT6358_ID_##vreg, \ | |
47 | .owner = THIS_MODULE, \ | |
48 | .n_voltages = ((max) - (min)) / (step) + 1, \ | |
49 | .linear_ranges = volt_ranges, \ | |
50 | .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ | |
51 | .vsel_reg = MT6358_BUCK_##vreg##_ELR0, \ | |
52 | .vsel_mask = vosel_mask, \ | |
53 | .enable_reg = MT6358_BUCK_##vreg##_CON0, \ | |
54 | .enable_mask = BIT(0), \ | |
55 | .of_map_mode = mt6358_map_mode, \ | |
56 | }, \ | |
57 | .status_reg = MT6358_BUCK_##vreg##_DBG1, \ | |
58 | .qi = BIT(0), \ | |
59 | .da_vsel_reg = _da_vsel_reg, \ | |
60 | .da_vsel_mask = _da_vsel_mask, \ | |
f67ff1bd HHW |
61 | .modeset_reg = _modeset_reg, \ |
62 | .modeset_mask = BIT(_modeset_shift), \ | |
f67ff1bd HHW |
63 | } |
64 | ||
65 | #define MT6358_LDO(match, vreg, ldo_volt_table, \ | |
66 | ldo_index_table, enreg, enbit, vosel, \ | |
b99b7b79 | 67 | vosel_mask) \ |
f67ff1bd HHW |
68 | [MT6358_ID_##vreg] = { \ |
69 | .desc = { \ | |
70 | .name = #vreg, \ | |
71 | .of_match = of_match_ptr(match), \ | |
72 | .ops = &mt6358_volt_table_ops, \ | |
73 | .type = REGULATOR_VOLTAGE, \ | |
74 | .id = MT6358_ID_##vreg, \ | |
75 | .owner = THIS_MODULE, \ | |
76 | .n_voltages = ARRAY_SIZE(ldo_volt_table), \ | |
77 | .volt_table = ldo_volt_table, \ | |
78 | .vsel_reg = vosel, \ | |
79 | .vsel_mask = vosel_mask, \ | |
80 | .enable_reg = enreg, \ | |
81 | .enable_mask = BIT(enbit), \ | |
82 | }, \ | |
83 | .status_reg = MT6358_LDO_##vreg##_CON1, \ | |
84 | .qi = BIT(15), \ | |
85 | .index_table = ldo_index_table, \ | |
86 | .n_table = ARRAY_SIZE(ldo_index_table), \ | |
f67ff1bd HHW |
87 | } |
88 | ||
89 | #define MT6358_LDO1(match, vreg, min, max, step, \ | |
90 | volt_ranges, _da_vsel_reg, _da_vsel_mask, \ | |
b99b7b79 | 91 | vosel, vosel_mask) \ |
f67ff1bd HHW |
92 | [MT6358_ID_##vreg] = { \ |
93 | .desc = { \ | |
94 | .name = #vreg, \ | |
95 | .of_match = of_match_ptr(match), \ | |
96 | .ops = &mt6358_volt_range_ops, \ | |
97 | .type = REGULATOR_VOLTAGE, \ | |
98 | .id = MT6358_ID_##vreg, \ | |
99 | .owner = THIS_MODULE, \ | |
100 | .n_voltages = ((max) - (min)) / (step) + 1, \ | |
101 | .linear_ranges = volt_ranges, \ | |
102 | .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ | |
103 | .vsel_reg = vosel, \ | |
104 | .vsel_mask = vosel_mask, \ | |
105 | .enable_reg = MT6358_LDO_##vreg##_CON0, \ | |
106 | .enable_mask = BIT(0), \ | |
107 | }, \ | |
108 | .da_vsel_reg = _da_vsel_reg, \ | |
109 | .da_vsel_mask = _da_vsel_mask, \ | |
f67ff1bd HHW |
110 | .status_reg = MT6358_LDO_##vreg##_DBG1, \ |
111 | .qi = BIT(0), \ | |
112 | } | |
113 | ||
114 | #define MT6358_REG_FIXED(match, vreg, \ | |
115 | enreg, enbit, volt) \ | |
116 | [MT6358_ID_##vreg] = { \ | |
117 | .desc = { \ | |
118 | .name = #vreg, \ | |
119 | .of_match = of_match_ptr(match), \ | |
120 | .ops = &mt6358_volt_fixed_ops, \ | |
121 | .type = REGULATOR_VOLTAGE, \ | |
122 | .id = MT6358_ID_##vreg, \ | |
123 | .owner = THIS_MODULE, \ | |
124 | .n_voltages = 1, \ | |
125 | .enable_reg = enreg, \ | |
126 | .enable_mask = BIT(enbit), \ | |
127 | .min_uV = volt, \ | |
128 | }, \ | |
129 | .status_reg = MT6358_LDO_##vreg##_CON1, \ | |
130 | .qi = BIT(15), \ | |
131 | } | |
132 | ||
f0e3c626 JW |
133 | #define MT6366_BUCK(match, vreg, min, max, step, \ |
134 | volt_ranges, vosel_mask, _da_vsel_reg, _da_vsel_mask, \ | |
135 | _modeset_reg, _modeset_shift) \ | |
136 | [MT6366_ID_##vreg] = { \ | |
137 | .desc = { \ | |
138 | .name = #vreg, \ | |
139 | .of_match = of_match_ptr(match), \ | |
140 | .ops = &mt6358_volt_range_ops, \ | |
141 | .type = REGULATOR_VOLTAGE, \ | |
142 | .id = MT6366_ID_##vreg, \ | |
143 | .owner = THIS_MODULE, \ | |
144 | .n_voltages = ((max) - (min)) / (step) + 1, \ | |
145 | .linear_ranges = volt_ranges, \ | |
146 | .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ | |
147 | .vsel_reg = MT6358_BUCK_##vreg##_ELR0, \ | |
148 | .vsel_mask = vosel_mask, \ | |
149 | .enable_reg = MT6358_BUCK_##vreg##_CON0, \ | |
150 | .enable_mask = BIT(0), \ | |
151 | .of_map_mode = mt6358_map_mode, \ | |
152 | }, \ | |
153 | .status_reg = MT6358_BUCK_##vreg##_DBG1, \ | |
154 | .qi = BIT(0), \ | |
155 | .da_vsel_reg = _da_vsel_reg, \ | |
156 | .da_vsel_mask = _da_vsel_mask, \ | |
157 | .modeset_reg = _modeset_reg, \ | |
158 | .modeset_mask = BIT(_modeset_shift), \ | |
159 | } | |
160 | ||
161 | #define MT6366_LDO(match, vreg, ldo_volt_table, \ | |
162 | ldo_index_table, enreg, enbit, vosel, \ | |
163 | vosel_mask) \ | |
164 | [MT6366_ID_##vreg] = { \ | |
165 | .desc = { \ | |
166 | .name = #vreg, \ | |
167 | .of_match = of_match_ptr(match), \ | |
168 | .ops = &mt6358_volt_table_ops, \ | |
169 | .type = REGULATOR_VOLTAGE, \ | |
170 | .id = MT6366_ID_##vreg, \ | |
171 | .owner = THIS_MODULE, \ | |
172 | .n_voltages = ARRAY_SIZE(ldo_volt_table), \ | |
173 | .volt_table = ldo_volt_table, \ | |
174 | .vsel_reg = vosel, \ | |
175 | .vsel_mask = vosel_mask, \ | |
176 | .enable_reg = enreg, \ | |
177 | .enable_mask = BIT(enbit), \ | |
178 | }, \ | |
179 | .status_reg = MT6358_LDO_##vreg##_CON1, \ | |
180 | .qi = BIT(15), \ | |
181 | .index_table = ldo_index_table, \ | |
182 | .n_table = ARRAY_SIZE(ldo_index_table), \ | |
183 | } | |
184 | ||
185 | #define MT6366_LDO1(match, vreg, min, max, step, \ | |
186 | volt_ranges, _da_vsel_reg, _da_vsel_mask, \ | |
187 | vosel, vosel_mask) \ | |
188 | [MT6366_ID_##vreg] = { \ | |
189 | .desc = { \ | |
190 | .name = #vreg, \ | |
191 | .of_match = of_match_ptr(match), \ | |
192 | .ops = &mt6358_volt_range_ops, \ | |
193 | .type = REGULATOR_VOLTAGE, \ | |
194 | .id = MT6366_ID_##vreg, \ | |
195 | .owner = THIS_MODULE, \ | |
196 | .n_voltages = ((max) - (min)) / (step) + 1, \ | |
197 | .linear_ranges = volt_ranges, \ | |
198 | .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ | |
199 | .vsel_reg = vosel, \ | |
200 | .vsel_mask = vosel_mask, \ | |
201 | .enable_reg = MT6358_LDO_##vreg##_CON0, \ | |
202 | .enable_mask = BIT(0), \ | |
203 | }, \ | |
204 | .da_vsel_reg = _da_vsel_reg, \ | |
205 | .da_vsel_mask = _da_vsel_mask, \ | |
206 | .status_reg = MT6358_LDO_##vreg##_DBG1, \ | |
207 | .qi = BIT(0), \ | |
208 | } | |
209 | ||
210 | #define MT6366_REG_FIXED(match, vreg, \ | |
211 | enreg, enbit, volt) \ | |
212 | [MT6366_ID_##vreg] = { \ | |
213 | .desc = { \ | |
214 | .name = #vreg, \ | |
215 | .of_match = of_match_ptr(match), \ | |
216 | .ops = &mt6358_volt_fixed_ops, \ | |
217 | .type = REGULATOR_VOLTAGE, \ | |
218 | .id = MT6366_ID_##vreg, \ | |
219 | .owner = THIS_MODULE, \ | |
220 | .n_voltages = 1, \ | |
221 | .enable_reg = enreg, \ | |
222 | .enable_mask = BIT(enbit), \ | |
223 | .min_uV = volt, \ | |
224 | }, \ | |
225 | .status_reg = MT6358_LDO_##vreg##_CON1, \ | |
226 | .qi = BIT(15), \ | |
227 | } | |
228 | ||
60ab7f41 | 229 | static const struct linear_range buck_volt_range1[] = { |
f67ff1bd HHW |
230 | REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250), |
231 | }; | |
232 | ||
60ab7f41 | 233 | static const struct linear_range buck_volt_range2[] = { |
f67ff1bd HHW |
234 | REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500), |
235 | }; | |
236 | ||
60ab7f41 | 237 | static const struct linear_range buck_volt_range3[] = { |
f67ff1bd HHW |
238 | REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000), |
239 | }; | |
240 | ||
60ab7f41 | 241 | static const struct linear_range buck_volt_range4[] = { |
f67ff1bd HHW |
242 | REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500), |
243 | }; | |
244 | ||
431ea63b | 245 | static const unsigned int vdram2_voltages[] = { |
f67ff1bd HHW |
246 | 600000, 1800000, |
247 | }; | |
248 | ||
431ea63b | 249 | static const unsigned int vsim_voltages[] = { |
f67ff1bd HHW |
250 | 1700000, 1800000, 2700000, 3000000, 3100000, |
251 | }; | |
252 | ||
431ea63b | 253 | static const unsigned int vibr_voltages[] = { |
f67ff1bd HHW |
254 | 1200000, 1300000, 1500000, 1800000, |
255 | 2000000, 2800000, 3000000, 3300000, | |
256 | }; | |
257 | ||
431ea63b | 258 | static const unsigned int vusb_voltages[] = { |
f67ff1bd HHW |
259 | 3000000, 3100000, |
260 | }; | |
261 | ||
431ea63b | 262 | static const unsigned int vcamd_voltages[] = { |
f67ff1bd HHW |
263 | 900000, 1000000, 1100000, 1200000, |
264 | 1300000, 1500000, 1800000, | |
265 | }; | |
266 | ||
431ea63b | 267 | static const unsigned int vefuse_voltages[] = { |
f67ff1bd HHW |
268 | 1700000, 1800000, 1900000, |
269 | }; | |
270 | ||
431ea63b | 271 | static const unsigned int vmch_vemc_voltages[] = { |
f67ff1bd HHW |
272 | 2900000, 3000000, 3300000, |
273 | }; | |
274 | ||
431ea63b | 275 | static const unsigned int vcama_voltages[] = { |
f67ff1bd HHW |
276 | 1800000, 2500000, 2700000, |
277 | 2800000, 2900000, 3000000, | |
278 | }; | |
279 | ||
431ea63b | 280 | static const unsigned int vcn33_bt_wifi_voltages[] = { |
f67ff1bd HHW |
281 | 3300000, 3400000, 3500000, |
282 | }; | |
283 | ||
431ea63b | 284 | static const unsigned int vmc_voltages[] = { |
f67ff1bd HHW |
285 | 1800000, 2900000, 3000000, 3300000, |
286 | }; | |
287 | ||
431ea63b | 288 | static const unsigned int vldo28_voltages[] = { |
f67ff1bd HHW |
289 | 2800000, 3000000, |
290 | }; | |
291 | ||
292 | static const u32 vdram2_idx[] = { | |
293 | 0, 12, | |
294 | }; | |
295 | ||
296 | static const u32 vsim_idx[] = { | |
297 | 3, 4, 8, 11, 12, | |
298 | }; | |
299 | ||
300 | static const u32 vibr_idx[] = { | |
301 | 0, 1, 2, 4, 5, 9, 11, 13, | |
302 | }; | |
303 | ||
304 | static const u32 vusb_idx[] = { | |
305 | 3, 4, | |
306 | }; | |
307 | ||
308 | static const u32 vcamd_idx[] = { | |
309 | 3, 4, 5, 6, 7, 9, 12, | |
310 | }; | |
311 | ||
312 | static const u32 vefuse_idx[] = { | |
313 | 11, 12, 13, | |
314 | }; | |
315 | ||
316 | static const u32 vmch_vemc_idx[] = { | |
317 | 2, 3, 5, | |
318 | }; | |
319 | ||
320 | static const u32 vcama_idx[] = { | |
321 | 0, 7, 9, 10, 11, 12, | |
322 | }; | |
323 | ||
324 | static const u32 vcn33_bt_wifi_idx[] = { | |
325 | 1, 2, 3, | |
326 | }; | |
327 | ||
328 | static const u32 vmc_idx[] = { | |
329 | 4, 10, 11, 13, | |
330 | }; | |
331 | ||
332 | static const u32 vldo28_idx[] = { | |
333 | 1, 3, | |
334 | }; | |
335 | ||
336 | static unsigned int mt6358_map_mode(unsigned int mode) | |
337 | { | |
338 | return mode == MT6358_BUCK_MODE_AUTO ? | |
339 | REGULATOR_MODE_NORMAL : REGULATOR_MODE_FAST; | |
340 | } | |
341 | ||
342 | static int mt6358_set_voltage_sel(struct regulator_dev *rdev, | |
343 | unsigned int selector) | |
344 | { | |
345 | int idx, ret; | |
346 | const u32 *pvol; | |
347 | struct mt6358_regulator_info *info = rdev_get_drvdata(rdev); | |
348 | ||
349 | pvol = info->index_table; | |
350 | ||
351 | idx = pvol[selector]; | |
b99b7b79 | 352 | idx <<= ffs(info->desc.vsel_mask) - 1; |
f67ff1bd | 353 | ret = regmap_update_bits(rdev->regmap, info->desc.vsel_reg, |
b99b7b79 | 354 | info->desc.vsel_mask, idx); |
f67ff1bd HHW |
355 | |
356 | return ret; | |
357 | } | |
358 | ||
359 | static int mt6358_get_voltage_sel(struct regulator_dev *rdev) | |
360 | { | |
361 | int idx, ret; | |
362 | u32 selector; | |
363 | struct mt6358_regulator_info *info = rdev_get_drvdata(rdev); | |
364 | const u32 *pvol; | |
365 | ||
366 | ret = regmap_read(rdev->regmap, info->desc.vsel_reg, &selector); | |
367 | if (ret != 0) { | |
368 | dev_info(&rdev->dev, | |
369 | "Failed to get mt6358 %s vsel reg: %d\n", | |
370 | info->desc.name, ret); | |
371 | return ret; | |
372 | } | |
373 | ||
b99b7b79 AL |
374 | selector = (selector & info->desc.vsel_mask) >> |
375 | (ffs(info->desc.vsel_mask) - 1); | |
f67ff1bd HHW |
376 | pvol = info->index_table; |
377 | for (idx = 0; idx < info->desc.n_voltages; idx++) { | |
378 | if (pvol[idx] == selector) | |
379 | return idx; | |
380 | } | |
381 | ||
382 | return -EINVAL; | |
383 | } | |
384 | ||
385 | static int mt6358_get_buck_voltage_sel(struct regulator_dev *rdev) | |
386 | { | |
387 | int ret, regval; | |
388 | struct mt6358_regulator_info *info = rdev_get_drvdata(rdev); | |
389 | ||
390 | ret = regmap_read(rdev->regmap, info->da_vsel_reg, ®val); | |
391 | if (ret != 0) { | |
392 | dev_err(&rdev->dev, | |
393 | "Failed to get mt6358 Buck %s vsel reg: %d\n", | |
394 | info->desc.name, ret); | |
395 | return ret; | |
396 | } | |
397 | ||
b99b7b79 | 398 | ret = (regval & info->da_vsel_mask) >> (ffs(info->da_vsel_mask) - 1); |
f67ff1bd HHW |
399 | |
400 | return ret; | |
401 | } | |
402 | ||
403 | static int mt6358_get_status(struct regulator_dev *rdev) | |
404 | { | |
405 | int ret; | |
406 | u32 regval; | |
407 | struct mt6358_regulator_info *info = rdev_get_drvdata(rdev); | |
408 | ||
409 | ret = regmap_read(rdev->regmap, info->status_reg, ®val); | |
410 | if (ret != 0) { | |
411 | dev_info(&rdev->dev, "Failed to get enable reg: %d\n", ret); | |
412 | return ret; | |
413 | } | |
414 | ||
415 | return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; | |
416 | } | |
417 | ||
418 | static int mt6358_regulator_set_mode(struct regulator_dev *rdev, | |
419 | unsigned int mode) | |
420 | { | |
421 | struct mt6358_regulator_info *info = rdev_get_drvdata(rdev); | |
422 | int val; | |
423 | ||
424 | switch (mode) { | |
425 | case REGULATOR_MODE_FAST: | |
426 | val = MT6358_BUCK_MODE_FORCE_PWM; | |
427 | break; | |
428 | case REGULATOR_MODE_NORMAL: | |
429 | val = MT6358_BUCK_MODE_AUTO; | |
430 | break; | |
431 | default: | |
432 | return -EINVAL; | |
433 | } | |
434 | ||
b99b7b79 AL |
435 | dev_dbg(&rdev->dev, "mt6358 buck set_mode %#x, %#x, %#x\n", |
436 | info->modeset_reg, info->modeset_mask, val); | |
f67ff1bd | 437 | |
b99b7b79 | 438 | val <<= ffs(info->modeset_mask) - 1; |
f67ff1bd HHW |
439 | |
440 | return regmap_update_bits(rdev->regmap, info->modeset_reg, | |
441 | info->modeset_mask, val); | |
442 | } | |
443 | ||
444 | static unsigned int mt6358_regulator_get_mode(struct regulator_dev *rdev) | |
445 | { | |
446 | struct mt6358_regulator_info *info = rdev_get_drvdata(rdev); | |
447 | int ret, regval; | |
448 | ||
449 | ret = regmap_read(rdev->regmap, info->modeset_reg, ®val); | |
450 | if (ret != 0) { | |
451 | dev_err(&rdev->dev, | |
452 | "Failed to get mt6358 buck mode: %d\n", ret); | |
453 | return ret; | |
454 | } | |
455 | ||
b99b7b79 | 456 | switch ((regval & info->modeset_mask) >> (ffs(info->modeset_mask) - 1)) { |
f67ff1bd HHW |
457 | case MT6358_BUCK_MODE_AUTO: |
458 | return REGULATOR_MODE_NORMAL; | |
459 | case MT6358_BUCK_MODE_FORCE_PWM: | |
460 | return REGULATOR_MODE_FAST; | |
461 | default: | |
462 | return -EINVAL; | |
463 | } | |
464 | } | |
465 | ||
466 | static const struct regulator_ops mt6358_volt_range_ops = { | |
467 | .list_voltage = regulator_list_voltage_linear_range, | |
468 | .map_voltage = regulator_map_voltage_linear_range, | |
469 | .set_voltage_sel = regulator_set_voltage_sel_regmap, | |
470 | .get_voltage_sel = mt6358_get_buck_voltage_sel, | |
471 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
472 | .enable = regulator_enable_regmap, | |
473 | .disable = regulator_disable_regmap, | |
474 | .is_enabled = regulator_is_enabled_regmap, | |
475 | .get_status = mt6358_get_status, | |
476 | .set_mode = mt6358_regulator_set_mode, | |
477 | .get_mode = mt6358_regulator_get_mode, | |
478 | }; | |
479 | ||
480 | static const struct regulator_ops mt6358_volt_table_ops = { | |
481 | .list_voltage = regulator_list_voltage_table, | |
482 | .map_voltage = regulator_map_voltage_iterate, | |
483 | .set_voltage_sel = mt6358_set_voltage_sel, | |
484 | .get_voltage_sel = mt6358_get_voltage_sel, | |
485 | .set_voltage_time_sel = regulator_set_voltage_time_sel, | |
486 | .enable = regulator_enable_regmap, | |
487 | .disable = regulator_disable_regmap, | |
488 | .is_enabled = regulator_is_enabled_regmap, | |
489 | .get_status = mt6358_get_status, | |
490 | }; | |
491 | ||
492 | static const struct regulator_ops mt6358_volt_fixed_ops = { | |
493 | .list_voltage = regulator_list_voltage_linear, | |
494 | .enable = regulator_enable_regmap, | |
495 | .disable = regulator_disable_regmap, | |
496 | .is_enabled = regulator_is_enabled_regmap, | |
497 | .get_status = mt6358_get_status, | |
498 | }; | |
499 | ||
500 | /* The array is indexed by id(MT6358_ID_XXX) */ | |
501 | static struct mt6358_regulator_info mt6358_regulators[] = { | |
502 | MT6358_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500, | |
503 | buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f, | |
b99b7b79 | 504 | MT6358_VDRAM1_ANA_CON0, 8), |
f67ff1bd HHW |
505 | MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250, |
506 | buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f, | |
b99b7b79 | 507 | MT6358_VCORE_VGPU_ANA_CON0, 1), |
f0e3c626 JW |
508 | MT6358_BUCK("buck_vcore_sshub", VCORE_SSHUB, 500000, 1293750, 6250, |
509 | buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_SSHUB_ELR0, 0x7f, | |
510 | MT6358_VCORE_VGPU_ANA_CON0, 1), | |
f67ff1bd | 511 | MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, |
b99b7b79 | 512 | buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, |
f67ff1bd HHW |
513 | MT6358_VPA_ANA_CON0, 3), |
514 | MT6358_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250, | |
515 | buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f, | |
b99b7b79 | 516 | MT6358_VPROC_ANA_CON0, 1), |
f67ff1bd HHW |
517 | MT6358_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250, |
518 | buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f, | |
b99b7b79 | 519 | MT6358_VPROC_ANA_CON0, 2), |
f67ff1bd | 520 | MT6358_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250, |
b99b7b79 | 521 | buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, |
f67ff1bd HHW |
522 | MT6358_VCORE_VGPU_ANA_CON0, 2), |
523 | MT6358_BUCK("buck_vs2", VS2, 500000, 2087500, 12500, | |
b99b7b79 | 524 | buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, |
f67ff1bd HHW |
525 | MT6358_VS2_ANA_CON0, 8), |
526 | MT6358_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250, | |
527 | buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, | |
b99b7b79 | 528 | MT6358_VMODEM_ANA_CON0, 8), |
f67ff1bd | 529 | MT6358_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500, |
b99b7b79 | 530 | buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, |
f67ff1bd HHW |
531 | MT6358_VS1_ANA_CON0, 8), |
532 | MT6358_REG_FIXED("ldo_vrf12", VRF12, | |
533 | MT6358_LDO_VRF12_CON0, 0, 1200000), | |
534 | MT6358_REG_FIXED("ldo_vio18", VIO18, | |
535 | MT6358_LDO_VIO18_CON0, 0, 1800000), | |
536 | MT6358_REG_FIXED("ldo_vcamio", VCAMIO, | |
537 | MT6358_LDO_VCAMIO_CON0, 0, 1800000), | |
538 | MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000), | |
539 | MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000), | |
540 | MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000), | |
541 | MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000), | |
542 | MT6358_REG_FIXED("ldo_vaux18", VAUX18, | |
543 | MT6358_LDO_VAUX18_CON0, 0, 1800000), | |
544 | MT6358_REG_FIXED("ldo_vbif28", VBIF28, | |
545 | MT6358_LDO_VBIF28_CON0, 0, 2800000), | |
546 | MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000), | |
547 | MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000), | |
548 | MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000), | |
549 | MT6358_REG_FIXED("ldo_vaud28", VAUD28, | |
550 | MT6358_LDO_VAUD28_CON0, 0, 2800000), | |
551 | MT6358_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx, | |
b99b7b79 | 552 | MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0xf), |
f67ff1bd | 553 | MT6358_LDO("ldo_vsim1", VSIM1, vsim_voltages, vsim_idx, |
b99b7b79 | 554 | MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00), |
f67ff1bd | 555 | MT6358_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx, |
b99b7b79 | 556 | MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00), |
f67ff1bd | 557 | MT6358_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx, |
b99b7b79 | 558 | MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700), |
f67ff1bd | 559 | MT6358_LDO("ldo_vcamd", VCAMD, vcamd_voltages, vcamd_idx, |
b99b7b79 | 560 | MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00), |
f67ff1bd | 561 | MT6358_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx, |
b99b7b79 | 562 | MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00), |
f67ff1bd | 563 | MT6358_LDO("ldo_vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx, |
b99b7b79 | 564 | MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700), |
f67ff1bd | 565 | MT6358_LDO("ldo_vcama1", VCAMA1, vcama_voltages, vcama_idx, |
b99b7b79 | 566 | MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00), |
f67ff1bd | 567 | MT6358_LDO("ldo_vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx, |
b99b7b79 | 568 | MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700), |
f67ff1bd HHW |
569 | MT6358_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages, |
570 | vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0, | |
b99b7b79 | 571 | 0, MT6358_VCN33_ANA_CON0, 0x300), |
f67ff1bd HHW |
572 | MT6358_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages, |
573 | vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1, | |
b99b7b79 | 574 | 0, MT6358_VCN33_ANA_CON0, 0x300), |
f67ff1bd | 575 | MT6358_LDO("ldo_vcama2", VCAMA2, vcama_voltages, vcama_idx, |
b99b7b79 | 576 | MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00), |
f67ff1bd | 577 | MT6358_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx, |
b99b7b79 | 578 | MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00), |
f67ff1bd HHW |
579 | MT6358_LDO("ldo_vldo28", VLDO28, vldo28_voltages, vldo28_idx, |
580 | MT6358_LDO_VLDO28_CON0_0, 0, | |
b99b7b79 | 581 | MT6358_VLDO28_ANA_CON0, 0x300), |
f67ff1bd | 582 | MT6358_LDO("ldo_vsim2", VSIM2, vsim_voltages, vsim_idx, |
b99b7b79 | 583 | MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00), |
f67ff1bd | 584 | MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250, |
b99b7b79 | 585 | buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, |
f67ff1bd HHW |
586 | MT6358_LDO_VSRAM_CON0, 0x7f), |
587 | MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250, | |
b99b7b79 | 588 | buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, |
f67ff1bd | 589 | MT6358_LDO_VSRAM_CON2, 0x7f), |
f0e3c626 JW |
590 | MT6358_LDO1("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, 500000, |
591 | 1293750, 6250, buck_volt_range1, | |
592 | MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f, | |
593 | MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f), | |
f67ff1bd | 594 | MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250, |
b99b7b79 | 595 | buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, |
f67ff1bd HHW |
596 | MT6358_LDO_VSRAM_CON3, 0x7f), |
597 | MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250, | |
b99b7b79 | 598 | buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, |
f67ff1bd HHW |
599 | MT6358_LDO_VSRAM_CON1, 0x7f), |
600 | }; | |
601 | ||
f0e3c626 JW |
602 | /* The array is indexed by id(MT6366_ID_XXX) */ |
603 | static struct mt6358_regulator_info mt6366_regulators[] = { | |
604 | MT6366_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500, | |
605 | buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f, | |
606 | MT6358_VDRAM1_ANA_CON0, 8), | |
607 | MT6366_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250, | |
608 | buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f, | |
609 | MT6358_VCORE_VGPU_ANA_CON0, 1), | |
610 | MT6366_BUCK("buck_vcore_sshub", VCORE_SSHUB, 500000, 1293750, 6250, | |
611 | buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_SSHUB_ELR0, 0x7f, | |
612 | MT6358_VCORE_VGPU_ANA_CON0, 1), | |
613 | MT6366_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, | |
614 | buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, | |
615 | MT6358_VPA_ANA_CON0, 3), | |
616 | MT6366_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250, | |
617 | buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f, | |
618 | MT6358_VPROC_ANA_CON0, 1), | |
619 | MT6366_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250, | |
620 | buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f, | |
621 | MT6358_VPROC_ANA_CON0, 2), | |
622 | MT6366_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250, | |
623 | buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, | |
624 | MT6358_VCORE_VGPU_ANA_CON0, 2), | |
625 | MT6366_BUCK("buck_vs2", VS2, 500000, 2087500, 12500, | |
626 | buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, | |
627 | MT6358_VS2_ANA_CON0, 8), | |
628 | MT6366_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250, | |
629 | buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, | |
630 | MT6358_VMODEM_ANA_CON0, 8), | |
631 | MT6366_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500, | |
632 | buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, | |
633 | MT6358_VS1_ANA_CON0, 8), | |
634 | MT6366_REG_FIXED("ldo_vrf12", VRF12, | |
635 | MT6358_LDO_VRF12_CON0, 0, 1200000), | |
636 | MT6366_REG_FIXED("ldo_vio18", VIO18, | |
637 | MT6358_LDO_VIO18_CON0, 0, 1800000), | |
638 | MT6366_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000), | |
639 | MT6366_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000), | |
640 | MT6366_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000), | |
641 | MT6366_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000), | |
642 | MT6366_REG_FIXED("ldo_vaux18", VAUX18, | |
643 | MT6358_LDO_VAUX18_CON0, 0, 1800000), | |
644 | MT6366_REG_FIXED("ldo_vbif28", VBIF28, | |
645 | MT6358_LDO_VBIF28_CON0, 0, 2800000), | |
646 | MT6366_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000), | |
647 | MT6366_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000), | |
648 | MT6366_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000), | |
649 | MT6366_REG_FIXED("ldo_vaud28", VAUD28, | |
650 | MT6358_LDO_VAUD28_CON0, 0, 2800000), | |
651 | MT6366_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx, | |
652 | MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10), | |
653 | MT6366_LDO("ldo_vsim1", VSIM1, vsim_voltages, vsim_idx, | |
654 | MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00), | |
655 | MT6366_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx, | |
656 | MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00), | |
657 | MT6366_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx, | |
658 | MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700), | |
659 | MT6366_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx, | |
660 | MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00), | |
661 | MT6366_LDO("ldo_vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx, | |
662 | MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700), | |
663 | MT6366_LDO("ldo_vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx, | |
664 | MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700), | |
665 | MT6366_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages, | |
666 | vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0, | |
667 | 0, MT6358_VCN33_ANA_CON0, 0x300), | |
668 | MT6366_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages, | |
669 | vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1, | |
670 | 0, MT6358_VCN33_ANA_CON0, 0x300), | |
671 | MT6366_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx, | |
672 | MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00), | |
673 | MT6366_LDO("ldo_vsim2", VSIM2, vsim_voltages, vsim_idx, | |
674 | MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00), | |
675 | MT6366_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250, | |
676 | buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, | |
677 | MT6358_LDO_VSRAM_CON0, 0x7f), | |
678 | MT6366_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250, | |
679 | buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, | |
680 | MT6358_LDO_VSRAM_CON2, 0x7f), | |
681 | MT6366_LDO1("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, 500000, | |
682 | 1293750, 6250, buck_volt_range1, | |
683 | MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f, | |
684 | MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1, 0x7f), | |
685 | MT6366_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250, | |
686 | buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, | |
687 | MT6358_LDO_VSRAM_CON3, 0x7f), | |
688 | MT6366_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250, | |
689 | buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, | |
690 | MT6358_LDO_VSRAM_CON1, 0x7f), | |
691 | }; | |
692 | ||
f67ff1bd HHW |
693 | static int mt6358_regulator_probe(struct platform_device *pdev) |
694 | { | |
695 | struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); | |
696 | struct regulator_config config = {}; | |
697 | struct regulator_dev *rdev; | |
f0e3c626 JW |
698 | struct mt6358_regulator_info *mt6358_info; |
699 | int i, max_regulator; | |
700 | ||
701 | if (mt6397->chip_id == MT6366_CHIP_ID) { | |
702 | max_regulator = MT6366_MAX_REGULATOR; | |
703 | mt6358_info = mt6366_regulators; | |
704 | } else { | |
705 | max_regulator = MT6358_MAX_REGULATOR; | |
706 | mt6358_info = mt6358_regulators; | |
707 | } | |
f67ff1bd | 708 | |
f0e3c626 | 709 | for (i = 0; i < max_regulator; i++) { |
f67ff1bd | 710 | config.dev = &pdev->dev; |
f0e3c626 | 711 | config.driver_data = &mt6358_info[i]; |
f67ff1bd HHW |
712 | config.regmap = mt6397->regmap; |
713 | ||
714 | rdev = devm_regulator_register(&pdev->dev, | |
f0e3c626 | 715 | &mt6358_info[i].desc, |
f67ff1bd HHW |
716 | &config); |
717 | if (IS_ERR(rdev)) { | |
718 | dev_err(&pdev->dev, "failed to register %s\n", | |
f0e3c626 | 719 | mt6358_info[i].desc.name); |
f67ff1bd HHW |
720 | return PTR_ERR(rdev); |
721 | } | |
722 | } | |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
727 | static const struct platform_device_id mt6358_platform_ids[] = { | |
728 | {"mt6358-regulator", 0}, | |
729 | { /* sentinel */ }, | |
730 | }; | |
731 | MODULE_DEVICE_TABLE(platform, mt6358_platform_ids); | |
732 | ||
733 | static struct platform_driver mt6358_regulator_driver = { | |
734 | .driver = { | |
735 | .name = "mt6358-regulator", | |
736 | }, | |
737 | .probe = mt6358_regulator_probe, | |
738 | .id_table = mt6358_platform_ids, | |
739 | }; | |
740 | ||
741 | module_platform_driver(mt6358_regulator_driver); | |
742 | ||
743 | MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>"); | |
744 | MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6358 PMIC"); | |
745 | MODULE_LICENSE("GPL"); |