[linux-2.6-block.git] / drivers / regulator / lp8788-ldo.c

/*
 * TI LP8788 MFD - ldo regulator driver
 *
 * Copyright 2012 Texas Instruments
 *
 * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/regulator/driver.h>
#include <linux/gpio/consumer.h>
#include <linux/mfd/lp8788.h>

/* register address */
#define LP8788_EN_LDO_A			0x0D	/* DLDO 1 ~ 8 */
#define LP8788_EN_LDO_B			0x0E	/* DLDO 9 ~ 12, ALDO 1 ~ 4 */
#define LP8788_EN_LDO_C			0x0F	/* ALDO 5 ~ 10 */
#define LP8788_EN_SEL			0x10
#define LP8788_DLDO1_VOUT		0x2E
#define LP8788_DLDO2_VOUT		0x2F
#define LP8788_DLDO3_VOUT		0x30
#define LP8788_DLDO4_VOUT		0x31
#define LP8788_DLDO5_VOUT		0x32
#define LP8788_DLDO6_VOUT		0x33
#define LP8788_DLDO7_VOUT		0x34
#define LP8788_DLDO8_VOUT		0x35
#define LP8788_DLDO9_VOUT		0x36
#define LP8788_DLDO10_VOUT		0x37
#define LP8788_DLDO11_VOUT		0x38
#define LP8788_DLDO12_VOUT		0x39
#define LP8788_ALDO1_VOUT		0x3A
#define LP8788_ALDO2_VOUT		0x3B
#define LP8788_ALDO3_VOUT		0x3C
#define LP8788_ALDO4_VOUT		0x3D
#define LP8788_ALDO5_VOUT		0x3E
#define LP8788_ALDO6_VOUT		0x3F
#define LP8788_ALDO7_VOUT		0x40
#define LP8788_ALDO8_VOUT		0x41
#define LP8788_ALDO9_VOUT		0x42
#define LP8788_ALDO10_VOUT		0x43
#define LP8788_DLDO1_TIMESTEP		0x44

/* mask/shift bits */
#define LP8788_EN_DLDO1_M		BIT(0)	/* Addr 0Dh ~ 0Fh */
#define LP8788_EN_DLDO2_M		BIT(1)
#define LP8788_EN_DLDO3_M		BIT(2)
#define LP8788_EN_DLDO4_M		BIT(3)
#define LP8788_EN_DLDO5_M		BIT(4)
#define LP8788_EN_DLDO6_M		BIT(5)
#define LP8788_EN_DLDO7_M		BIT(6)
#define LP8788_EN_DLDO8_M		BIT(7)
#define LP8788_EN_DLDO9_M		BIT(0)
#define LP8788_EN_DLDO10_M		BIT(1)
#define LP8788_EN_DLDO11_M		BIT(2)
#define LP8788_EN_DLDO12_M		BIT(3)
#define LP8788_EN_ALDO1_M		BIT(4)
#define LP8788_EN_ALDO2_M		BIT(5)
#define LP8788_EN_ALDO3_M		BIT(6)
#define LP8788_EN_ALDO4_M		BIT(7)
#define LP8788_EN_ALDO5_M		BIT(0)
#define LP8788_EN_ALDO6_M		BIT(1)
#define LP8788_EN_ALDO7_M		BIT(2)
#define LP8788_EN_ALDO8_M		BIT(3)
#define LP8788_EN_ALDO9_M		BIT(4)
#define LP8788_EN_ALDO10_M		BIT(5)
#define LP8788_EN_SEL_DLDO911_M		BIT(0)	/* Addr 10h */
#define LP8788_EN_SEL_DLDO7_M		BIT(1)
#define LP8788_EN_SEL_ALDO7_M		BIT(2)
#define LP8788_EN_SEL_ALDO5_M		BIT(3)
#define LP8788_EN_SEL_ALDO234_M		BIT(4)
#define LP8788_EN_SEL_ALDO1_M		BIT(5)
#define LP8788_VOUT_5BIT_M		0x1F	/* Addr 2Eh ~ 43h */
#define LP8788_VOUT_4BIT_M		0x0F
#define LP8788_VOUT_3BIT_M		0x07
#define LP8788_VOUT_1BIT_M		0x01
#define LP8788_STARTUP_TIME_M		0xF8	/* Addr 44h ~ 59h */
#define LP8788_STARTUP_TIME_S		3

#define ENABLE_TIME_USEC		32

enum lp8788_ldo_id {
	DLDO1,
	DLDO2,
	DLDO3,
	DLDO4,
	DLDO5,
	DLDO6,
	DLDO7,
	DLDO8,
	DLDO9,
	DLDO10,
	DLDO11,
	DLDO12,
	ALDO1,
	ALDO2,
	ALDO3,
	ALDO4,
	ALDO5,
	ALDO6,
	ALDO7,
	ALDO8,
	ALDO9,
	ALDO10,
};

struct lp8788_ldo {
	struct lp8788 *lp;
	struct regulator_desc *desc;
	struct regulator_dev *regulator;
	struct gpio_desc *ena_gpiod;
};

/* DLDO 1, 2, 3, 9 voltage table */
static const int lp8788_dldo1239_vtbl[] = {
	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
	2600000, 2700000, 2800000, 2900000, 3000000, 2850000, 2850000, 2850000,
	2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
	2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
};

/* DLDO 4 voltage table */
static const int lp8788_dldo4_vtbl[] = { 1800000, 3000000 };

/* DLDO 5, 7, 8 and ALDO 6 voltage table */
static const int lp8788_dldo578_aldo6_vtbl[] = {
	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
	2600000, 2700000, 2800000, 2900000, 3000000, 3000000, 3000000, 3000000,
};

/* DLDO 6 voltage table */
static const int lp8788_dldo6_vtbl[] = {
	3000000, 3100000, 3200000, 3300000, 3400000, 3500000, 3600000, 3600000,
};

/* DLDO 10, 11 voltage table */
static const int lp8788_dldo1011_vtbl[] = {
	1100000, 1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000,
	1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000,
};

/* ALDO 1 voltage table */
static const int lp8788_aldo1_vtbl[] = { 1800000, 2850000 };

/* ALDO 7 voltage table */
static const int lp8788_aldo7_vtbl[] = {
	1200000, 1300000, 1400000, 1500000, 1600000, 1700000, 1800000, 1800000,
};

static int lp8788_ldo_enable_time(struct regulator_dev *rdev)
{
	struct lp8788_ldo *ldo = rdev_get_drvdata(rdev);
	enum lp8788_ldo_id id = rdev_get_id(rdev);
	u8 val, addr = LP8788_DLDO1_TIMESTEP + id;

	if (lp8788_read_byte(ldo->lp, addr, &val))
		return -EINVAL;

	val = (val & LP8788_STARTUP_TIME_M) >> LP8788_STARTUP_TIME_S;

	return ENABLE_TIME_USEC * val;
}

static const struct regulator_ops lp8788_ldo_voltage_table_ops = {
	.list_voltage = regulator_list_voltage_table,
	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	.enable = regulator_enable_regmap,
	.disable = regulator_disable_regmap,
	.is_enabled = regulator_is_enabled_regmap,
	.enable_time = lp8788_ldo_enable_time,
};

static const struct regulator_ops lp8788_ldo_voltage_fixed_ops = {
	.list_voltage = regulator_list_voltage_linear,
	.enable = regulator_enable_regmap,
	.disable = regulator_disable_regmap,
	.is_enabled = regulator_is_enabled_regmap,
	.enable_time = lp8788_ldo_enable_time,
};

static struct regulator_desc lp8788_dldo_desc[] = {
	{
		.name = "dldo1",
		.id = DLDO1,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
		.volt_table = lp8788_dldo1239_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO1_VOUT,
		.vsel_mask = LP8788_VOUT_5BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO1_M,
	},
	{
		.name = "dldo2",
		.id = DLDO2,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
		.volt_table = lp8788_dldo1239_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO2_VOUT,
		.vsel_mask = LP8788_VOUT_5BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO2_M,
	},
	{
		.name = "dldo3",
		.id = DLDO3,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
		.volt_table = lp8788_dldo1239_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO3_VOUT,
		.vsel_mask = LP8788_VOUT_5BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO3_M,
	},
	{
		.name = "dldo4",
		.id = DLDO4,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo4_vtbl),
		.volt_table = lp8788_dldo4_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO4_VOUT,
		.vsel_mask = LP8788_VOUT_1BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO4_M,
	},
	{
		.name = "dldo5",
		.id = DLDO5,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
		.volt_table = lp8788_dldo578_aldo6_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO5_VOUT,
		.vsel_mask = LP8788_VOUT_4BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO5_M,
	},
	{
		.name = "dldo6",
		.id = DLDO6,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo6_vtbl),
		.volt_table = lp8788_dldo6_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO6_VOUT,
		.vsel_mask = LP8788_VOUT_3BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO6_M,
	},
	{
		.name = "dldo7",
		.id = DLDO7,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
		.volt_table = lp8788_dldo578_aldo6_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO7_VOUT,
		.vsel_mask = LP8788_VOUT_4BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO7_M,
	},
	{
		.name = "dldo8",
		.id = DLDO8,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
		.volt_table = lp8788_dldo578_aldo6_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO8_VOUT,
		.vsel_mask = LP8788_VOUT_4BIT_M,
		.enable_reg = LP8788_EN_LDO_A,
		.enable_mask = LP8788_EN_DLDO8_M,
	},
	{
		.name = "dldo9",
		.id = DLDO9,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
		.volt_table = lp8788_dldo1239_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO9_VOUT,
		.vsel_mask = LP8788_VOUT_5BIT_M,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_DLDO9_M,
	},
	{
		.name = "dldo10",
		.id = DLDO10,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
		.volt_table = lp8788_dldo1011_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO10_VOUT,
		.vsel_mask = LP8788_VOUT_4BIT_M,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_DLDO10_M,
	},
	{
		.name = "dldo11",
		.id = DLDO11,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
		.volt_table = lp8788_dldo1011_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_DLDO11_VOUT,
		.vsel_mask = LP8788_VOUT_4BIT_M,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_DLDO11_M,
	},
	{
		.name = "dldo12",
		.id = DLDO12,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_DLDO12_M,
		.min_uV = 2500000,
	},
};

static struct regulator_desc lp8788_aldo_desc[] = {
	{
		.name = "aldo1",
		.id = ALDO1,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_aldo1_vtbl),
		.volt_table = lp8788_aldo1_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_ALDO1_VOUT,
		.vsel_mask = LP8788_VOUT_1BIT_M,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_ALDO1_M,
	},
	{
		.name = "aldo2",
		.id = ALDO2,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_ALDO2_M,
		.min_uV = 2850000,
	},
	{
		.name = "aldo3",
		.id = ALDO3,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_ALDO3_M,
		.min_uV = 2850000,
	},
	{
		.name = "aldo4",
		.id = ALDO4,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_B,
		.enable_mask = LP8788_EN_ALDO4_M,
		.min_uV = 2850000,
	},
	{
		.name = "aldo5",
		.id = ALDO5,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_C,
		.enable_mask = LP8788_EN_ALDO5_M,
		.min_uV = 2850000,
	},
	{
		.name = "aldo6",
		.id = ALDO6,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
		.volt_table = lp8788_dldo578_aldo6_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_ALDO6_VOUT,
		.vsel_mask = LP8788_VOUT_4BIT_M,
		.enable_reg = LP8788_EN_LDO_C,
		.enable_mask = LP8788_EN_ALDO6_M,
	},
	{
		.name = "aldo7",
		.id = ALDO7,
		.ops = &lp8788_ldo_voltage_table_ops,
		.n_voltages = ARRAY_SIZE(lp8788_aldo7_vtbl),
		.volt_table = lp8788_aldo7_vtbl,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.vsel_reg = LP8788_ALDO7_VOUT,
		.vsel_mask = LP8788_VOUT_3BIT_M,
		.enable_reg = LP8788_EN_LDO_C,
		.enable_mask = LP8788_EN_ALDO7_M,
	},
	{
		.name = "aldo8",
		.id = ALDO8,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_C,
		.enable_mask = LP8788_EN_ALDO8_M,
		.min_uV = 2500000,
	},
	{
		.name = "aldo9",
		.id = ALDO9,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_C,
		.enable_mask = LP8788_EN_ALDO9_M,
		.min_uV = 2500000,
	},
	{
		.name = "aldo10",
		.id = ALDO10,
		.ops = &lp8788_ldo_voltage_fixed_ops,
		.n_voltages = 1,
		.type = REGULATOR_VOLTAGE,
		.owner = THIS_MODULE,
		.enable_reg = LP8788_EN_LDO_C,
		.enable_mask = LP8788_EN_ALDO10_M,
		.min_uV = 1100000,
	},
};

static int lp8788_config_ldo_enable_mode(struct platform_device *pdev,
					struct lp8788_ldo *ldo,
					enum lp8788_ldo_id id)
{
	struct lp8788 *lp = ldo->lp;
	enum lp8788_ext_ldo_en_id enable_id;
	u8 en_mask[] = {
		[EN_ALDO1]   = LP8788_EN_SEL_ALDO1_M,
		[EN_ALDO234] = LP8788_EN_SEL_ALDO234_M,
		[EN_ALDO5]   = LP8788_EN_SEL_ALDO5_M,
		[EN_ALDO7]   = LP8788_EN_SEL_ALDO7_M,
		[EN_DLDO7]   = LP8788_EN_SEL_DLDO7_M,
		[EN_DLDO911] = LP8788_EN_SEL_DLDO911_M,
	};

	switch (id) {
	case DLDO7:
		enable_id = EN_DLDO7;
		break;
	case DLDO9:
	case DLDO11:
		enable_id = EN_DLDO911;
		break;
	case ALDO1:
		enable_id = EN_ALDO1;
		break;
	case ALDO2 ... ALDO4:
		enable_id = EN_ALDO234;
		break;
	case ALDO5:
		enable_id = EN_ALDO5;
		break;
	case ALDO7:
		enable_id = EN_ALDO7;
		break;
	default:
		return 0;
	}

	/* FIXME: check default mode for GPIO here: high or low? */
	ldo->ena_gpiod = devm_gpiod_get_index_optional(&pdev->dev,
					       "enable",
					       enable_id,
					       GPIOD_OUT_HIGH |
					       GPIOD_FLAGS_BIT_NONEXCLUSIVE);
	if (IS_ERR(ldo->ena_gpiod))
		return PTR_ERR(ldo->ena_gpiod);

	/* if no GPIO for ldo pin, then set default enable mode */
	if (!ldo->ena_gpiod)
		goto set_default_ldo_enable_mode;

	return 0;

set_default_ldo_enable_mode:
	return lp8788_update_bits(lp, LP8788_EN_SEL, en_mask[enable_id], 0);
}

static int lp8788_dldo_probe(struct platform_device *pdev)
{
	struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
	int id = pdev->id;
	struct lp8788_ldo *ldo;
	struct regulator_config cfg = { };
	struct regulator_dev *rdev;
	int ret;

	ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
	if (!ldo)
		return -ENOMEM;

	ldo->lp = lp;
	ret = lp8788_config_ldo_enable_mode(pdev, ldo, id);
	if (ret)
		return ret;

	if (ldo->ena_gpiod)
		cfg.ena_gpiod = ldo->ena_gpiod;

	cfg.dev = pdev->dev.parent;
	cfg.init_data = lp->pdata ? lp->pdata->dldo_data[id] : NULL;
	cfg.driver_data = ldo;
	cfg.regmap = lp->regmap;

	rdev = devm_regulator_register(&pdev->dev, &lp8788_dldo_desc[id], &cfg);
	if (IS_ERR(rdev)) {
		ret = PTR_ERR(rdev);
		dev_err(&pdev->dev, "DLDO%d regulator register err = %d\n",
				id + 1, ret);
		return ret;
	}

	ldo->regulator = rdev;
	platform_set_drvdata(pdev, ldo);

	return 0;
}

static struct platform_driver lp8788_dldo_driver = {
	.probe = lp8788_dldo_probe,
	.driver = {
		.name = LP8788_DEV_DLDO,
	},
};

static int lp8788_aldo_probe(struct platform_device *pdev)
{
	struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
	int id = pdev->id;
	struct lp8788_ldo *ldo;
	struct regulator_config cfg = { };
	struct regulator_dev *rdev;
	int ret;

	ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
	if (!ldo)
		return -ENOMEM;

	ldo->lp = lp;
	ret = lp8788_config_ldo_enable_mode(pdev, ldo, id + ALDO1);
	if (ret)
		return ret;

	if (ldo->ena_gpiod)
		cfg.ena_gpiod = ldo->ena_gpiod;

	cfg.dev = pdev->dev.parent;
	cfg.init_data = lp->pdata ? lp->pdata->aldo_data[id] : NULL;
	cfg.driver_data = ldo;
	cfg.regmap = lp->regmap;

	rdev = devm_regulator_register(&pdev->dev, &lp8788_aldo_desc[id], &cfg);
	if (IS_ERR(rdev)) {
		ret = PTR_ERR(rdev);
		dev_err(&pdev->dev, "ALDO%d regulator register err = %d\n",
				id + 1, ret);
		return ret;
	}

	ldo->regulator = rdev;
	platform_set_drvdata(pdev, ldo);

	return 0;
}

static struct platform_driver lp8788_aldo_driver = {
	.probe = lp8788_aldo_probe,
	.driver = {
		.name = LP8788_DEV_ALDO,
	},
};

static struct platform_driver * const drivers[] = {
	&lp8788_dldo_driver,
	&lp8788_aldo_driver,
};

static int __init lp8788_ldo_init(void)
{
	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
}
subsys_initcall(lp8788_ldo_init);

static void __exit lp8788_ldo_exit(void)
{
	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
}
module_exit(lp8788_ldo_exit);

MODULE_DESCRIPTION("TI LP8788 LDO Driver");
MODULE_AUTHOR("Milo Kim");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:lp8788-dldo");
MODULE_ALIAS("platform:lp8788-aldo");
Commit	Line	Data
ade7515f KM	1	/*
	2	* TI LP8788 MFD - ldo regulator driver
	3	*
	4	* Copyright 2012 Texas Instruments
	5	*
	6	* Author: Milo(Woogyom) Kim <milo.kim@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	*/
	13
	14	#include <linux/module.h>
	15	#include <linux/slab.h>
	16	#include <linux/err.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/regulator/driver.h>
2468f0d5	19	#include <linux/gpio/consumer.h>
ade7515f KM	20	#include <linux/mfd/lp8788.h>
	21
	22	/* register address */
	23	#define LP8788_EN_LDO_A 0x0D /* DLDO 1 ~ 8 */
	24	#define LP8788_EN_LDO_B 0x0E /* DLDO 9 ~ 12, ALDO 1 ~ 4 */
	25	#define LP8788_EN_LDO_C 0x0F /* ALDO 5 ~ 10 */
	26	#define LP8788_EN_SEL 0x10
	27	#define LP8788_DLDO1_VOUT 0x2E
	28	#define LP8788_DLDO2_VOUT 0x2F
	29	#define LP8788_DLDO3_VOUT 0x30
	30	#define LP8788_DLDO4_VOUT 0x31
	31	#define LP8788_DLDO5_VOUT 0x32
	32	#define LP8788_DLDO6_VOUT 0x33
	33	#define LP8788_DLDO7_VOUT 0x34
	34	#define LP8788_DLDO8_VOUT 0x35
	35	#define LP8788_DLDO9_VOUT 0x36
	36	#define LP8788_DLDO10_VOUT 0x37
	37	#define LP8788_DLDO11_VOUT 0x38
	38	#define LP8788_DLDO12_VOUT 0x39
	39	#define LP8788_ALDO1_VOUT 0x3A
	40	#define LP8788_ALDO2_VOUT 0x3B
	41	#define LP8788_ALDO3_VOUT 0x3C
	42	#define LP8788_ALDO4_VOUT 0x3D
	43	#define LP8788_ALDO5_VOUT 0x3E
	44	#define LP8788_ALDO6_VOUT 0x3F
	45	#define LP8788_ALDO7_VOUT 0x40
	46	#define LP8788_ALDO8_VOUT 0x41
	47	#define LP8788_ALDO9_VOUT 0x42
	48	#define LP8788_ALDO10_VOUT 0x43
	49	#define LP8788_DLDO1_TIMESTEP 0x44
	50
	51	/* mask/shift bits */
	52	#define LP8788_EN_DLDO1_M BIT(0) /* Addr 0Dh ~ 0Fh */
	53	#define LP8788_EN_DLDO2_M BIT(1)
	54	#define LP8788_EN_DLDO3_M BIT(2)
	55	#define LP8788_EN_DLDO4_M BIT(3)
	56	#define LP8788_EN_DLDO5_M BIT(4)
	57	#define LP8788_EN_DLDO6_M BIT(5)
	58	#define LP8788_EN_DLDO7_M BIT(6)
	59	#define LP8788_EN_DLDO8_M BIT(7)
	60	#define LP8788_EN_DLDO9_M BIT(0)
	61	#define LP8788_EN_DLDO10_M BIT(1)
	62	#define LP8788_EN_DLDO11_M BIT(2)
	63	#define LP8788_EN_DLDO12_M BIT(3)
	64	#define LP8788_EN_ALDO1_M BIT(4)
	65	#define LP8788_EN_ALDO2_M BIT(5)
	66	#define LP8788_EN_ALDO3_M BIT(6)
	67	#define LP8788_EN_ALDO4_M BIT(7)
	68	#define LP8788_EN_ALDO5_M BIT(0)
	69	#define LP8788_EN_ALDO6_M BIT(1)
	70	#define LP8788_EN_ALDO7_M BIT(2)
	71	#define LP8788_EN_ALDO8_M BIT(3)
	72	#define LP8788_EN_ALDO9_M BIT(4)
	73	#define LP8788_EN_ALDO10_M BIT(5)
	74	#define LP8788_EN_SEL_DLDO911_M BIT(0) /* Addr 10h */
	75	#define LP8788_EN_SEL_DLDO7_M BIT(1)
	76	#define LP8788_EN_SEL_ALDO7_M BIT(2)
	77	#define LP8788_EN_SEL_ALDO5_M BIT(3)
	78	#define LP8788_EN_SEL_ALDO234_M BIT(4)
	79	#define LP8788_EN_SEL_ALDO1_M BIT(5)
	80	#define LP8788_VOUT_5BIT_M 0x1F /* Addr 2Eh ~ 43h */
	81	#define LP8788_VOUT_4BIT_M 0x0F
	82	#define LP8788_VOUT_3BIT_M 0x07
	83	#define LP8788_VOUT_1BIT_M 0x01
84	#define LP8788_STARTUP_TIME_M 0xF8 /* Addr 44h ~ 59h */
85	#define LP8788_STARTUP_TIME_S 3
86
87	#define ENABLE_TIME_USEC 32
ade7515f	88
ade7515f KM	89	enum lp8788_ldo_id {
	90	DLDO1,
	91	DLDO2,
	92	DLDO3,
	93	DLDO4,
	94	DLDO5,
	95	DLDO6,
	96	DLDO7,
	97	DLDO8,
	98	DLDO9,
	99	DLDO10,
	100	DLDO11,
	101	DLDO12,
	102	ALDO1,
	103	ALDO2,
	104	ALDO3,
	105	ALDO4,
	106	ALDO5,
	107	ALDO6,
	108	ALDO7,
	109	ALDO8,
	110	ALDO9,
	111	ALDO10,
	112	};
	113
	114	struct lp8788_ldo {
	115	struct lp8788 *lp;
	116	struct regulator_desc *desc;
	117	struct regulator_dev *regulator;
2468f0d5	118	struct gpio_desc *ena_gpiod;
ade7515f KM	119	};
	120
	121	/* DLDO 1, 2, 3, 9 voltage table */
4e92920b	122	static const int lp8788_dldo1239_vtbl[] = {
ade7515f KM	123	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
	124	2600000, 2700000, 2800000, 2900000, 3000000, 2850000, 2850000, 2850000,
	125	2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
	126	2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
	127	};
	128
	129	/* DLDO 4 voltage table */
	130	static const int lp8788_dldo4_vtbl[] = { 1800000, 3000000 };
	131
	132	/* DLDO 5, 7, 8 and ALDO 6 voltage table */
	133	static const int lp8788_dldo578_aldo6_vtbl[] = {
	134	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
	135	2600000, 2700000, 2800000, 2900000, 3000000, 3000000, 3000000, 3000000,
	136	};
	137
	138	/* DLDO 6 voltage table */
	139	static const int lp8788_dldo6_vtbl[] = {
	140	3000000, 3100000, 3200000, 3300000, 3400000, 3500000, 3600000, 3600000,
	141	};
	142
	143	/* DLDO 10, 11 voltage table */
	144	static const int lp8788_dldo1011_vtbl[] = {
	145	1100000, 1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000,
	146	1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000,
	147	};
	148
	149	/* ALDO 1 voltage table */
	150	static const int lp8788_aldo1_vtbl[] = { 1800000, 2850000 };
	151
	152	/* ALDO 7 voltage table */
	153	static const int lp8788_aldo7_vtbl[] = {
	154	1200000, 1300000, 1400000, 1500000, 1600000, 1700000, 1800000, 1800000,
	155	};
	156
ade7515f KM	157	static int lp8788_ldo_enable_time(struct regulator_dev *rdev)
	158	{
	159	struct lp8788_ldo *ldo = rdev_get_drvdata(rdev);
	160	enum lp8788_ldo_id id = rdev_get_id(rdev);
	161	u8 val, addr = LP8788_DLDO1_TIMESTEP + id;
	162
	163	if (lp8788_read_byte(ldo->lp, addr, &val))
	164	return -EINVAL;
	165
	166	val = (val & LP8788_STARTUP_TIME_M) >> LP8788_STARTUP_TIME_S;
	167
	168	return ENABLE_TIME_USEC * val;
	169	}
	170
95dfead1	171	static const struct regulator_ops lp8788_ldo_voltage_table_ops = {
ade7515f KM	172	.list_voltage = regulator_list_voltage_table,
	173	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	174	.get_voltage_sel = regulator_get_voltage_sel_regmap,
407945fd KM	175	.enable = regulator_enable_regmap,
	176	.disable = regulator_disable_regmap,
	177	.is_enabled = regulator_is_enabled_regmap,
ade7515f KM	178	.enable_time = lp8788_ldo_enable_time,
	179	};
	180
95dfead1	181	static const struct regulator_ops lp8788_ldo_voltage_fixed_ops = {
b5366e5e	182	.list_voltage = regulator_list_voltage_linear,
407945fd KM	183	.enable = regulator_enable_regmap,
	184	.disable = regulator_disable_regmap,
	185	.is_enabled = regulator_is_enabled_regmap,
ade7515f KM	186	.enable_time = lp8788_ldo_enable_time,
	187	};
	188
	189	static struct regulator_desc lp8788_dldo_desc[] = {
	190	{
	191	.name = "dldo1",
	192	.id = DLDO1,
	193	.ops = &lp8788_ldo_voltage_table_ops,
	194	.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
	195	.volt_table = lp8788_dldo1239_vtbl,
	196	.type = REGULATOR_VOLTAGE,
	197	.owner = THIS_MODULE,
	198	.vsel_reg = LP8788_DLDO1_VOUT,
	199	.vsel_mask = LP8788_VOUT_5BIT_M,
	200	.enable_reg = LP8788_EN_LDO_A,
	201	.enable_mask = LP8788_EN_DLDO1_M,
	202	},
	203	{
	204	.name = "dldo2",
	205	.id = DLDO2,
	206	.ops = &lp8788_ldo_voltage_table_ops,
	207	.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
	208	.volt_table = lp8788_dldo1239_vtbl,
	209	.type = REGULATOR_VOLTAGE,
	210	.owner = THIS_MODULE,
	211	.vsel_reg = LP8788_DLDO2_VOUT,
	212	.vsel_mask = LP8788_VOUT_5BIT_M,
	213	.enable_reg = LP8788_EN_LDO_A,
	214	.enable_mask = LP8788_EN_DLDO2_M,
	215	},
	216	{
	217	.name = "dldo3",
	218	.id = DLDO3,
	219	.ops = &lp8788_ldo_voltage_table_ops,
	220	.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
	221	.volt_table = lp8788_dldo1239_vtbl,
	222	.type = REGULATOR_VOLTAGE,
	223	.owner = THIS_MODULE,
	224	.vsel_reg = LP8788_DLDO3_VOUT,
	225	.vsel_mask = LP8788_VOUT_5BIT_M,
	226	.enable_reg = LP8788_EN_LDO_A,
	227	.enable_mask = LP8788_EN_DLDO3_M,
	228	},
	229	{
	230	.name = "dldo4",
	231	.id = DLDO4,
	232	.ops = &lp8788_ldo_voltage_table_ops,
	233	.n_voltages = ARRAY_SIZE(lp8788_dldo4_vtbl),
	234	.volt_table = lp8788_dldo4_vtbl,
	235	.type = REGULATOR_VOLTAGE,
	236	.owner = THIS_MODULE,
	237	.vsel_reg = LP8788_DLDO4_VOUT,
	238	.vsel_mask = LP8788_VOUT_1BIT_M,
	239	.enable_reg = LP8788_EN_LDO_A,
	240	.enable_mask = LP8788_EN_DLDO4_M,
	241	},
	242	{
	243	.name = "dldo5",
	244	.id = DLDO5,
	245	.ops = &lp8788_ldo_voltage_table_ops,
	246	.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
	247	.volt_table = lp8788_dldo578_aldo6_vtbl,
	248	.type = REGULATOR_VOLTAGE,
	249	.owner = THIS_MODULE,
250	.vsel_reg = LP8788_DLDO5_VOUT,
251	.vsel_mask = LP8788_VOUT_4BIT_M,
252	.enable_reg = LP8788_EN_LDO_A,
253	.enable_mask = LP8788_EN_DLDO5_M,
254	},
255	{
256	.name = "dldo6",
257	.id = DLDO6,
258	.ops = &lp8788_ldo_voltage_table_ops,
259	.n_voltages = ARRAY_SIZE(lp8788_dldo6_vtbl),
260	.volt_table = lp8788_dldo6_vtbl,
261	.type = REGULATOR_VOLTAGE,
262	.owner = THIS_MODULE,
263	.vsel_reg = LP8788_DLDO6_VOUT,
264	.vsel_mask = LP8788_VOUT_3BIT_M,
265	.enable_reg = LP8788_EN_LDO_A,
266	.enable_mask = LP8788_EN_DLDO6_M,
267	},
268	{
269	.name = "dldo7",
270	.id = DLDO7,
271	.ops = &lp8788_ldo_voltage_table_ops,
272	.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
273	.volt_table = lp8788_dldo578_aldo6_vtbl,
274	.type = REGULATOR_VOLTAGE,
275	.owner = THIS_MODULE,
276	.vsel_reg = LP8788_DLDO7_VOUT,
277	.vsel_mask = LP8788_VOUT_4BIT_M,
278	.enable_reg = LP8788_EN_LDO_A,
279	.enable_mask = LP8788_EN_DLDO7_M,
280	},
281	{
282	.name = "dldo8",
283	.id = DLDO8,
284	.ops = &lp8788_ldo_voltage_table_ops,
285	.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
286	.volt_table = lp8788_dldo578_aldo6_vtbl,
287	.type = REGULATOR_VOLTAGE,
288	.owner = THIS_MODULE,
289	.vsel_reg = LP8788_DLDO8_VOUT,
290	.vsel_mask = LP8788_VOUT_4BIT_M,
291	.enable_reg = LP8788_EN_LDO_A,
292	.enable_mask = LP8788_EN_DLDO8_M,
293	},
294	{
295	.name = "dldo9",
296	.id = DLDO9,
297	.ops = &lp8788_ldo_voltage_table_ops,
298	.n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
299	.volt_table = lp8788_dldo1239_vtbl,
300	.type = REGULATOR_VOLTAGE,
301	.owner = THIS_MODULE,
302	.vsel_reg = LP8788_DLDO9_VOUT,
303	.vsel_mask = LP8788_VOUT_5BIT_M,
304	.enable_reg = LP8788_EN_LDO_B,
305	.enable_mask = LP8788_EN_DLDO9_M,
306	},
307	{
308	.name = "dldo10",
309	.id = DLDO10,
310	.ops = &lp8788_ldo_voltage_table_ops,
311	.n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
312	.volt_table = lp8788_dldo1011_vtbl,
313	.type = REGULATOR_VOLTAGE,
314	.owner = THIS_MODULE,
315	.vsel_reg = LP8788_DLDO10_VOUT,
316	.vsel_mask = LP8788_VOUT_4BIT_M,
317	.enable_reg = LP8788_EN_LDO_B,
318	.enable_mask = LP8788_EN_DLDO10_M,
319	},
320	{
321	.name = "dldo11",
322	.id = DLDO11,
323	.ops = &lp8788_ldo_voltage_table_ops,
324	.n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
325	.volt_table = lp8788_dldo1011_vtbl,
326	.type = REGULATOR_VOLTAGE,
327	.owner = THIS_MODULE,
328	.vsel_reg = LP8788_DLDO11_VOUT,
329	.vsel_mask = LP8788_VOUT_4BIT_M,
330	.enable_reg = LP8788_EN_LDO_B,
331	.enable_mask = LP8788_EN_DLDO11_M,
332	},
333	{
334	.name = "dldo12",
335	.id = DLDO12,
336	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	337	.n_voltages = 1,
ade7515f KM	338	.type = REGULATOR_VOLTAGE,
	339	.owner = THIS_MODULE,
	340	.enable_reg = LP8788_EN_LDO_B,
	341	.enable_mask = LP8788_EN_DLDO12_M,
b5366e5e	342	.min_uV = 2500000,
ade7515f KM	343	},
	344	};
	345
	346	static struct regulator_desc lp8788_aldo_desc[] = {
	347	{
	348	.name = "aldo1",
	349	.id = ALDO1,
	350	.ops = &lp8788_ldo_voltage_table_ops,
	351	.n_voltages = ARRAY_SIZE(lp8788_aldo1_vtbl),
	352	.volt_table = lp8788_aldo1_vtbl,
	353	.type = REGULATOR_VOLTAGE,
	354	.owner = THIS_MODULE,
	355	.vsel_reg = LP8788_ALDO1_VOUT,
	356	.vsel_mask = LP8788_VOUT_1BIT_M,
	357	.enable_reg = LP8788_EN_LDO_B,
	358	.enable_mask = LP8788_EN_ALDO1_M,
	359	},
	360	{
	361	.name = "aldo2",
	362	.id = ALDO2,
	363	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	364	.n_voltages = 1,
ade7515f KM	365	.type = REGULATOR_VOLTAGE,
	366	.owner = THIS_MODULE,
	367	.enable_reg = LP8788_EN_LDO_B,
	368	.enable_mask = LP8788_EN_ALDO2_M,
b5366e5e	369	.min_uV = 2850000,
ade7515f KM	370	},
	371	{
	372	.name = "aldo3",
	373	.id = ALDO3,
	374	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	375	.n_voltages = 1,
ade7515f KM	376	.type = REGULATOR_VOLTAGE,
	377	.owner = THIS_MODULE,
	378	.enable_reg = LP8788_EN_LDO_B,
	379	.enable_mask = LP8788_EN_ALDO3_M,
b5366e5e	380	.min_uV = 2850000,
ade7515f KM	381	},
	382	{
	383	.name = "aldo4",
	384	.id = ALDO4,
	385	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	386	.n_voltages = 1,
ade7515f KM	387	.type = REGULATOR_VOLTAGE,
	388	.owner = THIS_MODULE,
	389	.enable_reg = LP8788_EN_LDO_B,
	390	.enable_mask = LP8788_EN_ALDO4_M,
b5366e5e	391	.min_uV = 2850000,
ade7515f KM	392	},
	393	{
	394	.name = "aldo5",
	395	.id = ALDO5,
	396	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	397	.n_voltages = 1,
ade7515f KM	398	.type = REGULATOR_VOLTAGE,
	399	.owner = THIS_MODULE,
	400	.enable_reg = LP8788_EN_LDO_C,
	401	.enable_mask = LP8788_EN_ALDO5_M,
b5366e5e	402	.min_uV = 2850000,
ade7515f KM	403	},
	404	{
	405	.name = "aldo6",
	406	.id = ALDO6,
	407	.ops = &lp8788_ldo_voltage_table_ops,
	408	.n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
	409	.volt_table = lp8788_dldo578_aldo6_vtbl,
	410	.type = REGULATOR_VOLTAGE,
	411	.owner = THIS_MODULE,
	412	.vsel_reg = LP8788_ALDO6_VOUT,
	413	.vsel_mask = LP8788_VOUT_4BIT_M,
	414	.enable_reg = LP8788_EN_LDO_C,
	415	.enable_mask = LP8788_EN_ALDO6_M,
	416	},
	417	{
	418	.name = "aldo7",
	419	.id = ALDO7,
	420	.ops = &lp8788_ldo_voltage_table_ops,
	421	.n_voltages = ARRAY_SIZE(lp8788_aldo7_vtbl),
	422	.volt_table = lp8788_aldo7_vtbl,
	423	.type = REGULATOR_VOLTAGE,
	424	.owner = THIS_MODULE,
	425	.vsel_reg = LP8788_ALDO7_VOUT,
	426	.vsel_mask = LP8788_VOUT_3BIT_M,
	427	.enable_reg = LP8788_EN_LDO_C,
	428	.enable_mask = LP8788_EN_ALDO7_M,
	429	},
	430	{
	431	.name = "aldo8",
	432	.id = ALDO8,
	433	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	434	.n_voltages = 1,
ade7515f KM	435	.type = REGULATOR_VOLTAGE,
	436	.owner = THIS_MODULE,
	437	.enable_reg = LP8788_EN_LDO_C,
	438	.enable_mask = LP8788_EN_ALDO8_M,
b5366e5e	439	.min_uV = 2500000,
ade7515f KM	440	},
	441	{
	442	.name = "aldo9",
	443	.id = ALDO9,
	444	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	445	.n_voltages = 1,
ade7515f KM	446	.type = REGULATOR_VOLTAGE,
	447	.owner = THIS_MODULE,
	448	.enable_reg = LP8788_EN_LDO_C,
	449	.enable_mask = LP8788_EN_ALDO9_M,
b5366e5e	450	.min_uV = 2500000,
ade7515f KM	451	},
	452	{
	453	.name = "aldo10",
	454	.id = ALDO10,
	455	.ops = &lp8788_ldo_voltage_fixed_ops,
74c8cfda	456	.n_voltages = 1,
ade7515f KM	457	.type = REGULATOR_VOLTAGE,
	458	.owner = THIS_MODULE,
	459	.enable_reg = LP8788_EN_LDO_C,
	460	.enable_mask = LP8788_EN_ALDO10_M,
b5366e5e	461	.min_uV = 1100000,
ade7515f KM	462	},
	463	};
	464
f02a3917 KM	465	static int lp8788_config_ldo_enable_mode(struct platform_device *pdev,
f02a3917 KM	466	struct lp8788_ldo *ldo,
ade7515f KM	467	enum lp8788_ldo_id id)
ade7515f KM	468	{
ade7515f	469	struct lp8788 *lp = ldo->lp;
ade7515f KM	470	enum lp8788_ext_ldo_en_id enable_id;
	471	u8 en_mask[] = {
	472	[EN_ALDO1] = LP8788_EN_SEL_ALDO1_M,
	473	[EN_ALDO234] = LP8788_EN_SEL_ALDO234_M,
	474	[EN_ALDO5] = LP8788_EN_SEL_ALDO5_M,
	475	[EN_ALDO7] = LP8788_EN_SEL_ALDO7_M,
	476	[EN_DLDO7] = LP8788_EN_SEL_DLDO7_M,
	477	[EN_DLDO911] = LP8788_EN_SEL_DLDO911_M,
	478	};
ade7515f KM	479
	480	switch (id) {
	481	case DLDO7:
	482	enable_id = EN_DLDO7;
	483	break;
	484	case DLDO9:
	485	case DLDO11:
	486	enable_id = EN_DLDO911;
	487	break;
	488	case ALDO1:
	489	enable_id = EN_ALDO1;
	490	break;
	491	case ALDO2 ... ALDO4:
	492	enable_id = EN_ALDO234;
	493	break;
	494	case ALDO5:
	495	enable_id = EN_ALDO5;
	496	break;
	497	case ALDO7:
	498	enable_id = EN_ALDO7;
	499	break;
	500	default:
	501	return 0;
	502	}
	503
2468f0d5 LW	504	/* FIXME: check default mode for GPIO here: high or low? */
2468f0d5 LW	505	ldo->ena_gpiod = devm_gpiod_get_index_optional(&pdev->dev,
63239e4b LW	506	"enable",
	507	enable_id,
	508	GPIOD_OUT_HIGH \|
	509	GPIOD_FLAGS_BIT_NONEXCLUSIVE);
2468f0d5 LW	510	if (IS_ERR(ldo->ena_gpiod))
	511	return PTR_ERR(ldo->ena_gpiod);
	512
	513	/* if no GPIO for ldo pin, then set default enable mode */
	514	if (!ldo->ena_gpiod)
ade7515f KM	515	goto set_default_ldo_enable_mode;
ade7515f KM	516
407945fd	517	return 0;
ade7515f KM	518
ade7515f KM	519	set_default_ldo_enable_mode:
40b5aa8f	520	return lp8788_update_bits(lp, LP8788_EN_SEL, en_mask[enable_id], 0);
ade7515f KM	521	}
ade7515f KM	522
a5023574	523	static int lp8788_dldo_probe(struct platform_device *pdev)
ade7515f KM	524	{
	525	struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
	526	int id = pdev->id;
	527	struct lp8788_ldo *ldo;
	528	struct regulator_config cfg = { };
	529	struct regulator_dev *rdev;
	530	int ret;
	531
939e88f0	532	ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
ade7515f KM	533	if (!ldo)
	534	return -ENOMEM;
	535
	536	ldo->lp = lp;
80abd60d	537	ret = lp8788_config_ldo_enable_mode(pdev, ldo, id);
ade7515f KM	538	if (ret)
	539	return ret;
	540
2468f0d5 LW	541	if (ldo->ena_gpiod)
2468f0d5 LW	542	cfg.ena_gpiod = ldo->ena_gpiod;
407945fd	543
939e88f0	544	cfg.dev = pdev->dev.parent;
ade7515f KM	545	cfg.init_data = lp->pdata ? lp->pdata->dldo_data[id] : NULL;
	546	cfg.driver_data = ldo;
	547	cfg.regmap = lp->regmap;
	548
0b7bb090	549	rdev = devm_regulator_register(&pdev->dev, &lp8788_dldo_desc[id], &cfg);
ade7515f KM	550	if (IS_ERR(rdev)) {
ade7515f KM	551	ret = PTR_ERR(rdev);
939e88f0	552	dev_err(&pdev->dev, "DLDO%d regulator register err = %d\n",
ade7515f KM	553	id + 1, ret);
	554	return ret;
	555	}
	556
	557	ldo->regulator = rdev;
	558	platform_set_drvdata(pdev, ldo);
	559
	560	return 0;
	561	}
	562
ade7515f KM	563	static struct platform_driver lp8788_dldo_driver = {
ade7515f KM	564	.probe = lp8788_dldo_probe,
ade7515f KM	565	.driver = {
ade7515f KM	566	.name = LP8788_DEV_DLDO,
ade7515f KM	567	},
	568	};
	569
a5023574	570	static int lp8788_aldo_probe(struct platform_device *pdev)
ade7515f KM	571	{
	572	struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
	573	int id = pdev->id;
	574	struct lp8788_ldo *ldo;
	575	struct regulator_config cfg = { };
	576	struct regulator_dev *rdev;
	577	int ret;
	578
939e88f0	579	ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
ade7515f KM	580	if (!ldo)
	581	return -ENOMEM;
	582
	583	ldo->lp = lp;
80abd60d	584	ret = lp8788_config_ldo_enable_mode(pdev, ldo, id + ALDO1);
ade7515f KM	585	if (ret)
	586	return ret;
	587
2468f0d5 LW	588	if (ldo->ena_gpiod)
2468f0d5 LW	589	cfg.ena_gpiod = ldo->ena_gpiod;
407945fd	590
939e88f0	591	cfg.dev = pdev->dev.parent;
ade7515f KM	592	cfg.init_data = lp->pdata ? lp->pdata->aldo_data[id] : NULL;
	593	cfg.driver_data = ldo;
	594	cfg.regmap = lp->regmap;
	595
0b7bb090	596	rdev = devm_regulator_register(&pdev->dev, &lp8788_aldo_desc[id], &cfg);
ade7515f KM	597	if (IS_ERR(rdev)) {
ade7515f KM	598	ret = PTR_ERR(rdev);
939e88f0	599	dev_err(&pdev->dev, "ALDO%d regulator register err = %d\n",
ade7515f KM	600	id + 1, ret);
	601	return ret;
	602	}
	603
	604	ldo->regulator = rdev;
	605	platform_set_drvdata(pdev, ldo);
	606
	607	return 0;
	608	}
	609
ade7515f KM	610	static struct platform_driver lp8788_aldo_driver = {
ade7515f KM	611	.probe = lp8788_aldo_probe,
ade7515f KM	612	.driver = {
ade7515f KM	613	.name = LP8788_DEV_ALDO,
ade7515f KM	614	},
	615	};
	616
7629cef1 TR	617	static struct platform_driver * const drivers[] = {
	618	&lp8788_dldo_driver,
	619	&lp8788_aldo_driver,
	620	};
	621
ade7515f KM	622	static int __init lp8788_ldo_init(void)
ade7515f KM	623	{
7629cef1	624	return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
ade7515f KM	625	}
	626	subsys_initcall(lp8788_ldo_init);
	627
	628	static void __exit lp8788_ldo_exit(void)
	629	{
7629cef1	630	platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
ade7515f KM	631	}
	632	module_exit(lp8788_ldo_exit);
	633
	634	MODULE_DESCRIPTION("TI LP8788 LDO Driver");
	635	MODULE_AUTHOR("Milo Kim");
	636	MODULE_LICENSE("GPL");
	637	MODULE_ALIAS("platform:lp8788-dldo");
	638	MODULE_ALIAS("platform:lp8788-aldo");