Commit | Line | Data |
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0cbdf7bc MS |
1 | /* |
2 | * Regulator driver for National Semiconductors LP3971 PMIC chip | |
3 | * | |
4 | * Copyright (C) 2009 Samsung Electronics | |
5 | * Author: Marek Szyprowski <m.szyprowski@samsung.com> | |
6 | * | |
7 | * Based on wm8350.c | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | */ | |
14 | ||
15 | #include <linux/bug.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/i2c.h> | |
18 | #include <linux/kernel.h> | |
65602c32 | 19 | #include <linux/module.h> |
0cbdf7bc MS |
20 | #include <linux/regulator/driver.h> |
21 | #include <linux/regulator/lp3971.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
0cbdf7bc MS |
23 | |
24 | struct lp3971 { | |
25 | struct device *dev; | |
26 | struct mutex io_lock; | |
27 | struct i2c_client *i2c; | |
28 | int num_regulators; | |
29 | struct regulator_dev **rdev; | |
30 | }; | |
31 | ||
32 | static u8 lp3971_reg_read(struct lp3971 *lp3971, u8 reg); | |
33 | static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val); | |
34 | ||
35 | #define LP3971_SYS_CONTROL1_REG 0x07 | |
36 | ||
37 | /* System control register 1 initial value, | |
38 | bits 4 and 5 are EPROM programmable */ | |
39 | #define SYS_CONTROL1_INIT_VAL 0x40 | |
40 | #define SYS_CONTROL1_INIT_MASK 0xCF | |
41 | ||
42 | #define LP3971_BUCK_VOL_ENABLE_REG 0x10 | |
43 | #define LP3971_BUCK_VOL_CHANGE_REG 0x20 | |
44 | ||
45 | /* Voltage control registers shift: | |
46 | LP3971_BUCK1 -> 0 | |
47 | LP3971_BUCK2 -> 4 | |
48 | LP3971_BUCK3 -> 6 | |
49 | */ | |
451a73cd | 50 | #define BUCK_VOL_CHANGE_SHIFT(x) (((!!x) << 2) | (x & ~0x01)) |
0cbdf7bc MS |
51 | #define BUCK_VOL_CHANGE_FLAG_GO 0x01 |
52 | #define BUCK_VOL_CHANGE_FLAG_TARGET 0x02 | |
53 | #define BUCK_VOL_CHANGE_FLAG_MASK 0x03 | |
54 | ||
55 | #define LP3971_BUCK1_BASE 0x23 | |
56 | #define LP3971_BUCK2_BASE 0x29 | |
57 | #define LP3971_BUCK3_BASE 0x32 | |
58 | ||
6faa7e0a | 59 | static const int buck_base_addr[] = { |
0cbdf7bc MS |
60 | LP3971_BUCK1_BASE, |
61 | LP3971_BUCK2_BASE, | |
62 | LP3971_BUCK3_BASE, | |
63 | }; | |
64 | ||
65 | #define LP3971_BUCK_TARGET_VOL1_REG(x) (buck_base_addr[x]) | |
66 | #define LP3971_BUCK_TARGET_VOL2_REG(x) (buck_base_addr[x]+1) | |
67 | ||
cad8d76e AL |
68 | static const unsigned int buck_voltage_map[] = { |
69 | 0, 800000, 850000, 900000, 950000, 1000000, 1050000, 1100000, | |
70 | 1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000, | |
71 | 1550000, 1600000, 1650000, 1700000, 1800000, 1900000, 2500000, 2800000, | |
72 | 3000000, 3300000, | |
0cbdf7bc MS |
73 | }; |
74 | ||
75 | #define BUCK_TARGET_VOL_MASK 0x3f | |
0cbdf7bc MS |
76 | |
77 | #define LP3971_BUCK_RAMP_REG(x) (buck_base_addr[x]+2) | |
78 | ||
79 | #define LP3971_LDO_ENABLE_REG 0x12 | |
80 | #define LP3971_LDO_VOL_CONTR_BASE 0x39 | |
81 | ||
82 | /* Voltage control registers: | |
83 | LP3971_LDO1 -> LP3971_LDO_VOL_CONTR_BASE + 0 | |
84 | LP3971_LDO2 -> LP3971_LDO_VOL_CONTR_BASE + 0 | |
85 | LP3971_LDO3 -> LP3971_LDO_VOL_CONTR_BASE + 1 | |
86 | LP3971_LDO4 -> LP3971_LDO_VOL_CONTR_BASE + 1 | |
87 | LP3971_LDO5 -> LP3971_LDO_VOL_CONTR_BASE + 2 | |
88 | */ | |
89 | #define LP3971_LDO_VOL_CONTR_REG(x) (LP3971_LDO_VOL_CONTR_BASE + (x >> 1)) | |
90 | ||
91 | /* Voltage control registers shift: | |
92 | LP3971_LDO1 -> 0, LP3971_LDO2 -> 4 | |
93 | LP3971_LDO3 -> 0, LP3971_LDO4 -> 4 | |
94 | LP3971_LDO5 -> 0 | |
95 | */ | |
96 | #define LDO_VOL_CONTR_SHIFT(x) ((x & 1) << 2) | |
97 | #define LDO_VOL_CONTR_MASK 0x0f | |
98 | ||
cad8d76e AL |
99 | static const unsigned int ldo45_voltage_map[] = { |
100 | 1000000, 1050000, 1100000, 1150000, 1200000, 1250000, 1300000, 1350000, | |
101 | 1400000, 1500000, 1800000, 1900000, 2500000, 2800000, 3000000, 3300000, | |
0cbdf7bc MS |
102 | }; |
103 | ||
cad8d76e AL |
104 | static const unsigned int ldo123_voltage_map[] = { |
105 | 1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000, | |
106 | 2600000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000, | |
0cbdf7bc MS |
107 | }; |
108 | ||
0cbdf7bc MS |
109 | #define LDO_VOL_MIN_IDX 0x00 |
110 | #define LDO_VOL_MAX_IDX 0x0f | |
111 | ||
0cbdf7bc MS |
112 | static int lp3971_ldo_is_enabled(struct regulator_dev *dev) |
113 | { | |
114 | struct lp3971 *lp3971 = rdev_get_drvdata(dev); | |
115 | int ldo = rdev_get_id(dev) - LP3971_LDO1; | |
116 | u16 mask = 1 << (1 + ldo); | |
117 | u16 val; | |
118 | ||
119 | val = lp3971_reg_read(lp3971, LP3971_LDO_ENABLE_REG); | |
120 | return (val & mask) != 0; | |
121 | } | |
122 | ||
123 | static int lp3971_ldo_enable(struct regulator_dev *dev) | |
124 | { | |
125 | struct lp3971 *lp3971 = rdev_get_drvdata(dev); | |
126 | int ldo = rdev_get_id(dev) - LP3971_LDO1; | |
127 | u16 mask = 1 << (1 + ldo); | |
128 | ||
129 | return lp3971_set_bits(lp3971, LP3971_LDO_ENABLE_REG, mask, mask); | |
130 | } | |
131 | ||
132 | static int lp3971_ldo_disable(struct regulator_dev *dev) | |
133 | { | |
134 | struct lp3971 *lp3971 = rdev_get_drvdata(dev); | |
135 | int ldo = rdev_get_id(dev) - LP3971_LDO1; | |
136 | u16 mask = 1 << (1 + ldo); | |
137 | ||
138 | return lp3971_set_bits(lp3971, LP3971_LDO_ENABLE_REG, mask, 0); | |
139 | } | |
140 | ||
f38482fa | 141 | static int lp3971_ldo_get_voltage_sel(struct regulator_dev *dev) |
0cbdf7bc MS |
142 | { |
143 | struct lp3971 *lp3971 = rdev_get_drvdata(dev); | |
144 | int ldo = rdev_get_id(dev) - LP3971_LDO1; | |
145 | u16 val, reg; | |
146 | ||
147 | reg = lp3971_reg_read(lp3971, LP3971_LDO_VOL_CONTR_REG(ldo)); | |
148 | val = (reg >> LDO_VOL_CONTR_SHIFT(ldo)) & LDO_VOL_CONTR_MASK; | |
149 | ||
f38482fa | 150 | return val; |
0cbdf7bc MS |
151 | } |
152 | ||
dd8e2314 AL |
153 | static int lp3971_ldo_set_voltage_sel(struct regulator_dev *dev, |
154 | unsigned int selector) | |
0cbdf7bc MS |
155 | { |
156 | struct lp3971 *lp3971 = rdev_get_drvdata(dev); | |
157 | int ldo = rdev_get_id(dev) - LP3971_LDO1; | |
3a93f2a9 | 158 | |
0cbdf7bc | 159 | return lp3971_set_bits(lp3971, LP3971_LDO_VOL_CONTR_REG(ldo), |
cdb868f5 | 160 | LDO_VOL_CONTR_MASK << LDO_VOL_CONTR_SHIFT(ldo), |
dd8e2314 | 161 | selector << LDO_VOL_CONTR_SHIFT(ldo)); |
0cbdf7bc MS |
162 | } |
163 | ||
164 | static struct regulator_ops lp3971_ldo_ops = { | |
cad8d76e | 165 | .list_voltage = regulator_list_voltage_table, |
3e655618 | 166 | .map_voltage = regulator_map_voltage_ascend, |
0cbdf7bc MS |
167 | .is_enabled = lp3971_ldo_is_enabled, |
168 | .enable = lp3971_ldo_enable, | |
169 | .disable = lp3971_ldo_disable, | |
f38482fa | 170 | .get_voltage_sel = lp3971_ldo_get_voltage_sel, |
dd8e2314 | 171 | .set_voltage_sel = lp3971_ldo_set_voltage_sel, |
0cbdf7bc MS |
172 | }; |
173 | ||
0cbdf7bc MS |
174 | static int lp3971_dcdc_is_enabled(struct regulator_dev *dev) |
175 | { | |
176 | struct lp3971 *lp3971 = rdev_get_drvdata(dev); | |
177 | int buck = rdev_get_id(dev) - LP3971_DCDC1; | |
178 | u16 mask = 1 << (buck * 2); | |
179 | u16 val; | |
180 | ||
181 | val = lp3971_reg_read(lp3971, LP3971_BUCK_VOL_ENABLE_REG); | |
182 | return (val & mask) != 0; | |
183 | } | |
184 | ||
185 | static int lp3971_dcdc_enable(struct regulator_dev *dev) | |
186 | { | |
187 | struct lp3971 *lp3971 = rdev_get_drvdata(dev); | |
188 | int buck = rdev_get_id(dev) - LP3971_DCDC1; | |
189 | u16 mask = 1 << (buck * 2); | |
190 | ||
191 | return lp3971_set_bits(lp3971, LP3971_BUCK_VOL_ENABLE_REG, mask, mask); | |
192 | } | |
193 | ||
194 | static int lp3971_dcdc_disable(struct regulator_dev *dev) | |
195 | { | |
196 | struct lp3971 *lp3971 = rdev_get_drvdata(dev); | |
197 | int buck = rdev_get_id(dev) - LP3971_DCDC1; | |
198 | u16 mask = 1 << (buck * 2); | |
199 | ||
200 | return lp3971_set_bits(lp3971, LP3971_BUCK_VOL_ENABLE_REG, mask, 0); | |
201 | } | |
202 | ||
f38482fa | 203 | static int lp3971_dcdc_get_voltage_sel(struct regulator_dev *dev) |
0cbdf7bc MS |
204 | { |
205 | struct lp3971 *lp3971 = rdev_get_drvdata(dev); | |
206 | int buck = rdev_get_id(dev) - LP3971_DCDC1; | |
207 | u16 reg; | |
0cbdf7bc MS |
208 | |
209 | reg = lp3971_reg_read(lp3971, LP3971_BUCK_TARGET_VOL1_REG(buck)); | |
210 | reg &= BUCK_TARGET_VOL_MASK; | |
211 | ||
f38482fa | 212 | return reg; |
0cbdf7bc MS |
213 | } |
214 | ||
dd8e2314 AL |
215 | static int lp3971_dcdc_set_voltage_sel(struct regulator_dev *dev, |
216 | unsigned int selector) | |
0cbdf7bc MS |
217 | { |
218 | struct lp3971 *lp3971 = rdev_get_drvdata(dev); | |
219 | int buck = rdev_get_id(dev) - LP3971_DCDC1; | |
0cbdf7bc MS |
220 | int ret; |
221 | ||
0cbdf7bc | 222 | ret = lp3971_set_bits(lp3971, LP3971_BUCK_TARGET_VOL1_REG(buck), |
dd8e2314 | 223 | BUCK_TARGET_VOL_MASK, selector); |
0cbdf7bc MS |
224 | if (ret) |
225 | return ret; | |
226 | ||
227 | ret = lp3971_set_bits(lp3971, LP3971_BUCK_VOL_CHANGE_REG, | |
228 | BUCK_VOL_CHANGE_FLAG_MASK << BUCK_VOL_CHANGE_SHIFT(buck), | |
229 | BUCK_VOL_CHANGE_FLAG_GO << BUCK_VOL_CHANGE_SHIFT(buck)); | |
230 | if (ret) | |
231 | return ret; | |
232 | ||
233 | return lp3971_set_bits(lp3971, LP3971_BUCK_VOL_CHANGE_REG, | |
234 | BUCK_VOL_CHANGE_FLAG_MASK << BUCK_VOL_CHANGE_SHIFT(buck), | |
235 | 0 << BUCK_VOL_CHANGE_SHIFT(buck)); | |
236 | } | |
237 | ||
238 | static struct regulator_ops lp3971_dcdc_ops = { | |
cad8d76e | 239 | .list_voltage = regulator_list_voltage_table, |
3e655618 | 240 | .map_voltage = regulator_map_voltage_ascend, |
0cbdf7bc MS |
241 | .is_enabled = lp3971_dcdc_is_enabled, |
242 | .enable = lp3971_dcdc_enable, | |
243 | .disable = lp3971_dcdc_disable, | |
f38482fa | 244 | .get_voltage_sel = lp3971_dcdc_get_voltage_sel, |
dd8e2314 | 245 | .set_voltage_sel = lp3971_dcdc_set_voltage_sel, |
0cbdf7bc MS |
246 | }; |
247 | ||
14add4ff | 248 | static const struct regulator_desc regulators[] = { |
0cbdf7bc MS |
249 | { |
250 | .name = "LDO1", | |
251 | .id = LP3971_LDO1, | |
252 | .ops = &lp3971_ldo_ops, | |
253 | .n_voltages = ARRAY_SIZE(ldo123_voltage_map), | |
cad8d76e | 254 | .volt_table = ldo123_voltage_map, |
0cbdf7bc MS |
255 | .type = REGULATOR_VOLTAGE, |
256 | .owner = THIS_MODULE, | |
257 | }, | |
258 | { | |
259 | .name = "LDO2", | |
260 | .id = LP3971_LDO2, | |
261 | .ops = &lp3971_ldo_ops, | |
262 | .n_voltages = ARRAY_SIZE(ldo123_voltage_map), | |
cad8d76e | 263 | .volt_table = ldo123_voltage_map, |
0cbdf7bc MS |
264 | .type = REGULATOR_VOLTAGE, |
265 | .owner = THIS_MODULE, | |
266 | }, | |
267 | { | |
268 | .name = "LDO3", | |
269 | .id = LP3971_LDO3, | |
270 | .ops = &lp3971_ldo_ops, | |
271 | .n_voltages = ARRAY_SIZE(ldo123_voltage_map), | |
cad8d76e | 272 | .volt_table = ldo123_voltage_map, |
0cbdf7bc MS |
273 | .type = REGULATOR_VOLTAGE, |
274 | .owner = THIS_MODULE, | |
275 | }, | |
276 | { | |
277 | .name = "LDO4", | |
278 | .id = LP3971_LDO4, | |
279 | .ops = &lp3971_ldo_ops, | |
280 | .n_voltages = ARRAY_SIZE(ldo45_voltage_map), | |
cad8d76e | 281 | .volt_table = ldo45_voltage_map, |
0cbdf7bc MS |
282 | .type = REGULATOR_VOLTAGE, |
283 | .owner = THIS_MODULE, | |
284 | }, | |
285 | { | |
286 | .name = "LDO5", | |
287 | .id = LP3971_LDO5, | |
288 | .ops = &lp3971_ldo_ops, | |
289 | .n_voltages = ARRAY_SIZE(ldo45_voltage_map), | |
cad8d76e | 290 | .volt_table = ldo45_voltage_map, |
0cbdf7bc MS |
291 | .type = REGULATOR_VOLTAGE, |
292 | .owner = THIS_MODULE, | |
293 | }, | |
294 | { | |
295 | .name = "DCDC1", | |
296 | .id = LP3971_DCDC1, | |
297 | .ops = &lp3971_dcdc_ops, | |
298 | .n_voltages = ARRAY_SIZE(buck_voltage_map), | |
cad8d76e | 299 | .volt_table = buck_voltage_map, |
0cbdf7bc MS |
300 | .type = REGULATOR_VOLTAGE, |
301 | .owner = THIS_MODULE, | |
302 | }, | |
303 | { | |
304 | .name = "DCDC2", | |
305 | .id = LP3971_DCDC2, | |
306 | .ops = &lp3971_dcdc_ops, | |
307 | .n_voltages = ARRAY_SIZE(buck_voltage_map), | |
cad8d76e | 308 | .volt_table = buck_voltage_map, |
0cbdf7bc MS |
309 | .type = REGULATOR_VOLTAGE, |
310 | .owner = THIS_MODULE, | |
311 | }, | |
312 | { | |
313 | .name = "DCDC3", | |
314 | .id = LP3971_DCDC3, | |
315 | .ops = &lp3971_dcdc_ops, | |
316 | .n_voltages = ARRAY_SIZE(buck_voltage_map), | |
cad8d76e | 317 | .volt_table = buck_voltage_map, |
0cbdf7bc MS |
318 | .type = REGULATOR_VOLTAGE, |
319 | .owner = THIS_MODULE, | |
320 | }, | |
321 | }; | |
322 | ||
323 | static int lp3971_i2c_read(struct i2c_client *i2c, char reg, int count, | |
324 | u16 *dest) | |
325 | { | |
326 | int ret; | |
327 | ||
328 | if (count != 1) | |
329 | return -EIO; | |
330 | ret = i2c_smbus_read_byte_data(i2c, reg); | |
27ef7f00 | 331 | if (ret < 0) |
0cbdf7bc MS |
332 | return -EIO; |
333 | ||
334 | *dest = ret; | |
335 | return 0; | |
336 | } | |
337 | ||
338 | static int lp3971_i2c_write(struct i2c_client *i2c, char reg, int count, | |
339 | const u16 *src) | |
340 | { | |
0cbdf7bc MS |
341 | if (count != 1) |
342 | return -EIO; | |
1bddc2f5 | 343 | return i2c_smbus_write_byte_data(i2c, reg, *src); |
0cbdf7bc MS |
344 | } |
345 | ||
346 | static u8 lp3971_reg_read(struct lp3971 *lp3971, u8 reg) | |
347 | { | |
348 | u16 val = 0; | |
349 | ||
350 | mutex_lock(&lp3971->io_lock); | |
351 | ||
352 | lp3971_i2c_read(lp3971->i2c, reg, 1, &val); | |
353 | ||
354 | dev_dbg(lp3971->dev, "reg read 0x%02x -> 0x%02x\n", (int)reg, | |
355 | (unsigned)val&0xff); | |
356 | ||
357 | mutex_unlock(&lp3971->io_lock); | |
358 | ||
359 | return val & 0xff; | |
360 | } | |
361 | ||
362 | static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val) | |
363 | { | |
364 | u16 tmp; | |
365 | int ret; | |
366 | ||
367 | mutex_lock(&lp3971->io_lock); | |
368 | ||
369 | ret = lp3971_i2c_read(lp3971->i2c, reg, 1, &tmp); | |
370 | tmp = (tmp & ~mask) | val; | |
371 | if (ret == 0) { | |
372 | ret = lp3971_i2c_write(lp3971->i2c, reg, 1, &tmp); | |
373 | dev_dbg(lp3971->dev, "reg write 0x%02x -> 0x%02x\n", (int)reg, | |
374 | (unsigned)val&0xff); | |
375 | } | |
376 | mutex_unlock(&lp3971->io_lock); | |
377 | ||
378 | return ret; | |
379 | } | |
380 | ||
a5023574 | 381 | static int setup_regulators(struct lp3971 *lp3971, |
ebbed04f | 382 | struct lp3971_platform_data *pdata) |
0cbdf7bc MS |
383 | { |
384 | int i, err; | |
ebbed04f DT |
385 | |
386 | lp3971->num_regulators = pdata->num_regulators; | |
387 | lp3971->rdev = kcalloc(pdata->num_regulators, | |
388 | sizeof(struct regulator_dev *), GFP_KERNEL); | |
67e46f34 DC |
389 | if (!lp3971->rdev) { |
390 | err = -ENOMEM; | |
391 | goto err_nomem; | |
392 | } | |
0cbdf7bc MS |
393 | |
394 | /* Instantiate the regulators */ | |
ebbed04f | 395 | for (i = 0; i < pdata->num_regulators; i++) { |
c172708d | 396 | struct regulator_config config = { }; |
ebbed04f | 397 | struct lp3971_regulator_subdev *reg = &pdata->regulators[i]; |
0cbdf7bc | 398 | |
c172708d MB |
399 | config.dev = lp3971->dev; |
400 | config.init_data = reg->initdata; | |
401 | config.driver_data = lp3971; | |
402 | ||
403 | lp3971->rdev[i] = regulator_register(®ulators[reg->id], | |
404 | &config); | |
d662fc82 JL |
405 | if (IS_ERR(lp3971->rdev[i])) { |
406 | err = PTR_ERR(lp3971->rdev[i]); | |
0cbdf7bc MS |
407 | dev_err(lp3971->dev, "regulator init failed: %d\n", |
408 | err); | |
409 | goto error; | |
410 | } | |
411 | } | |
412 | ||
413 | return 0; | |
ebbed04f | 414 | |
0cbdf7bc | 415 | error: |
ebbed04f DT |
416 | while (--i >= 0) |
417 | regulator_unregister(lp3971->rdev[i]); | |
0cbdf7bc MS |
418 | kfree(lp3971->rdev); |
419 | lp3971->rdev = NULL; | |
67e46f34 | 420 | err_nomem: |
0cbdf7bc MS |
421 | return err; |
422 | } | |
423 | ||
a5023574 | 424 | static int lp3971_i2c_probe(struct i2c_client *i2c, |
0cbdf7bc MS |
425 | const struct i2c_device_id *id) |
426 | { | |
427 | struct lp3971 *lp3971; | |
dff91d0b | 428 | struct lp3971_platform_data *pdata = dev_get_platdata(&i2c->dev); |
0cbdf7bc MS |
429 | int ret; |
430 | u16 val; | |
431 | ||
ebbed04f DT |
432 | if (!pdata) { |
433 | dev_dbg(&i2c->dev, "No platform init data supplied\n"); | |
434 | return -ENODEV; | |
0cbdf7bc MS |
435 | } |
436 | ||
2af0af67 | 437 | lp3971 = devm_kzalloc(&i2c->dev, sizeof(struct lp3971), GFP_KERNEL); |
ebbed04f DT |
438 | if (lp3971 == NULL) |
439 | return -ENOMEM; | |
440 | ||
0cbdf7bc MS |
441 | lp3971->i2c = i2c; |
442 | lp3971->dev = &i2c->dev; | |
0cbdf7bc MS |
443 | |
444 | mutex_init(&lp3971->io_lock); | |
445 | ||
446 | /* Detect LP3971 */ | |
447 | ret = lp3971_i2c_read(i2c, LP3971_SYS_CONTROL1_REG, 1, &val); | |
448 | if (ret == 0 && (val & SYS_CONTROL1_INIT_MASK) != SYS_CONTROL1_INIT_VAL) | |
449 | ret = -ENODEV; | |
450 | if (ret < 0) { | |
451 | dev_err(&i2c->dev, "failed to detect device\n"); | |
2af0af67 | 452 | return ret; |
0cbdf7bc MS |
453 | } |
454 | ||
ebbed04f DT |
455 | ret = setup_regulators(lp3971, pdata); |
456 | if (ret < 0) | |
2af0af67 | 457 | return ret; |
0cbdf7bc | 458 | |
ebbed04f | 459 | i2c_set_clientdata(i2c, lp3971); |
0cbdf7bc | 460 | return 0; |
0cbdf7bc MS |
461 | } |
462 | ||
8dc995f5 | 463 | static int lp3971_i2c_remove(struct i2c_client *i2c) |
0cbdf7bc MS |
464 | { |
465 | struct lp3971 *lp3971 = i2c_get_clientdata(i2c); | |
466 | int i; | |
ebbed04f | 467 | |
0cbdf7bc | 468 | for (i = 0; i < lp3971->num_regulators; i++) |
ebbed04f DT |
469 | regulator_unregister(lp3971->rdev[i]); |
470 | ||
0cbdf7bc | 471 | kfree(lp3971->rdev); |
0cbdf7bc MS |
472 | |
473 | return 0; | |
474 | } | |
475 | ||
476 | static const struct i2c_device_id lp3971_i2c_id[] = { | |
477 | { "lp3971", 0 }, | |
478 | { } | |
479 | }; | |
480 | MODULE_DEVICE_TABLE(i2c, lp3971_i2c_id); | |
481 | ||
482 | static struct i2c_driver lp3971_i2c_driver = { | |
483 | .driver = { | |
484 | .name = "LP3971", | |
485 | .owner = THIS_MODULE, | |
486 | }, | |
487 | .probe = lp3971_i2c_probe, | |
5eb9f2b9 | 488 | .remove = lp3971_i2c_remove, |
0cbdf7bc MS |
489 | .id_table = lp3971_i2c_id, |
490 | }; | |
491 | ||
5af34e60 | 492 | module_i2c_driver(lp3971_i2c_driver); |
0cbdf7bc MS |
493 | |
494 | MODULE_LICENSE("GPL"); | |
495 | MODULE_AUTHOR("Marek Szyprowski <m.szyprowski@samsung.com>"); | |
496 | MODULE_DESCRIPTION("LP3971 PMIC driver"); |