[linux-2.6-block.git] / drivers / regulator / anatop-regulator.c

/*
 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
 */

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.

 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */

#include <linux/slab.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/of_regulator.h>

#define LDO_RAMP_UP_UNIT_IN_CYCLES      64 /* 64 cycles per step */
#define LDO_RAMP_UP_FREQ_IN_MHZ         24 /* cycle based on 24M OSC */

#define LDO_POWER_GATE			0x00
#define LDO_FET_FULL_ON			0x1f

struct anatop_regulator {
	const char *name;
	u32 control_reg;
	struct regmap *anatop;
	int vol_bit_shift;
	int vol_bit_width;
	u32 delay_reg;
	int delay_bit_shift;
	int delay_bit_width;
	int min_bit_val;
	int min_voltage;
	int max_voltage;
	struct regulator_desc rdesc;
	struct regulator_init_data *initdata;
	bool bypass;
	int sel;
};

static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
	unsigned int old_sel,
	unsigned int new_sel)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	u32 val;
	int ret = 0;

	/* check whether need to care about LDO ramp up speed */
	if (anatop_reg->delay_bit_width && new_sel > old_sel) {
		/*
		 * the delay for LDO ramp up time is
		 * based on the register setting, we need
		 * to calculate how many steps LDO need to
		 * ramp up, and how much delay needed. (us)
		 */
		regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
		val = (val >> anatop_reg->delay_bit_shift) &
			((1 << anatop_reg->delay_bit_width) - 1);
		ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
			val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
	}

	return ret;
}

static int anatop_regmap_enable(struct regulator_dev *reg)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	int sel;

	sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
	return regulator_set_voltage_sel_regmap(reg, sel);
}

static int anatop_regmap_disable(struct regulator_dev *reg)
{
	return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
}

static int anatop_regmap_is_enabled(struct regulator_dev *reg)
{
	return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
}

static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
					      unsigned selector)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	int ret;

	if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) {
		anatop_reg->sel = selector;
		return 0;
	}

	ret = regulator_set_voltage_sel_regmap(reg, selector);
	if (!ret)
		anatop_reg->sel = selector;
	return ret;
}

static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);

	if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg))
		return anatop_reg->sel;

	return regulator_get_voltage_sel_regmap(reg);
}

static int anatop_regmap_get_bypass(struct regulator_dev *reg, bool *enable)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	int sel;

	sel = regulator_get_voltage_sel_regmap(reg);
	if (sel == LDO_FET_FULL_ON)
		WARN_ON(!anatop_reg->bypass);
	else if (sel != LDO_POWER_GATE)
		WARN_ON(anatop_reg->bypass);

	*enable = anatop_reg->bypass;
	return 0;
}

static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	int sel;

	if (enable == anatop_reg->bypass)
		return 0;

	sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
	anatop_reg->bypass = enable;

	return regulator_set_voltage_sel_regmap(reg, sel);
}

static struct regulator_ops anatop_rops = {
	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	.list_voltage = regulator_list_voltage_linear,
	.map_voltage = regulator_map_voltage_linear,
};

static struct regulator_ops anatop_core_rops = {
	.enable = anatop_regmap_enable,
	.disable = anatop_regmap_disable,
	.is_enabled = anatop_regmap_is_enabled,
	.set_voltage_sel = anatop_regmap_core_set_voltage_sel,
	.set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
	.get_voltage_sel = anatop_regmap_core_get_voltage_sel,
	.list_voltage = regulator_list_voltage_linear,
	.map_voltage = regulator_map_voltage_linear,
	.get_bypass = anatop_regmap_get_bypass,
	.set_bypass = anatop_regmap_set_bypass,
};

static int anatop_regulator_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct device_node *anatop_np;
	struct regulator_desc *rdesc;
	struct regulator_dev *rdev;
	struct anatop_regulator *sreg;
	struct regulator_init_data *initdata;
	struct regulator_config config = { };
	int ret = 0;
	u32 val;

	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
	if (!sreg)
		return -ENOMEM;
	sreg->name = of_get_property(np, "regulator-name", NULL);
	rdesc = &sreg->rdesc;
	rdesc->name = sreg->name;
	rdesc->type = REGULATOR_VOLTAGE;
	rdesc->owner = THIS_MODULE;

	initdata = of_get_regulator_init_data(dev, np, rdesc);
	sreg->initdata = initdata;

	anatop_np = of_get_parent(np);
	if (!anatop_np)
		return -ENODEV;
	sreg->anatop = syscon_node_to_regmap(anatop_np);
	of_node_put(anatop_np);
	if (IS_ERR(sreg->anatop))
		return PTR_ERR(sreg->anatop);

	ret = of_property_read_u32(np, "anatop-reg-offset",
				   &sreg->control_reg);
	if (ret) {
		dev_err(dev, "no anatop-reg-offset property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-vol-bit-width",
				   &sreg->vol_bit_width);
	if (ret) {
		dev_err(dev, "no anatop-vol-bit-width property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-vol-bit-shift",
				   &sreg->vol_bit_shift);
	if (ret) {
		dev_err(dev, "no anatop-vol-bit-shift property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-min-bit-val",
				   &sreg->min_bit_val);
	if (ret) {
		dev_err(dev, "no anatop-min-bit-val property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-min-voltage",
				   &sreg->min_voltage);
	if (ret) {
		dev_err(dev, "no anatop-min-voltage property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-max-voltage",
				   &sreg->max_voltage);
	if (ret) {
		dev_err(dev, "no anatop-max-voltage property set\n");
		return ret;
	}

	/* read LDO ramp up setting, only for core reg */
	of_property_read_u32(np, "anatop-delay-reg-offset",
			     &sreg->delay_reg);
	of_property_read_u32(np, "anatop-delay-bit-width",
			     &sreg->delay_bit_width);
	of_property_read_u32(np, "anatop-delay-bit-shift",
			     &sreg->delay_bit_shift);

	rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage) / 25000 + 1
			    + sreg->min_bit_val;
	rdesc->min_uV = sreg->min_voltage;
	rdesc->uV_step = 25000;
	rdesc->linear_min_sel = sreg->min_bit_val;
	rdesc->vsel_reg = sreg->control_reg;
	rdesc->vsel_mask = ((1 << sreg->vol_bit_width) - 1) <<
			   sreg->vol_bit_shift;

	config.dev = &pdev->dev;
	config.init_data = initdata;
	config.driver_data = sreg;
	config.of_node = pdev->dev.of_node;
	config.regmap = sreg->anatop;

	/* Only core regulators have the ramp up delay configuration. */
	if (sreg->control_reg && sreg->delay_bit_width) {
		rdesc->ops = &anatop_core_rops;

		ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
		if (ret) {
			dev_err(dev, "failed to read initial state\n");
			return ret;
		}

		sreg->sel = (val & rdesc->vsel_mask) >> sreg->vol_bit_shift;
		if (sreg->sel == LDO_FET_FULL_ON) {
			sreg->sel = 0;
			sreg->bypass = true;
		}

		/*
		 * In case vddpu was disabled by the bootloader, we need to set
		 * a sane default until imx6-cpufreq was probed and changes the
		 * voltage to the correct value. In this case we set 1.25V.
		 */
		if (!sreg->sel && !strcmp(sreg->name, "vddpu"))
			sreg->sel = 22;

		if (!sreg->sel) {
			dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
			return -EINVAL;
		}
	} else {
		rdesc->ops = &anatop_rops;
	}

	/* register regulator */
	rdev = devm_regulator_register(dev, rdesc, &config);
	if (IS_ERR(rdev)) {
		dev_err(dev, "failed to register %s\n",
			rdesc->name);
		return PTR_ERR(rdev);
	}

	platform_set_drvdata(pdev, rdev);

	return 0;
}

static const struct of_device_id of_anatop_regulator_match_tbl[] = {
	{ .compatible = "fsl,anatop-regulator", },
	{ /* end */ }
};
MODULE_DEVICE_TABLE(of, of_anatop_regulator_match_tbl);

static struct platform_driver anatop_regulator_driver = {
	.driver = {
		.name	= "anatop_regulator",
		.of_match_table = of_anatop_regulator_match_tbl,
	},
	.probe	= anatop_regulator_probe,
};

static int __init anatop_regulator_init(void)
{
	return platform_driver_register(&anatop_regulator_driver);
}
postcore_initcall(anatop_regulator_init);

static void __exit anatop_regulator_exit(void)
{
	platform_driver_unregister(&anatop_regulator_driver);
}
module_exit(anatop_regulator_exit);

MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>");
MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
MODULE_DESCRIPTION("ANATOP Regulator driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:anatop_regulator");
Commit	Line	Data
e3e5aff7 YCLP	1	/*
	2	* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*/
	4
	5	/*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15
	16	* You should have received a copy of the GNU General Public License along
	17	* with this program; if not, write to the Free Software Foundation, Inc.,
	18	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
	19	*/
	20
	21	#include <linux/slab.h>
	22	#include <linux/device.h>
	23	#include <linux/module.h>
baa64151	24	#include <linux/mfd/syscon.h>
e3e5aff7 YCLP	25	#include <linux/err.h>
	26	#include <linux/io.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/of.h>
	29	#include <linux/of_address.h>
baa64151	30	#include <linux/regmap.h>
e3e5aff7 YCLP	31	#include <linux/regulator/driver.h>
	32	#include <linux/regulator/of_regulator.h>
	33
9ee417c0 AH	34	#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
	35	#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
	36
605ebd35	37	#define LDO_POWER_GATE 0x00
d38018f2	38	#define LDO_FET_FULL_ON 0x1f
605ebd35	39
e3e5aff7 YCLP	40	struct anatop_regulator {
	41	const char *name;
	42	u32 control_reg;
baa64151	43	struct regmap *anatop;
e3e5aff7 YCLP	44	int vol_bit_shift;
e3e5aff7 YCLP	45	int vol_bit_width;
9ee417c0 AH	46	u32 delay_reg;
	47	int delay_bit_shift;
	48	int delay_bit_width;
e3e5aff7 YCLP	49	int min_bit_val;
	50	int min_voltage;
	51	int max_voltage;
	52	struct regulator_desc rdesc;
	53	struct regulator_init_data *initdata;
d38018f2	54	bool bypass;
605ebd35	55	int sel;
e3e5aff7 YCLP	56	};
e3e5aff7 YCLP	57
9ee417c0 AH	58	static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
	59	unsigned int old_sel,
	60	unsigned int new_sel)
	61	{
	62	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	63	u32 val;
	64	int ret = 0;
	65
	66	/* check whether need to care about LDO ramp up speed */
	67	if (anatop_reg->delay_bit_width && new_sel > old_sel) {
	68	/*
	69	* the delay for LDO ramp up time is
	70	* based on the register setting, we need
	71	* to calculate how many steps LDO need to
	72	* ramp up, and how much delay needed. (us)
	73	*/
	74	regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
	75	val = (val >> anatop_reg->delay_bit_shift) &
	76	((1 << anatop_reg->delay_bit_width) - 1);
ff1ce057 SG	77	ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
ff1ce057 SG	78	val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
9ee417c0 AH	79	}
	80
	81	return ret;
	82	}
	83
605ebd35 PZ	84	static int anatop_regmap_enable(struct regulator_dev *reg)
	85	{
	86	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
d38018f2	87	int sel;
605ebd35	88
d38018f2 PZ	89	sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
d38018f2 PZ	90	return regulator_set_voltage_sel_regmap(reg, sel);
605ebd35 PZ	91	}
	92
	93	static int anatop_regmap_disable(struct regulator_dev *reg)
	94	{
	95	return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
	96	}
	97
	98	static int anatop_regmap_is_enabled(struct regulator_dev *reg)
	99	{
	100	return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
	101	}
	102
	103	static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
	104	unsigned selector)
	105	{
	106	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	107	int ret;
	108
d38018f2	109	if (anatop_reg->bypass \|\| !anatop_regmap_is_enabled(reg)) {
605ebd35 PZ	110	anatop_reg->sel = selector;
	111	return 0;
	112	}
	113
	114	ret = regulator_set_voltage_sel_regmap(reg, selector);
	115	if (!ret)
	116	anatop_reg->sel = selector;
	117	return ret;
	118	}
	119
	120	static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
	121	{
	122	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	123
d38018f2	124	if (anatop_reg->bypass \|\| !anatop_regmap_is_enabled(reg))
605ebd35 PZ	125	return anatop_reg->sel;
	126
	127	return regulator_get_voltage_sel_regmap(reg);
	128	}
	129
d38018f2 PZ	130	static int anatop_regmap_get_bypass(struct regulator_dev reg, bool enable)
	131	{
	132	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	133	int sel;
	134
	135	sel = regulator_get_voltage_sel_regmap(reg);
	136	if (sel == LDO_FET_FULL_ON)
	137	WARN_ON(!anatop_reg->bypass);
	138	else if (sel != LDO_POWER_GATE)
	139	WARN_ON(anatop_reg->bypass);
	140
	141	*enable = anatop_reg->bypass;
	142	return 0;
	143	}
	144
	145	static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
	146	{
	147	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	148	int sel;
	149
	150	if (enable == anatop_reg->bypass)
	151	return 0;
	152
	153	sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
	154	anatop_reg->bypass = enable;
	155
	156	return regulator_set_voltage_sel_regmap(reg, sel);
	157	}
	158
e3e5aff7	159	static struct regulator_ops anatop_rops = {
114c5748 AL	160	.set_voltage_sel = regulator_set_voltage_sel_regmap,
114c5748 AL	161	.get_voltage_sel = regulator_get_voltage_sel_regmap,
d01c3a1e AL	162	.list_voltage = regulator_list_voltage_linear,
d01c3a1e AL	163	.map_voltage = regulator_map_voltage_linear,
e3e5aff7 YCLP	164	};
e3e5aff7 YCLP	165
605ebd35 PZ	166	static struct regulator_ops anatop_core_rops = {
	167	.enable = anatop_regmap_enable,
	168	.disable = anatop_regmap_disable,
	169	.is_enabled = anatop_regmap_is_enabled,
	170	.set_voltage_sel = anatop_regmap_core_set_voltage_sel,
	171	.set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
	172	.get_voltage_sel = anatop_regmap_core_get_voltage_sel,
	173	.list_voltage = regulator_list_voltage_linear,
	174	.map_voltage = regulator_map_voltage_linear,
d38018f2 PZ	175	.get_bypass = anatop_regmap_get_bypass,
d38018f2 PZ	176	.set_bypass = anatop_regmap_set_bypass,
605ebd35 PZ	177	};
605ebd35 PZ	178
a5023574	179	static int anatop_regulator_probe(struct platform_device *pdev)
e3e5aff7 YCLP	180	{
	181	struct device *dev = &pdev->dev;
	182	struct device_node *np = dev->of_node;
baa64151	183	struct device_node *anatop_np;
e3e5aff7 YCLP	184	struct regulator_desc *rdesc;
	185	struct regulator_dev *rdev;
	186	struct anatop_regulator *sreg;
	187	struct regulator_init_data *initdata;
d914d81b	188	struct regulator_config config = { };
e3e5aff7	189	int ret = 0;
605ebd35	190	u32 val;
e3e5aff7	191
e3e5aff7 YCLP	192	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
	193	if (!sreg)
	194	return -ENOMEM;
f2b269b8	195	sreg->name = of_get_property(np, "regulator-name", NULL);
e3e5aff7	196	rdesc = &sreg->rdesc;
e3e5aff7	197	rdesc->name = sreg->name;
e3e5aff7 YCLP	198	rdesc->type = REGULATOR_VOLTAGE;
e3e5aff7 YCLP	199	rdesc->owner = THIS_MODULE;
baa64151	200
072e78b1 JMC	201	initdata = of_get_regulator_init_data(dev, np, rdesc);
	202	sreg->initdata = initdata;
	203
baa64151 DA	204	anatop_np = of_get_parent(np);
	205	if (!anatop_np)
	206	return -ENODEV;
	207	sreg->anatop = syscon_node_to_regmap(anatop_np);
	208	of_node_put(anatop_np);
	209	if (IS_ERR(sreg->anatop))
	210	return PTR_ERR(sreg->anatop);
	211
2f2cc27f YCLP	212	ret = of_property_read_u32(np, "anatop-reg-offset",
2f2cc27f YCLP	213	&sreg->control_reg);
e3e5aff7	214	if (ret) {
2f2cc27f	215	dev_err(dev, "no anatop-reg-offset property set\n");
f2b269b8	216	return ret;
e3e5aff7 YCLP	217	}
	218	ret = of_property_read_u32(np, "anatop-vol-bit-width",
	219	&sreg->vol_bit_width);
	220	if (ret) {
	221	dev_err(dev, "no anatop-vol-bit-width property set\n");
f2b269b8	222	return ret;
e3e5aff7 YCLP	223	}
	224	ret = of_property_read_u32(np, "anatop-vol-bit-shift",
	225	&sreg->vol_bit_shift);
	226	if (ret) {
	227	dev_err(dev, "no anatop-vol-bit-shift property set\n");
f2b269b8	228	return ret;
e3e5aff7 YCLP	229	}
	230	ret = of_property_read_u32(np, "anatop-min-bit-val",
	231	&sreg->min_bit_val);
	232	if (ret) {
	233	dev_err(dev, "no anatop-min-bit-val property set\n");
f2b269b8	234	return ret;
e3e5aff7 YCLP	235	}
	236	ret = of_property_read_u32(np, "anatop-min-voltage",
	237	&sreg->min_voltage);
	238	if (ret) {
	239	dev_err(dev, "no anatop-min-voltage property set\n");
f2b269b8	240	return ret;
e3e5aff7 YCLP	241	}
	242	ret = of_property_read_u32(np, "anatop-max-voltage",
	243	&sreg->max_voltage);
	244	if (ret) {
	245	dev_err(dev, "no anatop-max-voltage property set\n");
f2b269b8	246	return ret;
e3e5aff7 YCLP	247	}
e3e5aff7 YCLP	248
9ee417c0 AH	249	/* read LDO ramp up setting, only for core reg */
	250	of_property_read_u32(np, "anatop-delay-reg-offset",
	251	&sreg->delay_reg);
	252	of_property_read_u32(np, "anatop-delay-bit-width",
	253	&sreg->delay_bit_width);
	254	of_property_read_u32(np, "anatop-delay-bit-shift",
	255	&sreg->delay_bit_shift);
	256
985884db AL	257	rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage) / 25000 + 1
985884db AL	258	+ sreg->min_bit_val;
0713e6ab AL	259	rdesc->min_uV = sreg->min_voltage;
0713e6ab AL	260	rdesc->uV_step = 25000;
985884db	261	rdesc->linear_min_sel = sreg->min_bit_val;
e1b0144f AL	262	rdesc->vsel_reg = sreg->control_reg;
	263	rdesc->vsel_mask = ((1 << sreg->vol_bit_width) - 1) <<
	264	sreg->vol_bit_shift;
e3e5aff7	265
d914d81b AL	266	config.dev = &pdev->dev;
	267	config.init_data = initdata;
	268	config.driver_data = sreg;
	269	config.of_node = pdev->dev.of_node;
e1b0144f	270	config.regmap = sreg->anatop;
d914d81b	271
605ebd35 PZ	272	/* Only core regulators have the ramp up delay configuration. */
	273	if (sreg->control_reg && sreg->delay_bit_width) {
	274	rdesc->ops = &anatop_core_rops;
	275
	276	ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
	277	if (ret) {
	278	dev_err(dev, "failed to read initial state\n");
	279	return ret;
	280	}
	281
	282	sreg->sel = (val & rdesc->vsel_mask) >> sreg->vol_bit_shift;
d38018f2 PZ	283	if (sreg->sel == LDO_FET_FULL_ON) {
	284	sreg->sel = 0;
	285	sreg->bypass = true;
	286	}
fe08be3e MP	287
	288	/*
	289	* In case vddpu was disabled by the bootloader, we need to set
	290	* a sane default until imx6-cpufreq was probed and changes the
	291	* voltage to the correct value. In this case we set 1.25V.
	292	*/
	293	if (!sreg->sel && !strcmp(sreg->name, "vddpu"))
	294	sreg->sel = 22;
da0607c8 MP	295
	296	if (!sreg->sel) {
	297	dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
	298	return -EINVAL;
	299	}
605ebd35 PZ	300	} else {
	301	rdesc->ops = &anatop_rops;
	302	}
	303
e3e5aff7	304	/* register regulator */
be1221e8	305	rdev = devm_regulator_register(dev, rdesc, &config);
e3e5aff7 YCLP	306	if (IS_ERR(rdev)) {
	307	dev_err(dev, "failed to register %s\n",
	308	rdesc->name);
f2b269b8	309	return PTR_ERR(rdev);
e3e5aff7 YCLP	310	}
	311
	312	platform_set_drvdata(pdev, rdev);
	313
e3e5aff7 YCLP	314	return 0;
	315	}
	316
a799baab	317	static const struct of_device_id of_anatop_regulator_match_tbl[] = {
e3e5aff7 YCLP	318	{ .compatible = "fsl,anatop-regulator", },
	319	{ /* end */ }
	320	};
d702ffd4	321	MODULE_DEVICE_TABLE(of, of_anatop_regulator_match_tbl);
e3e5aff7	322
c0d78c23	323	static struct platform_driver anatop_regulator_driver = {
e3e5aff7 YCLP	324	.driver = {
e3e5aff7 YCLP	325	.name = "anatop_regulator",
e3e5aff7 YCLP	326	.of_match_table = of_anatop_regulator_match_tbl,
	327	},
	328	.probe = anatop_regulator_probe,
e3e5aff7 YCLP	329	};
	330
	331	static int __init anatop_regulator_init(void)
	332	{
c0d78c23	333	return platform_driver_register(&anatop_regulator_driver);
e3e5aff7 YCLP	334	}
	335	postcore_initcall(anatop_regulator_init);
	336
	337	static void __exit anatop_regulator_exit(void)
	338	{
c0d78c23	339	platform_driver_unregister(&anatop_regulator_driver);
e3e5aff7 YCLP	340	}
	341	module_exit(anatop_regulator_exit);
	342
34f75685 JH	343	MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>");
34f75685 JH	344	MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
e3e5aff7 YCLP	345	MODULE_DESCRIPTION("ANATOP Regulator driver");
e3e5aff7 YCLP	346	MODULE_LICENSE("GPL v2");
89705b9e	347	MODULE_ALIAS("platform:anatop_regulator");