[linux-2.6-block.git] / drivers / regulator / anatop-regulator.c

// SPDX-License-Identifier: GPL-2.0+
//
// Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.

#include <linux/slab.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/of_regulator.h>
#include <linux/regulator/machine.h>

#define LDO_RAMP_UP_UNIT_IN_CYCLES      64 /* 64 cycles per step */
#define LDO_RAMP_UP_FREQ_IN_MHZ         24 /* cycle based on 24M OSC */

#define LDO_POWER_GATE			0x00
#define LDO_FET_FULL_ON			0x1f

struct anatop_regulator {
	u32 control_reg;
	struct regmap *anatop;
	int vol_bit_shift;
	int vol_bit_width;
	u32 delay_reg;
	int delay_bit_shift;
	int delay_bit_width;
	int min_bit_val;
	int min_voltage;
	int max_voltage;
	struct regulator_desc rdesc;
	struct regulator_init_data *initdata;
	bool bypass;
	int sel;
};

static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
	unsigned int old_sel,
	unsigned int new_sel)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	u32 val;
	int ret = 0;

	/* check whether need to care about LDO ramp up speed */
	if (anatop_reg->delay_bit_width && new_sel > old_sel) {
		/*
		 * the delay for LDO ramp up time is
		 * based on the register setting, we need
		 * to calculate how many steps LDO need to
		 * ramp up, and how much delay needed. (us)
		 */
		regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
		val = (val >> anatop_reg->delay_bit_shift) &
			((1 << anatop_reg->delay_bit_width) - 1);
		ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
			val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
	}

	return ret;
}

static int anatop_regmap_enable(struct regulator_dev *reg)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	int sel;

	sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
	return regulator_set_voltage_sel_regmap(reg, sel);
}

static int anatop_regmap_disable(struct regulator_dev *reg)
{
	return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
}

static int anatop_regmap_is_enabled(struct regulator_dev *reg)
{
	return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
}

static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
					      unsigned selector)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	int ret;

	if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) {
		anatop_reg->sel = selector;
		return 0;
	}

	ret = regulator_set_voltage_sel_regmap(reg, selector);
	if (!ret)
		anatop_reg->sel = selector;
	return ret;
}

static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);

	if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg))
		return anatop_reg->sel;

	return regulator_get_voltage_sel_regmap(reg);
}

static int anatop_regmap_get_bypass(struct regulator_dev *reg, bool *enable)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	int sel;

	sel = regulator_get_voltage_sel_regmap(reg);
	if (sel == LDO_FET_FULL_ON)
		WARN_ON(!anatop_reg->bypass);
	else if (sel != LDO_POWER_GATE)
		WARN_ON(anatop_reg->bypass);

	*enable = anatop_reg->bypass;
	return 0;
}

static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
{
	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	int sel;

	if (enable == anatop_reg->bypass)
		return 0;

	sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
	anatop_reg->bypass = enable;

	return regulator_set_voltage_sel_regmap(reg, sel);
}

static struct regulator_ops anatop_rops = {
	.set_voltage_sel = regulator_set_voltage_sel_regmap,
	.get_voltage_sel = regulator_get_voltage_sel_regmap,
	.list_voltage = regulator_list_voltage_linear,
	.map_voltage = regulator_map_voltage_linear,
};

static struct regulator_ops anatop_core_rops = {
	.enable = anatop_regmap_enable,
	.disable = anatop_regmap_disable,
	.is_enabled = anatop_regmap_is_enabled,
	.set_voltage_sel = anatop_regmap_core_set_voltage_sel,
	.set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
	.get_voltage_sel = anatop_regmap_core_get_voltage_sel,
	.list_voltage = regulator_list_voltage_linear,
	.map_voltage = regulator_map_voltage_linear,
	.get_bypass = anatop_regmap_get_bypass,
	.set_bypass = anatop_regmap_set_bypass,
};

static int anatop_regulator_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct device_node *anatop_np;
	struct regulator_desc *rdesc;
	struct regulator_dev *rdev;
	struct anatop_regulator *sreg;
	struct regulator_init_data *initdata;
	struct regulator_config config = { };
	int ret = 0;
	u32 val;

	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
	if (!sreg)
		return -ENOMEM;

	rdesc = &sreg->rdesc;
	rdesc->type = REGULATOR_VOLTAGE;
	rdesc->owner = THIS_MODULE;

	of_property_read_string(np, "regulator-name", &rdesc->name);
	if (!rdesc->name) {
		dev_err(dev, "failed to get a regulator-name\n");
		return -EINVAL;
	}

	initdata = of_get_regulator_init_data(dev, np, rdesc);
	if (!initdata)
		return -ENOMEM;

	initdata->supply_regulator = "vin";
	sreg->initdata = initdata;

	anatop_np = of_get_parent(np);
	if (!anatop_np)
		return -ENODEV;
	sreg->anatop = syscon_node_to_regmap(anatop_np);
	of_node_put(anatop_np);
	if (IS_ERR(sreg->anatop))
		return PTR_ERR(sreg->anatop);

	ret = of_property_read_u32(np, "anatop-reg-offset",
				   &sreg->control_reg);
	if (ret) {
		dev_err(dev, "no anatop-reg-offset property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-vol-bit-width",
				   &sreg->vol_bit_width);
	if (ret) {
		dev_err(dev, "no anatop-vol-bit-width property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-vol-bit-shift",
				   &sreg->vol_bit_shift);
	if (ret) {
		dev_err(dev, "no anatop-vol-bit-shift property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-min-bit-val",
				   &sreg->min_bit_val);
	if (ret) {
		dev_err(dev, "no anatop-min-bit-val property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-min-voltage",
				   &sreg->min_voltage);
	if (ret) {
		dev_err(dev, "no anatop-min-voltage property set\n");
		return ret;
	}
	ret = of_property_read_u32(np, "anatop-max-voltage",
				   &sreg->max_voltage);
	if (ret) {
		dev_err(dev, "no anatop-max-voltage property set\n");
		return ret;
	}

	/* read LDO ramp up setting, only for core reg */
	of_property_read_u32(np, "anatop-delay-reg-offset",
			     &sreg->delay_reg);
	of_property_read_u32(np, "anatop-delay-bit-width",
			     &sreg->delay_bit_width);
	of_property_read_u32(np, "anatop-delay-bit-shift",
			     &sreg->delay_bit_shift);

	rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage) / 25000 + 1
			    + sreg->min_bit_val;
	rdesc->min_uV = sreg->min_voltage;
	rdesc->uV_step = 25000;
	rdesc->linear_min_sel = sreg->min_bit_val;
	rdesc->vsel_reg = sreg->control_reg;
	rdesc->vsel_mask = ((1 << sreg->vol_bit_width) - 1) <<
			   sreg->vol_bit_shift;
	rdesc->min_dropout_uV = 125000;

	config.dev = &pdev->dev;
	config.init_data = initdata;
	config.driver_data = sreg;
	config.of_node = pdev->dev.of_node;
	config.regmap = sreg->anatop;

	/* Only core regulators have the ramp up delay configuration. */
	if (sreg->control_reg && sreg->delay_bit_width) {
		rdesc->ops = &anatop_core_rops;

		ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
		if (ret) {
			dev_err(dev, "failed to read initial state\n");
			return ret;
		}

		sreg->sel = (val & rdesc->vsel_mask) >> sreg->vol_bit_shift;
		if (sreg->sel == LDO_FET_FULL_ON) {
			sreg->sel = 0;
			sreg->bypass = true;
		}

		/*
		 * In case vddpu was disabled by the bootloader, we need to set
		 * a sane default until imx6-cpufreq was probed and changes the
		 * voltage to the correct value. In this case we set 1.25V.
		 */
		if (!sreg->sel && !strcmp(rdesc->name, "vddpu"))
			sreg->sel = 22;

		/* set the default voltage of the pcie phy to be 1.100v */
		if (!sreg->sel && !strcmp(rdesc->name, "vddpcie"))
			sreg->sel = 0x10;

		if (!sreg->bypass && !sreg->sel) {
			dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
			return -EINVAL;
		}
	} else {
		u32 enable_bit;

		rdesc->ops = &anatop_rops;

		if (!of_property_read_u32(np, "anatop-enable-bit",
					  &enable_bit)) {
			anatop_rops.enable  = regulator_enable_regmap;
			anatop_rops.disable = regulator_disable_regmap;
			anatop_rops.is_enabled = regulator_is_enabled_regmap;

			rdesc->enable_reg = sreg->control_reg;
			rdesc->enable_mask = BIT(enable_bit);
		}
	}

	/* register regulator */
	rdev = devm_regulator_register(dev, rdesc, &config);
	if (IS_ERR(rdev)) {
		dev_err(dev, "failed to register %s\n",
			rdesc->name);
		return PTR_ERR(rdev);
	}

	platform_set_drvdata(pdev, rdev);

	return 0;
}

static const struct of_device_id of_anatop_regulator_match_tbl[] = {
	{ .compatible = "fsl,anatop-regulator", },
	{ /* end */ }
};
MODULE_DEVICE_TABLE(of, of_anatop_regulator_match_tbl);

static struct platform_driver anatop_regulator_driver = {
	.driver = {
		.name	= "anatop_regulator",
		.of_match_table = of_anatop_regulator_match_tbl,
	},
	.probe	= anatop_regulator_probe,
};

static int __init anatop_regulator_init(void)
{
	return platform_driver_register(&anatop_regulator_driver);
}
postcore_initcall(anatop_regulator_init);

static void __exit anatop_regulator_exit(void)
{
	platform_driver_unregister(&anatop_regulator_driver);
}
module_exit(anatop_regulator_exit);

MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>");
MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
MODULE_DESCRIPTION("ANATOP Regulator driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:anatop_regulator");
Commit	Line	Data
c07bbfe7 FE	1	// SPDX-License-Identifier: GPL-2.0+
	2	//
	3	// Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
e3e5aff7 YCLP	4
	5	#include <linux/slab.h>
	6	#include <linux/device.h>
	7	#include <linux/module.h>
baa64151	8	#include <linux/mfd/syscon.h>
e3e5aff7 YCLP	9	#include <linux/err.h>
	10	#include <linux/io.h>
	11	#include <linux/platform_device.h>
	12	#include <linux/of.h>
	13	#include <linux/of_address.h>
baa64151	14	#include <linux/regmap.h>
e3e5aff7 YCLP	15	#include <linux/regulator/driver.h>
e3e5aff7 YCLP	16	#include <linux/regulator/of_regulator.h>
0d19208e	17	#include <linux/regulator/machine.h>
e3e5aff7	18
9ee417c0 AH	19	#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
	20	#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
	21
605ebd35	22	#define LDO_POWER_GATE 0x00
d38018f2	23	#define LDO_FET_FULL_ON 0x1f
605ebd35	24
e3e5aff7	25	struct anatop_regulator {
e3e5aff7	26	u32 control_reg;
baa64151	27	struct regmap *anatop;
e3e5aff7 YCLP	28	int vol_bit_shift;
e3e5aff7 YCLP	29	int vol_bit_width;
9ee417c0 AH	30	u32 delay_reg;
	31	int delay_bit_shift;
	32	int delay_bit_width;
e3e5aff7 YCLP	33	int min_bit_val;
	34	int min_voltage;
	35	int max_voltage;
	36	struct regulator_desc rdesc;
	37	struct regulator_init_data *initdata;
d38018f2	38	bool bypass;
605ebd35	39	int sel;
e3e5aff7 YCLP	40	};
e3e5aff7 YCLP	41
9ee417c0 AH	42	static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
	43	unsigned int old_sel,
	44	unsigned int new_sel)
	45	{
	46	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	47	u32 val;
	48	int ret = 0;
	49
	50	/* check whether need to care about LDO ramp up speed */
	51	if (anatop_reg->delay_bit_width && new_sel > old_sel) {
	52	/*
	53	* the delay for LDO ramp up time is
	54	* based on the register setting, we need
	55	* to calculate how many steps LDO need to
	56	* ramp up, and how much delay needed. (us)
	57	*/
	58	regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
	59	val = (val >> anatop_reg->delay_bit_shift) &
	60	((1 << anatop_reg->delay_bit_width) - 1);
ff1ce057 SG	61	ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
ff1ce057 SG	62	val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
9ee417c0 AH	63	}
	64
	65	return ret;
	66	}
	67
605ebd35 PZ	68	static int anatop_regmap_enable(struct regulator_dev *reg)
	69	{
	70	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
d38018f2	71	int sel;
605ebd35	72
d38018f2 PZ	73	sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
d38018f2 PZ	74	return regulator_set_voltage_sel_regmap(reg, sel);
605ebd35 PZ	75	}
	76
	77	static int anatop_regmap_disable(struct regulator_dev *reg)
	78	{
	79	return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
	80	}
	81
	82	static int anatop_regmap_is_enabled(struct regulator_dev *reg)
	83	{
	84	return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
	85	}
	86
	87	static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
	88	unsigned selector)
	89	{
	90	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	91	int ret;
	92
d38018f2	93	if (anatop_reg->bypass \|\| !anatop_regmap_is_enabled(reg)) {
605ebd35 PZ	94	anatop_reg->sel = selector;
	95	return 0;
	96	}
	97
	98	ret = regulator_set_voltage_sel_regmap(reg, selector);
	99	if (!ret)
	100	anatop_reg->sel = selector;
	101	return ret;
	102	}
	103
	104	static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
	105	{
	106	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	107
d38018f2	108	if (anatop_reg->bypass \|\| !anatop_regmap_is_enabled(reg))
605ebd35 PZ	109	return anatop_reg->sel;
	110
	111	return regulator_get_voltage_sel_regmap(reg);
	112	}
	113
d38018f2 PZ	114	static int anatop_regmap_get_bypass(struct regulator_dev reg, bool enable)
	115	{
	116	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	117	int sel;
	118
	119	sel = regulator_get_voltage_sel_regmap(reg);
	120	if (sel == LDO_FET_FULL_ON)
	121	WARN_ON(!anatop_reg->bypass);
	122	else if (sel != LDO_POWER_GATE)
	123	WARN_ON(anatop_reg->bypass);
	124
	125	*enable = anatop_reg->bypass;
	126	return 0;
	127	}
	128
	129	static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
	130	{
	131	struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
	132	int sel;
	133
	134	if (enable == anatop_reg->bypass)
	135	return 0;
	136
	137	sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
	138	anatop_reg->bypass = enable;
	139
	140	return regulator_set_voltage_sel_regmap(reg, sel);
	141	}
	142
e3e5aff7	143	static struct regulator_ops anatop_rops = {
114c5748 AL	144	.set_voltage_sel = regulator_set_voltage_sel_regmap,
114c5748 AL	145	.get_voltage_sel = regulator_get_voltage_sel_regmap,
d01c3a1e AL	146	.list_voltage = regulator_list_voltage_linear,
d01c3a1e AL	147	.map_voltage = regulator_map_voltage_linear,
e3e5aff7 YCLP	148	};
e3e5aff7 YCLP	149
605ebd35 PZ	150	static struct regulator_ops anatop_core_rops = {
	151	.enable = anatop_regmap_enable,
	152	.disable = anatop_regmap_disable,
	153	.is_enabled = anatop_regmap_is_enabled,
	154	.set_voltage_sel = anatop_regmap_core_set_voltage_sel,
	155	.set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
	156	.get_voltage_sel = anatop_regmap_core_get_voltage_sel,
	157	.list_voltage = regulator_list_voltage_linear,
	158	.map_voltage = regulator_map_voltage_linear,
d38018f2 PZ	159	.get_bypass = anatop_regmap_get_bypass,
d38018f2 PZ	160	.set_bypass = anatop_regmap_set_bypass,
605ebd35 PZ	161	};
605ebd35 PZ	162
a5023574	163	static int anatop_regulator_probe(struct platform_device *pdev)
e3e5aff7 YCLP	164	{
	165	struct device *dev = &pdev->dev;
	166	struct device_node *np = dev->of_node;
baa64151	167	struct device_node *anatop_np;
e3e5aff7 YCLP	168	struct regulator_desc *rdesc;
	169	struct regulator_dev *rdev;
	170	struct anatop_regulator *sreg;
	171	struct regulator_init_data *initdata;
d914d81b	172	struct regulator_config config = { };
e3e5aff7	173	int ret = 0;
605ebd35	174	u32 val;
e3e5aff7	175
e3e5aff7 YCLP	176	sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
	177	if (!sreg)
	178	return -ENOMEM;
5062e047	179
e3e5aff7	180	rdesc = &sreg->rdesc;
e3e5aff7 YCLP	181	rdesc->type = REGULATOR_VOLTAGE;
e3e5aff7 YCLP	182	rdesc->owner = THIS_MODULE;
baa64151	183
aeb1404d	184	of_property_read_string(np, "regulator-name", &rdesc->name);
4af5924c DA	185	if (!rdesc->name) {
	186	dev_err(dev, "failed to get a regulator-name\n");
	187	return -EINVAL;
	188	}
aeb1404d	189
072e78b1	190	initdata = of_get_regulator_init_data(dev, np, rdesc);
7f51cf2e DA	191	if (!initdata)
	192	return -ENOMEM;
	193
0d19208e	194	initdata->supply_regulator = "vin";
072e78b1 JMC	195	sreg->initdata = initdata;
072e78b1 JMC	196
baa64151 DA	197	anatop_np = of_get_parent(np);
	198	if (!anatop_np)
	199	return -ENODEV;
	200	sreg->anatop = syscon_node_to_regmap(anatop_np);
	201	of_node_put(anatop_np);
	202	if (IS_ERR(sreg->anatop))
	203	return PTR_ERR(sreg->anatop);
	204
2f2cc27f YCLP	205	ret = of_property_read_u32(np, "anatop-reg-offset",
2f2cc27f YCLP	206	&sreg->control_reg);
e3e5aff7	207	if (ret) {
2f2cc27f	208	dev_err(dev, "no anatop-reg-offset property set\n");
f2b269b8	209	return ret;
e3e5aff7 YCLP	210	}
	211	ret = of_property_read_u32(np, "anatop-vol-bit-width",
	212	&sreg->vol_bit_width);
	213	if (ret) {
	214	dev_err(dev, "no anatop-vol-bit-width property set\n");
f2b269b8	215	return ret;
e3e5aff7 YCLP	216	}
	217	ret = of_property_read_u32(np, "anatop-vol-bit-shift",
	218	&sreg->vol_bit_shift);
	219	if (ret) {
	220	dev_err(dev, "no anatop-vol-bit-shift property set\n");
f2b269b8	221	return ret;
e3e5aff7 YCLP	222	}
	223	ret = of_property_read_u32(np, "anatop-min-bit-val",
	224	&sreg->min_bit_val);
	225	if (ret) {
	226	dev_err(dev, "no anatop-min-bit-val property set\n");
f2b269b8	227	return ret;
e3e5aff7 YCLP	228	}
	229	ret = of_property_read_u32(np, "anatop-min-voltage",
	230	&sreg->min_voltage);
	231	if (ret) {
	232	dev_err(dev, "no anatop-min-voltage property set\n");
f2b269b8	233	return ret;
e3e5aff7 YCLP	234	}
	235	ret = of_property_read_u32(np, "anatop-max-voltage",
	236	&sreg->max_voltage);
	237	if (ret) {
	238	dev_err(dev, "no anatop-max-voltage property set\n");
f2b269b8	239	return ret;
e3e5aff7 YCLP	240	}
e3e5aff7 YCLP	241
9ee417c0 AH	242	/* read LDO ramp up setting, only for core reg */
	243	of_property_read_u32(np, "anatop-delay-reg-offset",
	244	&sreg->delay_reg);
	245	of_property_read_u32(np, "anatop-delay-bit-width",
	246	&sreg->delay_bit_width);
	247	of_property_read_u32(np, "anatop-delay-bit-shift",
	248	&sreg->delay_bit_shift);
	249
985884db AL	250	rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage) / 25000 + 1
985884db AL	251	+ sreg->min_bit_val;
0713e6ab AL	252	rdesc->min_uV = sreg->min_voltage;
0713e6ab AL	253	rdesc->uV_step = 25000;
985884db	254	rdesc->linear_min_sel = sreg->min_bit_val;
e1b0144f AL	255	rdesc->vsel_reg = sreg->control_reg;
	256	rdesc->vsel_mask = ((1 << sreg->vol_bit_width) - 1) <<
	257	sreg->vol_bit_shift;
0d19208e	258	rdesc->min_dropout_uV = 125000;
e3e5aff7	259
d914d81b AL	260	config.dev = &pdev->dev;
	261	config.init_data = initdata;
	262	config.driver_data = sreg;
	263	config.of_node = pdev->dev.of_node;
e1b0144f	264	config.regmap = sreg->anatop;
d914d81b	265
605ebd35 PZ	266	/* Only core regulators have the ramp up delay configuration. */
	267	if (sreg->control_reg && sreg->delay_bit_width) {
	268	rdesc->ops = &anatop_core_rops;
	269
	270	ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
	271	if (ret) {
	272	dev_err(dev, "failed to read initial state\n");
	273	return ret;
	274	}
	275
	276	sreg->sel = (val & rdesc->vsel_mask) >> sreg->vol_bit_shift;
d38018f2 PZ	277	if (sreg->sel == LDO_FET_FULL_ON) {
	278	sreg->sel = 0;
	279	sreg->bypass = true;
	280	}
fe08be3e MP	281
	282	/*
	283	* In case vddpu was disabled by the bootloader, we need to set
	284	* a sane default until imx6-cpufreq was probed and changes the
	285	* voltage to the correct value. In this case we set 1.25V.
	286	*/
aeb1404d	287	if (!sreg->sel && !strcmp(rdesc->name, "vddpu"))
fe08be3e	288	sreg->sel = 22;
da0607c8	289
9bf94454	290	/* set the default voltage of the pcie phy to be 1.100v */
4af5924c	291	if (!sreg->sel && !strcmp(rdesc->name, "vddpcie"))
9bf94454 DA	292	sreg->sel = 0x10;
9bf94454 DA	293
8a092e68	294	if (!sreg->bypass && !sreg->sel) {
da0607c8 MP	295	dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
	296	return -EINVAL;
	297	}
605ebd35	298	} else {
ca7734ad AS	299	u32 enable_bit;
ca7734ad AS	300
605ebd35	301	rdesc->ops = &anatop_rops;
ca7734ad AS	302
	303	if (!of_property_read_u32(np, "anatop-enable-bit",
	304	&enable_bit)) {
	305	anatop_rops.enable = regulator_enable_regmap;
	306	anatop_rops.disable = regulator_disable_regmap;
	307	anatop_rops.is_enabled = regulator_is_enabled_regmap;
	308
	309	rdesc->enable_reg = sreg->control_reg;
	310	rdesc->enable_mask = BIT(enable_bit);
	311	}
605ebd35 PZ	312	}
605ebd35 PZ	313
e3e5aff7	314	/* register regulator */
be1221e8	315	rdev = devm_regulator_register(dev, rdesc, &config);
e3e5aff7 YCLP	316	if (IS_ERR(rdev)) {
	317	dev_err(dev, "failed to register %s\n",
	318	rdesc->name);
f2b269b8	319	return PTR_ERR(rdev);
e3e5aff7 YCLP	320	}
	321
	322	platform_set_drvdata(pdev, rdev);
	323
e3e5aff7 YCLP	324	return 0;
	325	}
	326
a799baab	327	static const struct of_device_id of_anatop_regulator_match_tbl[] = {
e3e5aff7 YCLP	328	{ .compatible = "fsl,anatop-regulator", },
	329	{ /* end */ }
	330	};
d702ffd4	331	MODULE_DEVICE_TABLE(of, of_anatop_regulator_match_tbl);
e3e5aff7	332
c0d78c23	333	static struct platform_driver anatop_regulator_driver = {
e3e5aff7 YCLP	334	.driver = {
e3e5aff7 YCLP	335	.name = "anatop_regulator",
e3e5aff7 YCLP	336	.of_match_table = of_anatop_regulator_match_tbl,
	337	},
	338	.probe = anatop_regulator_probe,
e3e5aff7 YCLP	339	};
	340
	341	static int __init anatop_regulator_init(void)
	342	{
c0d78c23	343	return platform_driver_register(&anatop_regulator_driver);
e3e5aff7 YCLP	344	}
	345	postcore_initcall(anatop_regulator_init);
	346
	347	static void __exit anatop_regulator_exit(void)
	348	{
c0d78c23	349	platform_driver_unregister(&anatop_regulator_driver);
e3e5aff7 YCLP	350	}
	351	module_exit(anatop_regulator_exit);
	352
34f75685 JH	353	MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>");
34f75685 JH	354	MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
e3e5aff7 YCLP	355	MODULE_DESCRIPTION("ANATOP Regulator driver");
e3e5aff7 YCLP	356	MODULE_LICENSE("GPL v2");
89705b9e	357	MODULE_ALIAS("platform:anatop_regulator");