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regulator: ab8500-ext: Remove get_voltage to avoid duplicate implementation
[linux-block.git] / drivers / regulator / ab8500.c
CommitLineData
c789ca20
SI		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
e1159e6d
BJ		 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
547f384f 8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
c789ca20
SI		 9 *
10 * AB8500 peripheral regulators
11 *
e1159e6d 12 * AB8500 supports the following regulators:
ea05ef31 13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
547f384f
LJ		 14 *
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
c789ca20
SI		 17 */
18#include <linux/init.h>
19#include <linux/kernel.h>
65602c32 20#include <linux/module.h>
c789ca20
SI		 21#include <linux/err.h>
22#include <linux/platform_device.h>
47c16975 23#include <linux/mfd/abx500.h>
ee66e653 24#include <linux/mfd/abx500/ab8500.h>
3a8334b9
LJ		 25#include <linux/of.h>
26#include <linux/regulator/of_regulator.h>
c789ca20
SI		 27#include <linux/regulator/driver.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/ab8500.h>
3a8334b9 30#include <linux/slab.h>
c789ca20 31
3fe52289
LJ		 32/**
33 * struct ab8500_shared_mode - is used when mode is shared between
34 * two regulators.
35 * @shared_regulator: pointer to the other sharing regulator
36 * @lp_mode_req: low power mode requested by this regulator
37 */
38struct ab8500_shared_mode {
39 struct ab8500_regulator_info *shared_regulator;
40 bool lp_mode_req;
41};
42
c789ca20
SI		 43/**
44 * struct ab8500_regulator_info - ab8500 regulator information
e1159e6d 45 * @dev: device pointer
c789ca20 46 * @desc: regulator description
c789ca20 47 * @regulator_dev: regulator device
3fe52289 48 * @shared_mode: used when mode is shared between two regulators
7ce4669c 49 * @load_lp_uA: maximum load in idle (low power) mode
47c16975 50 * @update_bank: bank to control on/off
c789ca20 51 * @update_reg: register to control on/off
bd28a157
EV		 52 * @update_mask: mask to enable/disable and set mode of regulator
53 * @update_val: bits holding the regulator current mode
54 * @update_val_idle: bits to enable the regulator in idle (low power) mode
55 * @update_val_normal: bits to enable the regulator in normal (high power) mode
3fe52289
LJ		 56 * @mode_bank: bank with location of mode register
57 * @mode_reg: mode register
58 * @mode_mask: mask for setting mode
59 * @mode_val_idle: mode setting for low power
60 * @mode_val_normal: mode setting for normal power
47c16975 61 * @voltage_bank: bank to control regulator voltage
c789ca20
SI		 62 * @voltage_reg: register to control regulator voltage
63 * @voltage_mask: mask to control regulator voltage
a0a7014c 64 * @voltage_shift: shift to control regulator voltage
c789ca20
SI		 65 */
66struct ab8500_regulator_info {
67 struct device *dev;
68 struct regulator_desc desc;
c789ca20 69 struct regulator_dev *regulator;
3fe52289 70 struct ab8500_shared_mode *shared_mode;
7ce4669c 71 int load_lp_uA;
47c16975
MW		 72 u8 update_bank;
73 u8 update_reg;
e1159e6d 74 u8 update_mask;
bd28a157
EV		 75 u8 update_val;
76 u8 update_val_idle;
77 u8 update_val_normal;
3fe52289
LJ		 78 u8 mode_bank;
79 u8 mode_reg;
80 u8 mode_mask;
81 u8 mode_val_idle;
82 u8 mode_val_normal;
47c16975
MW		 83 u8 voltage_bank;
84 u8 voltage_reg;
85 u8 voltage_mask;
a0a7014c 86 u8 voltage_shift;
d7607baf
LJ		 87 struct {
88 u8 voltage_limit;
89 u8 voltage_bank;
90 u8 voltage_reg;
91 u8 voltage_mask;
92 u8 voltage_shift;
93 } expand_register;
c789ca20
SI		 94};
95
96/* voltage tables for the vauxn/vintcore supplies */
ec1cc4d9 97static const unsigned int ldo_vauxn_voltages[] = {
c789ca20
SI		 98 1100000,
99 1200000,
100 1300000,
101 1400000,
102 1500000,
103 1800000,
104 1850000,
105 1900000,
106 2500000,
107 2650000,
108 2700000,
109 2750000,
110 2800000,
111 2900000,
112 3000000,
113 3300000,
114};
115
ec1cc4d9 116static const unsigned int ldo_vaux3_voltages[] = {
2b75151a
BJ		 117 1200000,
118 1500000,
119 1800000,
120 2100000,
121 2500000,
122 2750000,
123 2790000,
124 2910000,
125};
126
62ab4111 127static const unsigned int ldo_vaux56_voltages[] = {
547f384f
LJ		 128 1800000,
129 1050000,
130 1100000,
131 1200000,
132 1500000,
133 2200000,
134 2500000,
135 2790000,
136};
137
62ab4111 138static const unsigned int ldo_vaux3_ab8540_voltages[] = {
ae0a9a3e
LJ		 139 1200000,
140 1500000,
141 1800000,
142 2100000,
143 2500000,
144 2750000,
145 2790000,
146 2910000,
147 3050000,
148};
149
684d5ce4
ZH		 150static const unsigned int ldo_vaux56_ab8540_voltages[] = {
151 750000, 760000, 770000, 780000, 790000, 800000,
152 810000, 820000, 830000, 840000, 850000, 860000,
153 870000, 880000, 890000, 900000, 910000, 920000,
154 930000, 940000, 950000, 960000, 970000, 980000,
155 990000, 1000000, 1010000, 1020000, 1030000,
156 1040000, 1050000, 1060000, 1070000, 1080000,
157 1090000, 1100000, 1110000, 1120000, 1130000,
158 1140000, 1150000, 1160000, 1170000, 1180000,
159 1190000, 1200000, 1210000, 1220000, 1230000,
160 1240000, 1250000, 1260000, 1270000, 1280000,
161 1290000, 1300000, 1310000, 1320000, 1330000,
162 1340000, 1350000, 1360000, 1800000, 2790000,
163};
164
ec1cc4d9 165static const unsigned int ldo_vintcore_voltages[] = {
c789ca20
SI		 166 1200000,
167 1225000,
168 1250000,
169 1275000,
170 1300000,
171 1325000,
172 1350000,
173};
174
62ab4111 175static const unsigned int ldo_sdio_voltages[] = {
ae0a9a3e
LJ		 176 1160000,
177 1050000,
178 1100000,
179 1500000,
180 1800000,
181 2200000,
182 2910000,
183 3050000,
184};
185
b080c78a
LJ		 186static const unsigned int fixed_1200000_voltage[] = {
187 1200000,
188};
189
190static const unsigned int fixed_1800000_voltage[] = {
191 1800000,
192};
193
194static const unsigned int fixed_2000000_voltage[] = {
195 2000000,
196};
197
198static const unsigned int fixed_2050000_voltage[] = {
199 2050000,
200};
201
202static const unsigned int fixed_3300000_voltage[] = {
203 3300000,
204};
205
8a3b1b87
LJ		 206static const unsigned int ldo_vana_voltages[] = {
207 1050000,
208 1075000,
209 1100000,
210 1125000,
211 1150000,
212 1175000,
213 1200000,
214 1225000,
215};
216
217static const unsigned int ldo_vaudio_voltages[] = {
218 2000000,
219 2100000,
220 2200000,
221 2300000,
222 2400000,
223 2500000,
224 2600000,
225 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
226};
227
4c84b4dd
LJ		 228static const unsigned int ldo_vdmic_voltages[] = {
229 1800000,
230 1900000,
231 2000000,
232 2850000,
233};
234
3fe52289
LJ		 235static DEFINE_MUTEX(shared_mode_mutex);
236static struct ab8500_shared_mode ldo_anamic1_shared;
237static struct ab8500_shared_mode ldo_anamic2_shared;
4c84b4dd
LJ		 238static struct ab8500_shared_mode ab8540_ldo_anamic1_shared;
239static struct ab8500_shared_mode ab8540_ldo_anamic2_shared;
3fe52289 240
c789ca20
SI		 241static int ab8500_regulator_enable(struct regulator_dev *rdev)
242{
fc24b426 243 int ret;
c789ca20
SI		 244 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
245
fc24b426
BJ		 246 if (info == NULL) {
247 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 248 return -EINVAL;
fc24b426 249 }
c789ca20 250
47c16975 251 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d 252 info->update_bank, info->update_reg,
bd28a157 253 info->update_mask, info->update_val);
f71bf528 254 if (ret < 0) {
c789ca20
SI		 255 dev_err(rdev_get_dev(rdev),
256 "couldn't set enable bits for regulator\n");
f71bf528
AL		 257 return ret;
258 }
09aefa12
BJ		 259
260 dev_vdbg(rdev_get_dev(rdev),
261 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
262 info->desc.name, info->update_bank, info->update_reg,
bd28a157 263 info->update_mask, info->update_val);
09aefa12 264
c789ca20
SI		 265 return ret;
266}
267
268static int ab8500_regulator_disable(struct regulator_dev *rdev)
269{
fc24b426 270 int ret;
c789ca20
SI		 271 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
272
fc24b426
BJ		 273 if (info == NULL) {
274 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 275 return -EINVAL;
fc24b426 276 }
c789ca20 277
47c16975 278 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d
BJ		 279 info->update_bank, info->update_reg,
280 info->update_mask, 0x0);
f71bf528 281 if (ret < 0) {
c789ca20
SI		 282 dev_err(rdev_get_dev(rdev),
283 "couldn't set disable bits for regulator\n");
f71bf528
AL		 284 return ret;
285 }
09aefa12
BJ		 286
287 dev_vdbg(rdev_get_dev(rdev),
288 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
289 info->desc.name, info->update_bank, info->update_reg,
290 info->update_mask, 0x0);
291
c789ca20
SI		 292 return ret;
293}
294
438e695b
AL		 295static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
296{
297 int ret;
298 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
299 u8 regval;
300
301 if (info == NULL) {
302 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
303 return -EINVAL;
304 }
305
306 ret = abx500_get_register_interruptible(info->dev,
307 info->update_bank, info->update_reg, &regval);
308 if (ret < 0) {
309 dev_err(rdev_get_dev(rdev),
310 "couldn't read 0x%x register\n", info->update_reg);
311 return ret;
312 }
313
314 dev_vdbg(rdev_get_dev(rdev),
315 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
316 " 0x%x\n",
317 info->desc.name, info->update_bank, info->update_reg,
318 info->update_mask, regval);
319
320 if (regval & info->update_mask)
321 return 1;
322 else
323 return 0;
324}
325
7ce4669c
BJ		 326static unsigned int ab8500_regulator_get_optimum_mode(
327 struct regulator_dev *rdev, int input_uV,
328 int output_uV, int load_uA)
329{
330 unsigned int mode;
331
332 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
333
334 if (info == NULL) {
335 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
336 return -EINVAL;
337 }
338
339 if (load_uA <= info->load_lp_uA)
340 mode = REGULATOR_MODE_IDLE;
341 else
342 mode = REGULATOR_MODE_NORMAL;
343
344 return mode;
345}
346
bd28a157
EV		 347static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
348 unsigned int mode)
349{
3fe52289
LJ		 350 int ret = 0;
351 u8 bank;
352 u8 reg;
353 u8 mask;
354 u8 val;
355 bool dmr = false; /* Dedicated mode register */
bd28a157
EV		 356 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
357
358 if (info == NULL) {
359 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
360 return -EINVAL;
361 }
362
3fe52289
LJ		 363 if (info->shared_mode) {
364 /*
365 * Special case where mode is shared between two regulators.
366 */
367 struct ab8500_shared_mode *sm = info->shared_mode;
368 mutex_lock(&shared_mode_mutex);
369
370 if (mode == REGULATOR_MODE_IDLE) {
371 sm->lp_mode_req = true; /* Low power mode requested */
372 if (!((sm->shared_regulator)->
373 shared_mode->lp_mode_req)) {
374 mutex_unlock(&shared_mode_mutex);
375 return 0; /* Other regulator prevent LP mode */
376 }
377 } else {
378 sm->lp_mode_req = false;
379 }
380 }
381
382 if (info->mode_mask) {
383 /* Dedicated register for handling mode */
384
385 dmr = true;
386
387 switch (mode) {
388 case REGULATOR_MODE_NORMAL:
389 val = info->mode_val_normal;
390 break;
391 case REGULATOR_MODE_IDLE:
392 val = info->mode_val_idle;
393 break;
394 default:
395 if (info->shared_mode)
396 mutex_unlock(&shared_mode_mutex);
397 return -EINVAL;
398 }
399
400 bank = info->mode_bank;
401 reg = info->mode_reg;
402 mask = info->mode_mask;
403 } else {
404 /* Mode register same as enable register */
405
406 switch (mode) {
407 case REGULATOR_MODE_NORMAL:
408 info->update_val = info->update_val_normal;
409 val = info->update_val_normal;
410 break;
411 case REGULATOR_MODE_IDLE:
412 info->update_val = info->update_val_idle;
413 val = info->update_val_idle;
414 break;
415 default:
416 if (info->shared_mode)
417 mutex_unlock(&shared_mode_mutex);
418 return -EINVAL;
419 }
420
421 bank = info->update_bank;
422 reg = info->update_reg;
423 mask = info->update_mask;
bd28a157
EV		 424 }
425
438e695b 426 if (dmr || ab8500_regulator_is_enabled(rdev)) {
bd28a157 427 ret = abx500_mask_and_set_register_interruptible(info->dev,
3fe52289
LJ		 428 bank, reg, mask, val);
429 if (ret < 0)
bd28a157
EV		 430 dev_err(rdev_get_dev(rdev),
431 "couldn't set regulator mode\n");
7ce4669c
BJ		 432
433 dev_vdbg(rdev_get_dev(rdev),
434 "%s-set_mode (bank, reg, mask, value): "
435 "0x%x, 0x%x, 0x%x, 0x%x\n",
3fe52289
LJ		 436 info->desc.name, bank, reg,
437 mask, val);
bd28a157
EV		 438 }
439
3fe52289
LJ		 440 if (info->shared_mode)
441 mutex_unlock(&shared_mode_mutex);
742a7325 442
3fe52289 443 return ret;
bd28a157
EV		 444}
445
446static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
447{
448 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
449 int ret;
3fe52289
LJ		 450 u8 val;
451 u8 val_normal;
452 u8 val_idle;
bd28a157
EV		 453
454 if (info == NULL) {
455 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
456 return -EINVAL;
457 }
458
3fe52289
LJ		 459 /* Need special handling for shared mode */
460 if (info->shared_mode) {
461 if (info->shared_mode->lp_mode_req)
462 return REGULATOR_MODE_IDLE;
463 else
464 return REGULATOR_MODE_NORMAL;
465 }
466
467 if (info->mode_mask) {
468 /* Dedicated register for handling mode */
469 ret = abx500_get_register_interruptible(info->dev,
470 info->mode_bank, info->mode_reg, &val);
471 val = val & info->mode_mask;
472
473 val_normal = info->mode_val_normal;
474 val_idle = info->mode_val_idle;
475 } else {
476 /* Mode register same as enable register */
477 val = info->update_val;
478 val_normal = info->update_val_normal;
479 val_idle = info->update_val_idle;
480 }
481
482 if (val == val_normal)
bd28a157 483 ret = REGULATOR_MODE_NORMAL;
3fe52289 484 else if (val == val_idle)
bd28a157
EV		 485 ret = REGULATOR_MODE_IDLE;
486 else
487 ret = -EINVAL;
488
489 return ret;
490}
491
3bf6e90e 492static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
c789ca20 493{
09aefa12 494 int ret, val;
c789ca20 495 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 496 u8 regval;
c789ca20 497
fc24b426
BJ		 498 if (info == NULL) {
499 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 500 return -EINVAL;
fc24b426 501 }
c789ca20 502
09aefa12
BJ		 503 ret = abx500_get_register_interruptible(info->dev,
504 info->voltage_bank, info->voltage_reg, &regval);
c789ca20
SI		 505 if (ret < 0) {
506 dev_err(rdev_get_dev(rdev),
507 "couldn't read voltage reg for regulator\n");
508 return ret;
509 }
510
09aefa12 511 dev_vdbg(rdev_get_dev(rdev),
a0a7014c
LW		 512 "%s-get_voltage (bank, reg, mask, shift, value): "
513 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
514 info->desc.name, info->voltage_bank,
515 info->voltage_reg, info->voltage_mask,
516 info->voltage_shift, regval);
09aefa12 517
09aefa12 518 val = regval & info->voltage_mask;
a0a7014c 519 return val >> info->voltage_shift;
c789ca20
SI		 520}
521
d7607baf
LJ		 522static int ab8540_aux3_regulator_get_voltage_sel(struct regulator_dev *rdev)
523{
524 int ret, val;
525 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
526 u8 regval, regval_expand;
527
528 if (info == NULL) {
529 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
530 return -EINVAL;
531 }
532
533 ret = abx500_get_register_interruptible(info->dev,
534 info->voltage_bank, info->voltage_reg, &regval);
535
536 if (ret < 0) {
537 dev_err(rdev_get_dev(rdev),
538 "couldn't read voltage reg for regulator\n");
539 return ret;
540 }
541
542 ret = abx500_get_register_interruptible(info->dev,
543 info->expand_register.voltage_bank,
544 info->expand_register.voltage_reg, &regval_expand);
545
546 if (ret < 0) {
547 dev_err(rdev_get_dev(rdev),
548 "couldn't read voltage reg for regulator\n");
549 return ret;
550 }
551
552 dev_vdbg(rdev_get_dev(rdev),
553 "%s-get_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
554 " 0x%x\n",
555 info->desc.name, info->voltage_bank, info->voltage_reg,
556 info->voltage_mask, regval);
557 dev_vdbg(rdev_get_dev(rdev),
558 "%s-get_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
559 " 0x%x\n",
560 info->desc.name, info->expand_register.voltage_bank,
561 info->expand_register.voltage_reg,
562 info->expand_register.voltage_mask, regval_expand);
563
564 if (regval_expand&(info->expand_register.voltage_mask))
565 /* Vaux3 has a different layout */
566 val = info->expand_register.voltage_limit;
567 else
568 val = (regval & info->voltage_mask) >> info->voltage_shift;
569
570 return val;
571}
572
ae713d39
AL		 573static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
574 unsigned selector)
c789ca20 575{
fc24b426 576 int ret;
c789ca20 577 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 578 u8 regval;
c789ca20 579
fc24b426
BJ		 580 if (info == NULL) {
581 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 582 return -EINVAL;
fc24b426 583 }
c789ca20 584
c789ca20 585 /* set the registers for the request */
a0a7014c 586 regval = (u8)selector << info->voltage_shift;
47c16975 587 ret = abx500_mask_and_set_register_interruptible(info->dev,
09aefa12
BJ		 588 info->voltage_bank, info->voltage_reg,
589 info->voltage_mask, regval);
c789ca20
SI		 590 if (ret < 0)
591 dev_err(rdev_get_dev(rdev),
592 "couldn't set voltage reg for regulator\n");
593
09aefa12
BJ		 594 dev_vdbg(rdev_get_dev(rdev),
595 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
596 " 0x%x\n",
597 info->desc.name, info->voltage_bank, info->voltage_reg,
598 info->voltage_mask, regval);
599
c789ca20
SI		 600 return ret;
601}
602
d7607baf
LJ		 603static int ab8540_aux3_regulator_set_voltage_sel(struct regulator_dev *rdev,
604 unsigned selector)
605{
606 int ret;
607 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
608 u8 regval;
609
610 if (info == NULL) {
611 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
612 return -EINVAL;
613 }
614
615 if (selector >= info->expand_register.voltage_limit) {
616 /* Vaux3 bit4 has different layout */
617 regval = (u8)selector << info->expand_register.voltage_shift;
618 ret = abx500_mask_and_set_register_interruptible(info->dev,
619 info->expand_register.voltage_bank,
620 info->expand_register.voltage_reg,
621 info->expand_register.voltage_mask,
622 regval);
623 } else {
624 /* set the registers for the request */
625 regval = (u8)selector << info->voltage_shift;
626 ret = abx500_mask_and_set_register_interruptible(info->dev,
627 info->voltage_bank, info->voltage_reg,
628 info->voltage_mask, regval);
629 }
630 if (ret < 0)
631 dev_err(rdev_get_dev(rdev),
632 "couldn't set voltage reg for regulator\n");
633
634 dev_vdbg(rdev_get_dev(rdev),
635 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
636 " 0x%x\n",
637 info->desc.name, info->voltage_bank, info->voltage_reg,
638 info->voltage_mask, regval);
639
640 return ret;
641}
642
7ce4669c
BJ		 643static struct regulator_ops ab8500_regulator_volt_mode_ops = {
644 .enable = ab8500_regulator_enable,
645 .disable = ab8500_regulator_disable,
646 .is_enabled = ab8500_regulator_is_enabled,
647 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
648 .set_mode = ab8500_regulator_set_mode,
649 .get_mode = ab8500_regulator_get_mode,
650 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
651 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
652 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 653};
654
d7607baf
LJ		 655static struct regulator_ops ab8540_aux3_regulator_volt_mode_ops = {
656 .enable = ab8500_regulator_enable,
657 .disable = ab8500_regulator_disable,
658 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
659 .set_mode = ab8500_regulator_set_mode,
660 .get_mode = ab8500_regulator_get_mode,
661 .is_enabled = ab8500_regulator_is_enabled,
662 .get_voltage_sel = ab8540_aux3_regulator_get_voltage_sel,
663 .set_voltage_sel = ab8540_aux3_regulator_set_voltage_sel,
664 .list_voltage = regulator_list_voltage_table,
d7607baf
LJ		 665};
666
8a3b1b87
LJ		 667static struct regulator_ops ab8500_regulator_volt_ops = {
668 .enable = ab8500_regulator_enable,
669 .disable = ab8500_regulator_disable,
670 .is_enabled = ab8500_regulator_is_enabled,
671 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
672 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
673 .list_voltage = regulator_list_voltage_table,
8a3b1b87
LJ		 674};
675
7ce4669c
BJ		 676static struct regulator_ops ab8500_regulator_mode_ops = {
677 .enable = ab8500_regulator_enable,
678 .disable = ab8500_regulator_disable,
679 .is_enabled = ab8500_regulator_is_enabled,
680 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
681 .set_mode = ab8500_regulator_set_mode,
682 .get_mode = ab8500_regulator_get_mode,
d7816ab0 683 .list_voltage = regulator_list_voltage_table,
7ce4669c
BJ		 684};
685
686static struct regulator_ops ab8500_regulator_ops = {
687 .enable = ab8500_regulator_enable,
688 .disable = ab8500_regulator_disable,
689 .is_enabled = ab8500_regulator_is_enabled,
d7816ab0 690 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 691};
692
3fe52289
LJ		 693static struct regulator_ops ab8500_regulator_anamic_mode_ops = {
694 .enable = ab8500_regulator_enable,
695 .disable = ab8500_regulator_disable,
696 .is_enabled = ab8500_regulator_is_enabled,
697 .set_mode = ab8500_regulator_set_mode,
698 .get_mode = ab8500_regulator_get_mode,
699 .list_voltage = regulator_list_voltage_table,
700};
701
8e6a8d7d 702/* AB8500 regulator information */
6909b452
BJ		 703static struct ab8500_regulator_info
704 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
c789ca20 705 /*
e1159e6d
BJ		 706 * Variable Voltage Regulators
707 * name, min mV, max mV,
708 * update bank, reg, mask, enable val
ec1cc4d9 709 * volt bank, reg, mask
c789ca20 710 */
6909b452
BJ		 711 [AB8500_LDO_AUX1] = {
712 .desc = {
713 .name = "LDO-AUX1",
7ce4669c 714 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 715 .type = REGULATOR_VOLTAGE,
716 .id = AB8500_LDO_AUX1,
717 .owner = THIS_MODULE,
718 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 719 .volt_table = ldo_vauxn_voltages,
530158b6 720 .enable_time = 200,
6909b452 721 },
7ce4669c 722 .load_lp_uA = 5000,
6909b452
BJ		 723 .update_bank = 0x04,
724 .update_reg = 0x09,
725 .update_mask = 0x03,
bd28a157
EV		 726 .update_val = 0x01,
727 .update_val_idle = 0x03,
728 .update_val_normal = 0x01,
6909b452
BJ		 729 .voltage_bank = 0x04,
730 .voltage_reg = 0x1f,
731 .voltage_mask = 0x0f,
6909b452
BJ		 732 },
733 [AB8500_LDO_AUX2] = {
734 .desc = {
735 .name = "LDO-AUX2",
7ce4669c 736 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 737 .type = REGULATOR_VOLTAGE,
738 .id = AB8500_LDO_AUX2,
739 .owner = THIS_MODULE,
740 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 741 .volt_table = ldo_vauxn_voltages,
530158b6 742 .enable_time = 200,
6909b452 743 },
7ce4669c 744 .load_lp_uA = 5000,
6909b452
BJ		 745 .update_bank = 0x04,
746 .update_reg = 0x09,
747 .update_mask = 0x0c,
bd28a157
EV		 748 .update_val = 0x04,
749 .update_val_idle = 0x0c,
750 .update_val_normal = 0x04,
6909b452
BJ		 751 .voltage_bank = 0x04,
752 .voltage_reg = 0x20,
753 .voltage_mask = 0x0f,
6909b452
BJ		 754 },
755 [AB8500_LDO_AUX3] = {
756 .desc = {
757 .name = "LDO-AUX3",
7ce4669c 758 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 759 .type = REGULATOR_VOLTAGE,
760 .id = AB8500_LDO_AUX3,
761 .owner = THIS_MODULE,
762 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
ec1cc4d9 763 .volt_table = ldo_vaux3_voltages,
530158b6 764 .enable_time = 450,
6909b452 765 },
7ce4669c 766 .load_lp_uA = 5000,
6909b452
BJ		 767 .update_bank = 0x04,
768 .update_reg = 0x0a,
769 .update_mask = 0x03,
bd28a157
EV		 770 .update_val = 0x01,
771 .update_val_idle = 0x03,
772 .update_val_normal = 0x01,
6909b452
BJ		 773 .voltage_bank = 0x04,
774 .voltage_reg = 0x21,
775 .voltage_mask = 0x07,
6909b452
BJ		 776 },
777 [AB8500_LDO_INTCORE] = {
778 .desc = {
779 .name = "LDO-INTCORE",
7ce4669c 780 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 781 .type = REGULATOR_VOLTAGE,
782 .id = AB8500_LDO_INTCORE,
783 .owner = THIS_MODULE,
784 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
ec1cc4d9 785 .volt_table = ldo_vintcore_voltages,
530158b6 786 .enable_time = 750,
6909b452 787 },
7ce4669c 788 .load_lp_uA = 5000,
6909b452
BJ		 789 .update_bank = 0x03,
790 .update_reg = 0x80,
791 .update_mask = 0x44,
cc40dc29 792 .update_val = 0x44,
bd28a157
EV		 793 .update_val_idle = 0x44,
794 .update_val_normal = 0x04,
6909b452
BJ		 795 .voltage_bank = 0x03,
796 .voltage_reg = 0x80,
797 .voltage_mask = 0x38,
a0a7014c 798 .voltage_shift = 3,
6909b452 799 },
c789ca20
SI		 800
801 /*
e1159e6d
BJ		 802 * Fixed Voltage Regulators
803 * name, fixed mV,
804 * update bank, reg, mask, enable val
c789ca20 805 */
6909b452
BJ		 806 [AB8500_LDO_TVOUT] = {
807 .desc = {
808 .name = "LDO-TVOUT",
7ce4669c 809 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 810 .type = REGULATOR_VOLTAGE,
811 .id = AB8500_LDO_TVOUT,
812 .owner = THIS_MODULE,
813 .n_voltages = 1,
b080c78a 814 .volt_table = fixed_2000000_voltage,
ed3c138e 815 .enable_time = 500,
6909b452 816 },
7ce4669c 817 .load_lp_uA = 1000,
6909b452
BJ		 818 .update_bank = 0x03,
819 .update_reg = 0x80,
820 .update_mask = 0x82,
bd28a157 821 .update_val = 0x02,
7ce4669c
BJ		 822 .update_val_idle = 0x82,
823 .update_val_normal = 0x02,
6909b452
BJ		 824 },
825 [AB8500_LDO_AUDIO] = {
826 .desc = {
827 .name = "LDO-AUDIO",
7ce4669c 828 .ops = &ab8500_regulator_ops,
6909b452
BJ		 829 .type = REGULATOR_VOLTAGE,
830 .id = AB8500_LDO_AUDIO,
831 .owner = THIS_MODULE,
832 .n_voltages = 1,
530158b6 833 .enable_time = 140,
b080c78a 834 .volt_table = fixed_2000000_voltage,
6909b452 835 },
6909b452
BJ		 836 .update_bank = 0x03,
837 .update_reg = 0x83,
838 .update_mask = 0x02,
bd28a157 839 .update_val = 0x02,
6909b452
BJ		 840 },
841 [AB8500_LDO_ANAMIC1] = {
842 .desc = {
843 .name = "LDO-ANAMIC1",
7ce4669c 844 .ops = &ab8500_regulator_ops,
6909b452
BJ		 845 .type = REGULATOR_VOLTAGE,
846 .id = AB8500_LDO_ANAMIC1,
847 .owner = THIS_MODULE,
848 .n_voltages = 1,
530158b6 849 .enable_time = 500,
b080c78a 850 .volt_table = fixed_2050000_voltage,
6909b452 851 },
6909b452
BJ		 852 .update_bank = 0x03,
853 .update_reg = 0x83,
854 .update_mask = 0x08,
bd28a157 855 .update_val = 0x08,
6909b452
BJ		 856 },
857 [AB8500_LDO_ANAMIC2] = {
858 .desc = {
859 .name = "LDO-ANAMIC2",
7ce4669c 860 .ops = &ab8500_regulator_ops,
6909b452
BJ		 861 .type = REGULATOR_VOLTAGE,
862 .id = AB8500_LDO_ANAMIC2,
863 .owner = THIS_MODULE,
864 .n_voltages = 1,
530158b6 865 .enable_time = 500,
b080c78a 866 .volt_table = fixed_2050000_voltage,
6909b452 867 },
6909b452
BJ		 868 .update_bank = 0x03,
869 .update_reg = 0x83,
870 .update_mask = 0x10,
bd28a157 871 .update_val = 0x10,
6909b452
BJ		 872 },
873 [AB8500_LDO_DMIC] = {
874 .desc = {
875 .name = "LDO-DMIC",
7ce4669c 876 .ops = &ab8500_regulator_ops,
6909b452
BJ		 877 .type = REGULATOR_VOLTAGE,
878 .id = AB8500_LDO_DMIC,
879 .owner = THIS_MODULE,
880 .n_voltages = 1,
530158b6 881 .enable_time = 420,
b080c78a 882 .volt_table = fixed_1800000_voltage,
6909b452 883 },
6909b452
BJ		 884 .update_bank = 0x03,
885 .update_reg = 0x83,
886 .update_mask = 0x04,
bd28a157 887 .update_val = 0x04,
6909b452 888 },
7ce4669c
BJ		 889
890 /*
891 * Regulators with fixed voltage and normal/idle modes
892 */
6909b452
BJ		 893 [AB8500_LDO_ANA] = {
894 .desc = {
895 .name = "LDO-ANA",
7ce4669c 896 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 897 .type = REGULATOR_VOLTAGE,
898 .id = AB8500_LDO_ANA,
899 .owner = THIS_MODULE,
900 .n_voltages = 1,
530158b6 901 .enable_time = 140,
b080c78a 902 .volt_table = fixed_1200000_voltage,
6909b452 903 },
7ce4669c 904 .load_lp_uA = 1000,
6909b452
BJ		 905 .update_bank = 0x04,
906 .update_reg = 0x06,
907 .update_mask = 0x0c,
bd28a157 908 .update_val = 0x04,
7ce4669c
BJ		 909 .update_val_idle = 0x0c,
910 .update_val_normal = 0x04,
6909b452 911 },
8e6a8d7d 912};
6909b452 913
547f384f
LJ		 914/* AB8505 regulator information */
915static struct ab8500_regulator_info
916 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
917 /*
918 * Variable Voltage Regulators
919 * name, min mV, max mV,
920 * update bank, reg, mask, enable val
d3193103 921 * volt bank, reg, mask
547f384f
LJ		 922 */
923 [AB8505_LDO_AUX1] = {
924 .desc = {
925 .name = "LDO-AUX1",
926 .ops = &ab8500_regulator_volt_mode_ops,
927 .type = REGULATOR_VOLTAGE,
0b946411 928 .id = AB8505_LDO_AUX1,
547f384f
LJ		 929 .owner = THIS_MODULE,
930 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 931 .volt_table = ldo_vauxn_voltages,
547f384f 932 },
547f384f
LJ		 933 .load_lp_uA = 5000,
934 .update_bank = 0x04,
935 .update_reg = 0x09,
936 .update_mask = 0x03,
937 .update_val = 0x01,
938 .update_val_idle = 0x03,
939 .update_val_normal = 0x01,
940 .voltage_bank = 0x04,
941 .voltage_reg = 0x1f,
942 .voltage_mask = 0x0f,
547f384f
LJ		 943 },
944 [AB8505_LDO_AUX2] = {
945 .desc = {
946 .name = "LDO-AUX2",
947 .ops = &ab8500_regulator_volt_mode_ops,
948 .type = REGULATOR_VOLTAGE,
0b946411 949 .id = AB8505_LDO_AUX2,
547f384f
LJ		 950 .owner = THIS_MODULE,
951 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 952 .volt_table = ldo_vauxn_voltages,
547f384f 953 },
547f384f
LJ		 954 .load_lp_uA = 5000,
955 .update_bank = 0x04,
956 .update_reg = 0x09,
957 .update_mask = 0x0c,
958 .update_val = 0x04,
959 .update_val_idle = 0x0c,
960 .update_val_normal = 0x04,
961 .voltage_bank = 0x04,
962 .voltage_reg = 0x20,
963 .voltage_mask = 0x0f,
547f384f
LJ		 964 },
965 [AB8505_LDO_AUX3] = {
966 .desc = {
967 .name = "LDO-AUX3",
968 .ops = &ab8500_regulator_volt_mode_ops,
969 .type = REGULATOR_VOLTAGE,
0b946411 970 .id = AB8505_LDO_AUX3,
547f384f
LJ		 971 .owner = THIS_MODULE,
972 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 973 .volt_table = ldo_vaux3_voltages,
547f384f 974 },
547f384f
LJ		 975 .load_lp_uA = 5000,
976 .update_bank = 0x04,
977 .update_reg = 0x0a,
978 .update_mask = 0x03,
979 .update_val = 0x01,
980 .update_val_idle = 0x03,
981 .update_val_normal = 0x01,
982 .voltage_bank = 0x04,
983 .voltage_reg = 0x21,
984 .voltage_mask = 0x07,
547f384f
LJ		 985 },
986 [AB8505_LDO_AUX4] = {
987 .desc = {
988 .name = "LDO-AUX4",
989 .ops = &ab8500_regulator_volt_mode_ops,
990 .type = REGULATOR_VOLTAGE,
0b946411 991 .id = AB8505_LDO_AUX4,
547f384f
LJ		 992 .owner = THIS_MODULE,
993 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 994 .volt_table = ldo_vauxn_voltages,
547f384f 995 },
547f384f
LJ		 996 .load_lp_uA = 5000,
997 /* values for Vaux4Regu register */
998 .update_bank = 0x04,
999 .update_reg = 0x2e,
1000 .update_mask = 0x03,
1001 .update_val = 0x01,
1002 .update_val_idle = 0x03,
1003 .update_val_normal = 0x01,
1004 /* values for Vaux4SEL register */
1005 .voltage_bank = 0x04,
1006 .voltage_reg = 0x2f,
1007 .voltage_mask = 0x0f,
547f384f
LJ		 1008 },
1009 [AB8505_LDO_AUX5] = {
1010 .desc = {
1011 .name = "LDO-AUX5",
1012 .ops = &ab8500_regulator_volt_mode_ops,
1013 .type = REGULATOR_VOLTAGE,
1014 .id = AB8505_LDO_AUX5,
1015 .owner = THIS_MODULE,
1016 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1017 .volt_table = ldo_vaux56_voltages,
547f384f 1018 },
547f384f
LJ		 1019 .load_lp_uA = 2000,
1020 /* values for CtrlVaux5 register */
1021 .update_bank = 0x01,
1022 .update_reg = 0x55,
ae0a9a3e
LJ		 1023 .update_mask = 0x18,
1024 .update_val = 0x10,
1025 .update_val_idle = 0x18,
1026 .update_val_normal = 0x10,
547f384f
LJ		 1027 .voltage_bank = 0x01,
1028 .voltage_reg = 0x55,
1029 .voltage_mask = 0x07,
547f384f
LJ		 1030 },
1031 [AB8505_LDO_AUX6] = {
1032 .desc = {
1033 .name = "LDO-AUX6",
1034 .ops = &ab8500_regulator_volt_mode_ops,
1035 .type = REGULATOR_VOLTAGE,
1036 .id = AB8505_LDO_AUX6,
1037 .owner = THIS_MODULE,
1038 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1039 .volt_table = ldo_vaux56_voltages,
547f384f 1040 },
547f384f
LJ		 1041 .load_lp_uA = 2000,
1042 /* values for CtrlVaux6 register */
1043 .update_bank = 0x01,
1044 .update_reg = 0x56,
ae0a9a3e
LJ		 1045 .update_mask = 0x18,
1046 .update_val = 0x10,
1047 .update_val_idle = 0x18,
1048 .update_val_normal = 0x10,
547f384f
LJ		 1049 .voltage_bank = 0x01,
1050 .voltage_reg = 0x56,
1051 .voltage_mask = 0x07,
547f384f
LJ		 1052 },
1053 [AB8505_LDO_INTCORE] = {
1054 .desc = {
1055 .name = "LDO-INTCORE",
1056 .ops = &ab8500_regulator_volt_mode_ops,
1057 .type = REGULATOR_VOLTAGE,
0b946411 1058 .id = AB8505_LDO_INTCORE,
547f384f
LJ		 1059 .owner = THIS_MODULE,
1060 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1061 .volt_table = ldo_vintcore_voltages,
547f384f 1062 },
547f384f
LJ		 1063 .load_lp_uA = 5000,
1064 .update_bank = 0x03,
1065 .update_reg = 0x80,
1066 .update_mask = 0x44,
1067 .update_val = 0x04,
1068 .update_val_idle = 0x44,
1069 .update_val_normal = 0x04,
1070 .voltage_bank = 0x03,
1071 .voltage_reg = 0x80,
1072 .voltage_mask = 0x38,
547f384f
LJ		 1073 .voltage_shift = 3,
1074 },
1075
1076 /*
1077 * Fixed Voltage Regulators
1078 * name, fixed mV,
1079 * update bank, reg, mask, enable val
1080 */
1081 [AB8505_LDO_ADC] = {
1082 .desc = {
1083 .name = "LDO-ADC",
1084 .ops = &ab8500_regulator_mode_ops,
1085 .type = REGULATOR_VOLTAGE,
1086 .id = AB8505_LDO_ADC,
1087 .owner = THIS_MODULE,
1088 .n_voltages = 1,
b080c78a 1089 .volt_table = fixed_2000000_voltage,
a4d68468 1090 .enable_time = 10000,
547f384f 1091 },
547f384f
LJ		 1092 .load_lp_uA = 1000,
1093 .update_bank = 0x03,
1094 .update_reg = 0x80,
1095 .update_mask = 0x82,
1096 .update_val = 0x02,
1097 .update_val_idle = 0x82,
1098 .update_val_normal = 0x02,
1099 },
1100 [AB8505_LDO_USB] = {
1101 .desc = {
1102 .name = "LDO-USB",
1103 .ops = &ab8500_regulator_mode_ops,
1104 .type = REGULATOR_VOLTAGE,
0b946411 1105 .id = AB8505_LDO_USB,
547f384f
LJ		 1106 .owner = THIS_MODULE,
1107 .n_voltages = 1,
b080c78a 1108 .volt_table = fixed_3300000_voltage,
547f384f 1109 },
547f384f
LJ		 1110 .update_bank = 0x03,
1111 .update_reg = 0x82,
1112 .update_mask = 0x03,
1113 .update_val = 0x01,
1114 .update_val_idle = 0x03,
1115 .update_val_normal = 0x01,
1116 },
1117 [AB8505_LDO_AUDIO] = {
1118 .desc = {
1119 .name = "LDO-AUDIO",
8a3b1b87 1120 .ops = &ab8500_regulator_volt_ops,
547f384f 1121 .type = REGULATOR_VOLTAGE,
0b946411 1122 .id = AB8505_LDO_AUDIO,
547f384f 1123 .owner = THIS_MODULE,
8a3b1b87
LJ		 1124 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
1125 .volt_table = ldo_vaudio_voltages,
547f384f 1126 },
547f384f
LJ		 1127 .update_bank = 0x03,
1128 .update_reg = 0x83,
1129 .update_mask = 0x02,
1130 .update_val = 0x02,
8a3b1b87
LJ		 1131 .voltage_bank = 0x01,
1132 .voltage_reg = 0x57,
1133 .voltage_mask = 0x7,
1134 .voltage_shift = 4,
547f384f
LJ		 1135 },
1136 [AB8505_LDO_ANAMIC1] = {
1137 .desc = {
1138 .name = "LDO-ANAMIC1",
3fe52289 1139 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1140 .type = REGULATOR_VOLTAGE,
0b946411 1141 .id = AB8505_LDO_ANAMIC1,
547f384f
LJ		 1142 .owner = THIS_MODULE,
1143 .n_voltages = 1,
b080c78a 1144 .volt_table = fixed_2050000_voltage,
547f384f 1145 },
4c84b4dd 1146 .shared_mode = &ldo_anamic1_shared,
547f384f
LJ		 1147 .update_bank = 0x03,
1148 .update_reg = 0x83,
1149 .update_mask = 0x08,
1150 .update_val = 0x08,
3fe52289
LJ		 1151 .mode_bank = 0x01,
1152 .mode_reg = 0x54,
1153 .mode_mask = 0x04,
1154 .mode_val_idle = 0x04,
1155 .mode_val_normal = 0x00,
547f384f
LJ		 1156 },
1157 [AB8505_LDO_ANAMIC2] = {
1158 .desc = {
1159 .name = "LDO-ANAMIC2",
3fe52289 1160 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1161 .type = REGULATOR_VOLTAGE,
0b946411 1162 .id = AB8505_LDO_ANAMIC2,
547f384f
LJ		 1163 .owner = THIS_MODULE,
1164 .n_voltages = 1,
b080c78a 1165 .volt_table = fixed_2050000_voltage,
547f384f 1166 },
3fe52289 1167 .shared_mode = &ldo_anamic2_shared,
547f384f
LJ		 1168 .update_bank = 0x03,
1169 .update_reg = 0x83,
1170 .update_mask = 0x10,
1171 .update_val = 0x10,
3fe52289
LJ		 1172 .mode_bank = 0x01,
1173 .mode_reg = 0x54,
1174 .mode_mask = 0x04,
1175 .mode_val_idle = 0x04,
1176 .mode_val_normal = 0x00,
547f384f
LJ		 1177 },
1178 [AB8505_LDO_AUX8] = {
1179 .desc = {
1180 .name = "LDO-AUX8",
1181 .ops = &ab8500_regulator_ops,
1182 .type = REGULATOR_VOLTAGE,
1183 .id = AB8505_LDO_AUX8,
1184 .owner = THIS_MODULE,
1185 .n_voltages = 1,
b080c78a 1186 .volt_table = fixed_1800000_voltage,
547f384f 1187 },
547f384f
LJ		 1188 .update_bank = 0x03,
1189 .update_reg = 0x83,
1190 .update_mask = 0x04,
1191 .update_val = 0x04,
1192 },
1193 /*
1194 * Regulators with fixed voltage and normal/idle modes
1195 */
1196 [AB8505_LDO_ANA] = {
1197 .desc = {
1198 .name = "LDO-ANA",
8a3b1b87 1199 .ops = &ab8500_regulator_volt_mode_ops,
547f384f 1200 .type = REGULATOR_VOLTAGE,
0b946411 1201 .id = AB8505_LDO_ANA,
547f384f 1202 .owner = THIS_MODULE,
8a3b1b87
LJ		 1203 .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
1204 .volt_table = ldo_vana_voltages,
547f384f 1205 },
547f384f
LJ		 1206 .load_lp_uA = 1000,
1207 .update_bank = 0x04,
1208 .update_reg = 0x06,
1209 .update_mask = 0x0c,
1210 .update_val = 0x04,
1211 .update_val_idle = 0x0c,
1212 .update_val_normal = 0x04,
8a3b1b87
LJ		 1213 .voltage_bank = 0x04,
1214 .voltage_reg = 0x29,
1215 .voltage_mask = 0x7,
547f384f
LJ		 1216 },
1217};
1218
8e6a8d7d
LJ		 1219/* AB9540 regulator information */
1220static struct ab8500_regulator_info
1221 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
1222 /*
1223 * Variable Voltage Regulators
1224 * name, min mV, max mV,
1225 * update bank, reg, mask, enable val
d3193103 1226 * volt bank, reg, mask
8e6a8d7d
LJ		 1227 */
1228 [AB9540_LDO_AUX1] = {
1229 .desc = {
1230 .name = "LDO-AUX1",
1231 .ops = &ab8500_regulator_volt_mode_ops,
1232 .type = REGULATOR_VOLTAGE,
0b946411 1233 .id = AB9540_LDO_AUX1,
8e6a8d7d
LJ		 1234 .owner = THIS_MODULE,
1235 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1236 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1237 },
8e6a8d7d
LJ		 1238 .load_lp_uA = 5000,
1239 .update_bank = 0x04,
1240 .update_reg = 0x09,
1241 .update_mask = 0x03,
1242 .update_val = 0x01,
1243 .update_val_idle = 0x03,
1244 .update_val_normal = 0x01,
1245 .voltage_bank = 0x04,
1246 .voltage_reg = 0x1f,
1247 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1248 },
1249 [AB9540_LDO_AUX2] = {
1250 .desc = {
1251 .name = "LDO-AUX2",
1252 .ops = &ab8500_regulator_volt_mode_ops,
1253 .type = REGULATOR_VOLTAGE,
0b946411 1254 .id = AB9540_LDO_AUX2,
8e6a8d7d
LJ		 1255 .owner = THIS_MODULE,
1256 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1257 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1258 },
8e6a8d7d
LJ		 1259 .load_lp_uA = 5000,
1260 .update_bank = 0x04,
1261 .update_reg = 0x09,
1262 .update_mask = 0x0c,
1263 .update_val = 0x04,
1264 .update_val_idle = 0x0c,
1265 .update_val_normal = 0x04,
1266 .voltage_bank = 0x04,
1267 .voltage_reg = 0x20,
1268 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1269 },
1270 [AB9540_LDO_AUX3] = {
1271 .desc = {
1272 .name = "LDO-AUX3",
1273 .ops = &ab8500_regulator_volt_mode_ops,
1274 .type = REGULATOR_VOLTAGE,
0b946411 1275 .id = AB9540_LDO_AUX3,
8e6a8d7d
LJ		 1276 .owner = THIS_MODULE,
1277 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 1278 .volt_table = ldo_vaux3_voltages,
8e6a8d7d 1279 },
8e6a8d7d
LJ		 1280 .load_lp_uA = 5000,
1281 .update_bank = 0x04,
1282 .update_reg = 0x0a,
1283 .update_mask = 0x03,
1284 .update_val = 0x01,
1285 .update_val_idle = 0x03,
1286 .update_val_normal = 0x01,
1287 .voltage_bank = 0x04,
1288 .voltage_reg = 0x21,
1289 .voltage_mask = 0x07,
8e6a8d7d
LJ		 1290 },
1291 [AB9540_LDO_AUX4] = {
1292 .desc = {
1293 .name = "LDO-AUX4",
1294 .ops = &ab8500_regulator_volt_mode_ops,
1295 .type = REGULATOR_VOLTAGE,
1296 .id = AB9540_LDO_AUX4,
1297 .owner = THIS_MODULE,
1298 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1299 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1300 },
8e6a8d7d
LJ		 1301 .load_lp_uA = 5000,
1302 /* values for Vaux4Regu register */
1303 .update_bank = 0x04,
1304 .update_reg = 0x2e,
1305 .update_mask = 0x03,
1306 .update_val = 0x01,
1307 .update_val_idle = 0x03,
1308 .update_val_normal = 0x01,
1309 /* values for Vaux4SEL register */
1310 .voltage_bank = 0x04,
1311 .voltage_reg = 0x2f,
1312 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1313 },
1314 [AB9540_LDO_INTCORE] = {
1315 .desc = {
1316 .name = "LDO-INTCORE",
1317 .ops = &ab8500_regulator_volt_mode_ops,
1318 .type = REGULATOR_VOLTAGE,
0b946411 1319 .id = AB9540_LDO_INTCORE,
8e6a8d7d
LJ		 1320 .owner = THIS_MODULE,
1321 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1322 .volt_table = ldo_vintcore_voltages,
8e6a8d7d 1323 },
8e6a8d7d
LJ		 1324 .load_lp_uA = 5000,
1325 .update_bank = 0x03,
1326 .update_reg = 0x80,
1327 .update_mask = 0x44,
1328 .update_val = 0x44,
1329 .update_val_idle = 0x44,
1330 .update_val_normal = 0x04,
1331 .voltage_bank = 0x03,
1332 .voltage_reg = 0x80,
1333 .voltage_mask = 0x38,
8e6a8d7d
LJ		 1334 .voltage_shift = 3,
1335 },
6909b452 1336
8e6a8d7d
LJ		 1337 /*
1338 * Fixed Voltage Regulators
1339 * name, fixed mV,
1340 * update bank, reg, mask, enable val
1341 */
1342 [AB9540_LDO_TVOUT] = {
1343 .desc = {
1344 .name = "LDO-TVOUT",
1345 .ops = &ab8500_regulator_mode_ops,
1346 .type = REGULATOR_VOLTAGE,
0b946411 1347 .id = AB9540_LDO_TVOUT,
8e6a8d7d
LJ		 1348 .owner = THIS_MODULE,
1349 .n_voltages = 1,
b080c78a 1350 .volt_table = fixed_2000000_voltage,
a4d68468 1351 .enable_time = 10000,
8e6a8d7d 1352 },
8e6a8d7d
LJ		 1353 .load_lp_uA = 1000,
1354 .update_bank = 0x03,
1355 .update_reg = 0x80,
1356 .update_mask = 0x82,
1357 .update_val = 0x02,
1358 .update_val_idle = 0x82,
1359 .update_val_normal = 0x02,
1360 },
1361 [AB9540_LDO_USB] = {
1362 .desc = {
1363 .name = "LDO-USB",
1364 .ops = &ab8500_regulator_ops,
1365 .type = REGULATOR_VOLTAGE,
1366 .id = AB9540_LDO_USB,
1367 .owner = THIS_MODULE,
1368 .n_voltages = 1,
b080c78a 1369 .volt_table = fixed_3300000_voltage,
8e6a8d7d 1370 },
8e6a8d7d
LJ		 1371 .update_bank = 0x03,
1372 .update_reg = 0x82,
1373 .update_mask = 0x03,
1374 .update_val = 0x01,
1375 .update_val_idle = 0x03,
1376 .update_val_normal = 0x01,
1377 },
1378 [AB9540_LDO_AUDIO] = {
1379 .desc = {
1380 .name = "LDO-AUDIO",
1381 .ops = &ab8500_regulator_ops,
1382 .type = REGULATOR_VOLTAGE,
0b946411 1383 .id = AB9540_LDO_AUDIO,
8e6a8d7d
LJ		 1384 .owner = THIS_MODULE,
1385 .n_voltages = 1,
b080c78a 1386 .volt_table = fixed_2000000_voltage,
8e6a8d7d 1387 },
8e6a8d7d
LJ		 1388 .update_bank = 0x03,
1389 .update_reg = 0x83,
1390 .update_mask = 0x02,
1391 .update_val = 0x02,
1392 },
1393 [AB9540_LDO_ANAMIC1] = {
1394 .desc = {
1395 .name = "LDO-ANAMIC1",
1396 .ops = &ab8500_regulator_ops,
1397 .type = REGULATOR_VOLTAGE,
0b946411 1398 .id = AB9540_LDO_ANAMIC1,
8e6a8d7d
LJ		 1399 .owner = THIS_MODULE,
1400 .n_voltages = 1,
b080c78a 1401 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1402 },
8e6a8d7d
LJ		 1403 .update_bank = 0x03,
1404 .update_reg = 0x83,
1405 .update_mask = 0x08,
1406 .update_val = 0x08,
1407 },
1408 [AB9540_LDO_ANAMIC2] = {
1409 .desc = {
1410 .name = "LDO-ANAMIC2",
1411 .ops = &ab8500_regulator_ops,
1412 .type = REGULATOR_VOLTAGE,
0b946411 1413 .id = AB9540_LDO_ANAMIC2,
8e6a8d7d
LJ		 1414 .owner = THIS_MODULE,
1415 .n_voltages = 1,
b080c78a 1416 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1417 },
8e6a8d7d
LJ		 1418 .update_bank = 0x03,
1419 .update_reg = 0x83,
1420 .update_mask = 0x10,
1421 .update_val = 0x10,
1422 },
1423 [AB9540_LDO_DMIC] = {
1424 .desc = {
1425 .name = "LDO-DMIC",
1426 .ops = &ab8500_regulator_ops,
1427 .type = REGULATOR_VOLTAGE,
0b946411 1428 .id = AB9540_LDO_DMIC,
8e6a8d7d
LJ		 1429 .owner = THIS_MODULE,
1430 .n_voltages = 1,
b080c78a 1431 .volt_table = fixed_1800000_voltage,
8e6a8d7d 1432 },
8e6a8d7d
LJ		 1433 .update_bank = 0x03,
1434 .update_reg = 0x83,
1435 .update_mask = 0x04,
1436 .update_val = 0x04,
1437 },
1438
1439 /*
1440 * Regulators with fixed voltage and normal/idle modes
1441 */
1442 [AB9540_LDO_ANA] = {
1443 .desc = {
1444 .name = "LDO-ANA",
1445 .ops = &ab8500_regulator_mode_ops,
1446 .type = REGULATOR_VOLTAGE,
0b946411 1447 .id = AB9540_LDO_ANA,
8e6a8d7d
LJ		 1448 .owner = THIS_MODULE,
1449 .n_voltages = 1,
b080c78a 1450 .volt_table = fixed_1200000_voltage,
8e6a8d7d 1451 },
8e6a8d7d
LJ		 1452 .load_lp_uA = 1000,
1453 .update_bank = 0x04,
1454 .update_reg = 0x06,
1455 .update_mask = 0x0c,
1456 .update_val = 0x08,
1457 .update_val_idle = 0x0c,
1458 .update_val_normal = 0x08,
1459 },
c789ca20
SI		 1460};
1461
ae0a9a3e
LJ		 1462/* AB8540 regulator information */
1463static struct ab8500_regulator_info
1464 ab8540_regulator_info[AB8540_NUM_REGULATORS] = {
1465 /*
1466 * Variable Voltage Regulators
1467 * name, min mV, max mV,
1468 * update bank, reg, mask, enable val
d3193103 1469 * volt bank, reg, mask
ae0a9a3e
LJ		 1470 */
1471 [AB8540_LDO_AUX1] = {
1472 .desc = {
1473 .name = "LDO-AUX1",
1474 .ops = &ab8500_regulator_volt_mode_ops,
1475 .type = REGULATOR_VOLTAGE,
0b946411 1476 .id = AB8540_LDO_AUX1,
ae0a9a3e
LJ		 1477 .owner = THIS_MODULE,
1478 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1479 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1480 },
1481 .load_lp_uA = 5000,
1482 .update_bank = 0x04,
1483 .update_reg = 0x09,
1484 .update_mask = 0x03,
1485 .update_val = 0x01,
1486 .update_val_idle = 0x03,
1487 .update_val_normal = 0x01,
1488 .voltage_bank = 0x04,
1489 .voltage_reg = 0x1f,
1490 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1491 },
1492 [AB8540_LDO_AUX2] = {
1493 .desc = {
1494 .name = "LDO-AUX2",
1495 .ops = &ab8500_regulator_volt_mode_ops,
1496 .type = REGULATOR_VOLTAGE,
0b946411 1497 .id = AB8540_LDO_AUX2,
ae0a9a3e
LJ		 1498 .owner = THIS_MODULE,
1499 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1500 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1501 },
1502 .load_lp_uA = 5000,
1503 .update_bank = 0x04,
1504 .update_reg = 0x09,
1505 .update_mask = 0x0c,
1506 .update_val = 0x04,
1507 .update_val_idle = 0x0c,
1508 .update_val_normal = 0x04,
1509 .voltage_bank = 0x04,
1510 .voltage_reg = 0x20,
1511 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1512 },
1513 [AB8540_LDO_AUX3] = {
1514 .desc = {
1515 .name = "LDO-AUX3",
d7607baf 1516 .ops = &ab8540_aux3_regulator_volt_mode_ops,
ae0a9a3e 1517 .type = REGULATOR_VOLTAGE,
0b946411 1518 .id = AB8540_LDO_AUX3,
ae0a9a3e
LJ		 1519 .owner = THIS_MODULE,
1520 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
62ab4111 1521 .volt_table = ldo_vaux3_ab8540_voltages,
ae0a9a3e
LJ		 1522 },
1523 .load_lp_uA = 5000,
1524 .update_bank = 0x04,
1525 .update_reg = 0x0a,
1526 .update_mask = 0x03,
1527 .update_val = 0x01,
1528 .update_val_idle = 0x03,
1529 .update_val_normal = 0x01,
1530 .voltage_bank = 0x04,
1531 .voltage_reg = 0x21,
1532 .voltage_mask = 0x07,
d7607baf
LJ		 1533 .expand_register = {
1534 .voltage_limit = 8,
1535 .voltage_bank = 0x04,
1536 .voltage_reg = 0x01,
1537 .voltage_mask = 0x10,
1538 .voltage_shift = 1,
1539 }
ae0a9a3e
LJ		 1540 },
1541 [AB8540_LDO_AUX4] = {
1542 .desc = {
1543 .name = "LDO-AUX4",
1544 .ops = &ab8500_regulator_volt_mode_ops,
1545 .type = REGULATOR_VOLTAGE,
0b946411 1546 .id = AB8540_LDO_AUX4,
ae0a9a3e
LJ		 1547 .owner = THIS_MODULE,
1548 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1549 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1550 },
1551 .load_lp_uA = 5000,
1552 /* values for Vaux4Regu register */
1553 .update_bank = 0x04,
1554 .update_reg = 0x2e,
1555 .update_mask = 0x03,
1556 .update_val = 0x01,
1557 .update_val_idle = 0x03,
1558 .update_val_normal = 0x01,
1559 /* values for Vaux4SEL register */
1560 .voltage_bank = 0x04,
1561 .voltage_reg = 0x2f,
1562 .voltage_mask = 0x0f,
ae0a9a3e 1563 },
684d5ce4
ZH		 1564 [AB8540_LDO_AUX5] = {
1565 .desc = {
1566 .name = "LDO-AUX5",
1567 .ops = &ab8500_regulator_volt_mode_ops,
1568 .type = REGULATOR_VOLTAGE,
1569 .id = AB8540_LDO_AUX5,
1570 .owner = THIS_MODULE,
1571 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
d3193103 1572 .volt_table = ldo_vaux56_ab8540_voltages,
684d5ce4
ZH		 1573 },
1574 .load_lp_uA = 20000,
1575 /* values for Vaux5Regu register */
1576 .update_bank = 0x04,
1577 .update_reg = 0x32,
1578 .update_mask = 0x03,
1579 .update_val = 0x01,
1580 .update_val_idle = 0x03,
1581 .update_val_normal = 0x01,
1582 /* values for Vaux5SEL register */
1583 .voltage_bank = 0x04,
1584 .voltage_reg = 0x33,
1585 .voltage_mask = 0x3f,
684d5ce4
ZH		 1586 },
1587 [AB8540_LDO_AUX6] = {
1588 .desc = {
1589 .name = "LDO-AUX6",
1590 .ops = &ab8500_regulator_volt_mode_ops,
1591 .type = REGULATOR_VOLTAGE,
1592 .id = AB8540_LDO_AUX6,
1593 .owner = THIS_MODULE,
1594 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
d3193103 1595 .volt_table = ldo_vaux56_ab8540_voltages,
684d5ce4
ZH		 1596 },
1597 .load_lp_uA = 20000,
1598 /* values for Vaux6Regu register */
1599 .update_bank = 0x04,
1600 .update_reg = 0x35,
1601 .update_mask = 0x03,
1602 .update_val = 0x01,
1603 .update_val_idle = 0x03,
1604 .update_val_normal = 0x01,
1605 /* values for Vaux6SEL register */
1606 .voltage_bank = 0x04,
1607 .voltage_reg = 0x36,
1608 .voltage_mask = 0x3f,
684d5ce4 1609 },
ae0a9a3e
LJ		 1610 [AB8540_LDO_INTCORE] = {
1611 .desc = {
1612 .name = "LDO-INTCORE",
1613 .ops = &ab8500_regulator_volt_mode_ops,
1614 .type = REGULATOR_VOLTAGE,
0b946411 1615 .id = AB8540_LDO_INTCORE,
ae0a9a3e
LJ		 1616 .owner = THIS_MODULE,
1617 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1618 .volt_table = ldo_vintcore_voltages,
ae0a9a3e
LJ		 1619 },
1620 .load_lp_uA = 5000,
1621 .update_bank = 0x03,
1622 .update_reg = 0x80,
1623 .update_mask = 0x44,
1624 .update_val = 0x44,
1625 .update_val_idle = 0x44,
1626 .update_val_normal = 0x04,
1627 .voltage_bank = 0x03,
1628 .voltage_reg = 0x80,
1629 .voltage_mask = 0x38,
ae0a9a3e
LJ		 1630 .voltage_shift = 3,
1631 },
1632
1633 /*
1634 * Fixed Voltage Regulators
1635 * name, fixed mV,
1636 * update bank, reg, mask, enable val
1637 */
1638 [AB8540_LDO_TVOUT] = {
1639 .desc = {
1640 .name = "LDO-TVOUT",
1641 .ops = &ab8500_regulator_mode_ops,
1642 .type = REGULATOR_VOLTAGE,
0b946411 1643 .id = AB8540_LDO_TVOUT,
ae0a9a3e
LJ		 1644 .owner = THIS_MODULE,
1645 .n_voltages = 1,
aca45e9e 1646 .volt_table = fixed_2000000_voltage,
a4d68468 1647 .enable_time = 10000,
ae0a9a3e 1648 },
ae0a9a3e
LJ		 1649 .load_lp_uA = 1000,
1650 .update_bank = 0x03,
1651 .update_reg = 0x80,
1652 .update_mask = 0x82,
1653 .update_val = 0x02,
1654 .update_val_idle = 0x82,
1655 .update_val_normal = 0x02,
1656 },
1657 [AB8540_LDO_AUDIO] = {
1658 .desc = {
1659 .name = "LDO-AUDIO",
1660 .ops = &ab8500_regulator_ops,
1661 .type = REGULATOR_VOLTAGE,
0b946411 1662 .id = AB8540_LDO_AUDIO,
ae0a9a3e
LJ		 1663 .owner = THIS_MODULE,
1664 .n_voltages = 1,
b080c78a 1665 .volt_table = fixed_2000000_voltage,
ae0a9a3e
LJ		 1666 },
1667 .update_bank = 0x03,
1668 .update_reg = 0x83,
1669 .update_mask = 0x02,
1670 .update_val = 0x02,
1671 },
1672 [AB8540_LDO_ANAMIC1] = {
1673 .desc = {
1674 .name = "LDO-ANAMIC1",
4c84b4dd 1675 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1676 .type = REGULATOR_VOLTAGE,
0b946411 1677 .id = AB8540_LDO_ANAMIC1,
ae0a9a3e
LJ		 1678 .owner = THIS_MODULE,
1679 .n_voltages = 1,
b080c78a 1680 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1681 },
4c84b4dd 1682 .shared_mode = &ab8540_ldo_anamic1_shared,
ae0a9a3e
LJ		 1683 .update_bank = 0x03,
1684 .update_reg = 0x83,
1685 .update_mask = 0x08,
1686 .update_val = 0x08,
4c84b4dd
LJ		 1687 .mode_bank = 0x03,
1688 .mode_reg = 0x83,
1689 .mode_mask = 0x20,
1690 .mode_val_idle = 0x20,
1691 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1692 },
1693 [AB8540_LDO_ANAMIC2] = {
1694 .desc = {
1695 .name = "LDO-ANAMIC2",
4c84b4dd 1696 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1697 .type = REGULATOR_VOLTAGE,
0b946411 1698 .id = AB8540_LDO_ANAMIC2,
ae0a9a3e
LJ		 1699 .owner = THIS_MODULE,
1700 .n_voltages = 1,
b080c78a 1701 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1702 },
4c84b4dd 1703 .shared_mode = &ab8540_ldo_anamic2_shared,
ae0a9a3e
LJ		 1704 .update_bank = 0x03,
1705 .update_reg = 0x83,
1706 .update_mask = 0x10,
1707 .update_val = 0x10,
4c84b4dd
LJ		 1708 .mode_bank = 0x03,
1709 .mode_reg = 0x83,
1710 .mode_mask = 0x20,
1711 .mode_val_idle = 0x20,
1712 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1713 },
1714 [AB8540_LDO_DMIC] = {
1715 .desc = {
1716 .name = "LDO-DMIC",
4c84b4dd 1717 .ops = &ab8500_regulator_volt_mode_ops,
ae0a9a3e 1718 .type = REGULATOR_VOLTAGE,
0b946411 1719 .id = AB8540_LDO_DMIC,
ae0a9a3e 1720 .owner = THIS_MODULE,
4c84b4dd 1721 .n_voltages = ARRAY_SIZE(ldo_vdmic_voltages),
d3193103 1722 .volt_table = ldo_vdmic_voltages,
ae0a9a3e 1723 },
4c84b4dd 1724 .load_lp_uA = 1000,
ae0a9a3e
LJ		 1725 .update_bank = 0x03,
1726 .update_reg = 0x83,
1727 .update_mask = 0x04,
1728 .update_val = 0x04,
4c84b4dd
LJ		 1729 .voltage_bank = 0x03,
1730 .voltage_reg = 0x83,
1731 .voltage_mask = 0xc0,
ae0a9a3e
LJ		 1732 },
1733
1734 /*
1735 * Regulators with fixed voltage and normal/idle modes
1736 */
1737 [AB8540_LDO_ANA] = {
1738 .desc = {
1739 .name = "LDO-ANA",
1740 .ops = &ab8500_regulator_mode_ops,
1741 .type = REGULATOR_VOLTAGE,
0b946411 1742 .id = AB8540_LDO_ANA,
ae0a9a3e
LJ		 1743 .owner = THIS_MODULE,
1744 .n_voltages = 1,
b080c78a 1745 .volt_table = fixed_1200000_voltage,
ae0a9a3e
LJ		 1746 },
1747 .load_lp_uA = 1000,
1748 .update_bank = 0x04,
1749 .update_reg = 0x06,
1750 .update_mask = 0x0c,
1751 .update_val = 0x04,
1752 .update_val_idle = 0x0c,
1753 .update_val_normal = 0x04,
1754 },
1755 [AB8540_LDO_SDIO] = {
1756 .desc = {
1757 .name = "LDO-SDIO",
1758 .ops = &ab8500_regulator_volt_mode_ops,
1759 .type = REGULATOR_VOLTAGE,
1760 .id = AB8540_LDO_SDIO,
1761 .owner = THIS_MODULE,
62ab4111
LJ		 1762 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages),
1763 .volt_table = ldo_sdio_voltages,
ae0a9a3e 1764 },
ae0a9a3e
LJ		 1765 .load_lp_uA = 5000,
1766 .update_bank = 0x03,
1767 .update_reg = 0x88,
1768 .update_mask = 0x30,
1769 .update_val = 0x10,
1770 .update_val_idle = 0x30,
1771 .update_val_normal = 0x10,
1772 .voltage_bank = 0x03,
1773 .voltage_reg = 0x88,
1774 .voltage_mask = 0x07,
ae0a9a3e
LJ		 1775 },
1776};
1777
3fe52289
LJ		 1778static struct ab8500_shared_mode ldo_anamic1_shared = {
1779 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2],
1780};
1781
1782static struct ab8500_shared_mode ldo_anamic2_shared = {
1783 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1],
1784};
1785
4c84b4dd
LJ		 1786static struct ab8500_shared_mode ab8540_ldo_anamic1_shared = {
1787 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC2],
1788};
1789
1790static struct ab8500_shared_mode ab8540_ldo_anamic2_shared = {
1791 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC1],
1792};
1793
79568b94
BJ		 1794struct ab8500_reg_init {
1795 u8 bank;
1796 u8 addr;
1797 u8 mask;
1798};
1799
1800#define REG_INIT(_id, _bank, _addr, _mask) \
1801 [_id] = { \
1802 .bank = _bank, \
1803 .addr = _addr, \
1804 .mask = _mask, \
1805 }
1806
8e6a8d7d 1807/* AB8500 register init */
79568b94
BJ		 1808static struct ab8500_reg_init ab8500_reg_init[] = {
1809 /*
33bc8f46 1810 * 0x30, VanaRequestCtrl
79568b94
BJ		 1811 * 0xc0, VextSupply1RequestCtrl
1812 */
43a5911b 1813 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
79568b94
BJ		 1814 /*
1815 * 0x03, VextSupply2RequestCtrl
1816 * 0x0c, VextSupply3RequestCtrl
1817 * 0x30, Vaux1RequestCtrl
1818 * 0xc0, Vaux2RequestCtrl
1819 */
1820 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1821 /*
1822 * 0x03, Vaux3RequestCtrl
1823 * 0x04, SwHPReq
1824 */
1825 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1826 /*
1827 * 0x08, VanaSysClkReq1HPValid
1828 * 0x20, Vaux1SysClkReq1HPValid
1829 * 0x40, Vaux2SysClkReq1HPValid
1830 * 0x80, Vaux3SysClkReq1HPValid
1831 */
43a5911b 1832 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
79568b94
BJ		 1833 /*
1834 * 0x10, VextSupply1SysClkReq1HPValid
1835 * 0x20, VextSupply2SysClkReq1HPValid
1836 * 0x40, VextSupply3SysClkReq1HPValid
1837 */
43a5911b 1838 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
79568b94
BJ		 1839 /*
1840 * 0x08, VanaHwHPReq1Valid
1841 * 0x20, Vaux1HwHPReq1Valid
1842 * 0x40, Vaux2HwHPReq1Valid
1843 * 0x80, Vaux3HwHPReq1Valid
1844 */
43a5911b 1845 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
79568b94
BJ		 1846 /*
1847 * 0x01, VextSupply1HwHPReq1Valid
1848 * 0x02, VextSupply2HwHPReq1Valid
1849 * 0x04, VextSupply3HwHPReq1Valid
1850 */
43a5911b 1851 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
79568b94
BJ		 1852 /*
1853 * 0x08, VanaHwHPReq2Valid
1854 * 0x20, Vaux1HwHPReq2Valid
1855 * 0x40, Vaux2HwHPReq2Valid
1856 * 0x80, Vaux3HwHPReq2Valid
1857 */
43a5911b 1858 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
79568b94
BJ		 1859 /*
1860 * 0x01, VextSupply1HwHPReq2Valid
1861 * 0x02, VextSupply2HwHPReq2Valid
1862 * 0x04, VextSupply3HwHPReq2Valid
1863 */
43a5911b 1864 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
79568b94
BJ		 1865 /*
1866 * 0x20, VanaSwHPReqValid
1867 * 0x80, Vaux1SwHPReqValid
1868 */
43a5911b 1869 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
79568b94
BJ		 1870 /*
1871 * 0x01, Vaux2SwHPReqValid
1872 * 0x02, Vaux3SwHPReqValid
1873 * 0x04, VextSupply1SwHPReqValid
1874 * 0x08, VextSupply2SwHPReqValid
1875 * 0x10, VextSupply3SwHPReqValid
1876 */
43a5911b 1877 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
79568b94
BJ		 1878 /*
1879 * 0x02, SysClkReq2Valid1
43a5911b
LJ		 1880 * 0x04, SysClkReq3Valid1
1881 * 0x08, SysClkReq4Valid1
1882 * 0x10, SysClkReq5Valid1
1883 * 0x20, SysClkReq6Valid1
1884 * 0x40, SysClkReq7Valid1
79568b94
BJ		 1885 * 0x80, SysClkReq8Valid1
1886 */
1887 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1888 /*
1889 * 0x02, SysClkReq2Valid2
43a5911b
LJ		 1890 * 0x04, SysClkReq3Valid2
1891 * 0x08, SysClkReq4Valid2
1892 * 0x10, SysClkReq5Valid2
1893 * 0x20, SysClkReq6Valid2
1894 * 0x40, SysClkReq7Valid2
79568b94
BJ		 1895 * 0x80, SysClkReq8Valid2
1896 */
1897 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1898 /*
1899 * 0x02, VTVoutEna
1900 * 0x04, Vintcore12Ena
1901 * 0x38, Vintcore12Sel
1902 * 0x40, Vintcore12LP
1903 * 0x80, VTVoutLP
1904 */
1905 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1906 /*
1907 * 0x02, VaudioEna
1908 * 0x04, VdmicEna
1909 * 0x08, Vamic1Ena
1910 * 0x10, Vamic2Ena
1911 */
1912 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1913 /*
1914 * 0x01, Vamic1_dzout
1915 * 0x02, Vamic2_dzout
1916 */
1917 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
d79df329 1918 /*
43a5911b 1919 * 0x03, VpllRegu (NOTE! PRCMU register bits)
33bc8f46 1920 * 0x0c, VanaRegu
79568b94
BJ		 1921 */
1922 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1923 /*
1924 * 0x01, VrefDDREna
1925 * 0x02, VrefDDRSleepMode
1926 */
1927 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1928 /*
1929 * 0x03, VextSupply1Regu
1930 * 0x0c, VextSupply2Regu
1931 * 0x30, VextSupply3Regu
1932 * 0x40, ExtSupply2Bypass
1933 * 0x80, ExtSupply3Bypass
1934 */
1935 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1936 /*
1937 * 0x03, Vaux1Regu
1938 * 0x0c, Vaux2Regu
1939 */
1940 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1941 /*
1942 * 0x03, Vaux3Regu
1943 */
43a5911b 1944 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
79568b94
BJ		 1945 /*
1946 * 0x0f, Vaux1Sel
1947 */
1948 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1949 /*
1950 * 0x0f, Vaux2Sel
1951 */
1952 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1953 /*
1954 * 0x07, Vaux3Sel
1955 */
43a5911b 1956 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
79568b94
BJ		 1957 /*
1958 * 0x01, VextSupply12LP
1959 */
1960 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1961 /*
1962 * 0x04, Vaux1Disch
1963 * 0x08, Vaux2Disch
1964 * 0x10, Vaux3Disch
1965 * 0x20, Vintcore12Disch
1966 * 0x40, VTVoutDisch
1967 * 0x80, VaudioDisch
1968 */
43a5911b 1969 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
79568b94
BJ		 1970 /*
1971 * 0x02, VanaDisch
1972 * 0x04, VdmicPullDownEna
1973 * 0x10, VdmicDisch
1974 */
43a5911b 1975 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
79568b94
BJ		 1976};
1977
547f384f
LJ		 1978/* AB8505 register init */
1979static struct ab8500_reg_init ab8505_reg_init[] = {
1980 /*
1981 * 0x03, VarmRequestCtrl
1982 * 0x0c, VsmpsCRequestCtrl
1983 * 0x30, VsmpsARequestCtrl
1984 * 0xc0, VsmpsBRequestCtrl
1985 */
1986 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1987 /*
1988 * 0x03, VsafeRequestCtrl
1989 * 0x0c, VpllRequestCtrl
1990 * 0x30, VanaRequestCtrl
1991 */
1992 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
1993 /*
1994 * 0x30, Vaux1RequestCtrl
1995 * 0xc0, Vaux2RequestCtrl
1996 */
1997 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
1998 /*
1999 * 0x03, Vaux3RequestCtrl
2000 * 0x04, SwHPReq
2001 */
2002 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2003 /*
2004 * 0x01, VsmpsASysClkReq1HPValid
2005 * 0x02, VsmpsBSysClkReq1HPValid
2006 * 0x04, VsafeSysClkReq1HPValid
2007 * 0x08, VanaSysClkReq1HPValid
2008 * 0x10, VpllSysClkReq1HPValid
2009 * 0x20, Vaux1SysClkReq1HPValid
2010 * 0x40, Vaux2SysClkReq1HPValid
2011 * 0x80, Vaux3SysClkReq1HPValid
2012 */
2013 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2014 /*
2015 * 0x01, VsmpsCSysClkReq1HPValid
2016 * 0x02, VarmSysClkReq1HPValid
2017 * 0x04, VbbSysClkReq1HPValid
2018 * 0x08, VsmpsMSysClkReq1HPValid
2019 */
2020 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
2021 /*
2022 * 0x01, VsmpsAHwHPReq1Valid
2023 * 0x02, VsmpsBHwHPReq1Valid
2024 * 0x04, VsafeHwHPReq1Valid
2025 * 0x08, VanaHwHPReq1Valid
2026 * 0x10, VpllHwHPReq1Valid
2027 * 0x20, Vaux1HwHPReq1Valid
2028 * 0x40, Vaux2HwHPReq1Valid
2029 * 0x80, Vaux3HwHPReq1Valid
2030 */
2031 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2032 /*
2033 * 0x08, VsmpsMHwHPReq1Valid
2034 */
2035 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
2036 /*
2037 * 0x01, VsmpsAHwHPReq2Valid
2038 * 0x02, VsmpsBHwHPReq2Valid
2039 * 0x04, VsafeHwHPReq2Valid
2040 * 0x08, VanaHwHPReq2Valid
2041 * 0x10, VpllHwHPReq2Valid
2042 * 0x20, Vaux1HwHPReq2Valid
2043 * 0x40, Vaux2HwHPReq2Valid
2044 * 0x80, Vaux3HwHPReq2Valid
2045 */
2046 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2047 /*
2048 * 0x08, VsmpsMHwHPReq2Valid
2049 */
2050 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
2051 /*
2052 * 0x01, VsmpsCSwHPReqValid
2053 * 0x02, VarmSwHPReqValid
2054 * 0x04, VsmpsASwHPReqValid
2055 * 0x08, VsmpsBSwHPReqValid
2056 * 0x10, VsafeSwHPReqValid
2057 * 0x20, VanaSwHPReqValid
2058 * 0x40, VpllSwHPReqValid
2059 * 0x80, Vaux1SwHPReqValid
2060 */
2061 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2062 /*
2063 * 0x01, Vaux2SwHPReqValid
2064 * 0x02, Vaux3SwHPReqValid
2065 * 0x20, VsmpsMSwHPReqValid
2066 */
2067 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
2068 /*
2069 * 0x02, SysClkReq2Valid1
2070 * 0x04, SysClkReq3Valid1
2071 * 0x08, SysClkReq4Valid1
2072 */
2073 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
2074 /*
2075 * 0x02, SysClkReq2Valid2
2076 * 0x04, SysClkReq3Valid2
2077 * 0x08, SysClkReq4Valid2
2078 */
2079 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
2080 /*
2081 * 0x01, Vaux4SwHPReqValid
2082 * 0x02, Vaux4HwHPReq2Valid
2083 * 0x04, Vaux4HwHPReq1Valid
2084 * 0x08, Vaux4SysClkReq1HPValid
2085 */
2086 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2087 /*
2088 * 0x02, VadcEna
2089 * 0x04, VintCore12Ena
2090 * 0x38, VintCore12Sel
2091 * 0x40, VintCore12LP
2092 * 0x80, VadcLP
2093 */
2094 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
2095 /*
2096 * 0x02, VaudioEna
2097 * 0x04, VdmicEna
2098 * 0x08, Vamic1Ena
2099 * 0x10, Vamic2Ena
2100 */
2101 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2102 /*
2103 * 0x01, Vamic1_dzout
2104 * 0x02, Vamic2_dzout
2105 */
2106 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2107 /*
2108 * 0x03, VsmpsARegu
2109 * 0x0c, VsmpsASelCtrl
2110 * 0x10, VsmpsAAutoMode
2111 * 0x20, VsmpsAPWMMode
2112 */
2113 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
2114 /*
2115 * 0x03, VsmpsBRegu
2116 * 0x0c, VsmpsBSelCtrl
2117 * 0x10, VsmpsBAutoMode
2118 * 0x20, VsmpsBPWMMode
2119 */
2120 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
2121 /*
2122 * 0x03, VsafeRegu
2123 * 0x0c, VsafeSelCtrl
2124 * 0x10, VsafeAutoMode
2125 * 0x20, VsafePWMMode
2126 */
2127 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
2128 /*
2129 * 0x03, VpllRegu (NOTE! PRCMU register bits)
2130 * 0x0c, VanaRegu
2131 */
2132 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2133 /*
2134 * 0x03, VextSupply1Regu
2135 * 0x0c, VextSupply2Regu
2136 * 0x30, VextSupply3Regu
2137 * 0x40, ExtSupply2Bypass
2138 * 0x80, ExtSupply3Bypass
2139 */
2140 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2141 /*
2142 * 0x03, Vaux1Regu
2143 * 0x0c, Vaux2Regu
2144 */
2145 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
2146 /*
2147 * 0x0f, Vaux3Regu
2148 */
2149 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2150 /*
2151 * 0x3f, VsmpsASel1
2152 */
2153 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
2154 /*
2155 * 0x3f, VsmpsASel2
2156 */
2157 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
2158 /*
2159 * 0x3f, VsmpsASel3
2160 */
2161 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
2162 /*
2163 * 0x3f, VsmpsBSel1
2164 */
2165 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
2166 /*
2167 * 0x3f, VsmpsBSel2
2168 */
2169 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
2170 /*
2171 * 0x3f, VsmpsBSel3
2172 */
2173 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
2174 /*
2175 * 0x7f, VsafeSel1
2176 */
2177 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
2178 /*
2179 * 0x3f, VsafeSel2
2180 */
2181 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
2182 /*
2183 * 0x3f, VsafeSel3
2184 */
2185 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
2186 /*
2187 * 0x0f, Vaux1Sel
2188 */
2189 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
2190 /*
2191 * 0x0f, Vaux2Sel
2192 */
2193 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
2194 /*
2195 * 0x07, Vaux3Sel
2196 * 0x30, VRF1Sel
2197 */
2198 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2199 /*
2200 * 0x03, Vaux4RequestCtrl
2201 */
2202 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2203 /*
2204 * 0x03, Vaux4Regu
2205 */
2206 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
2207 /*
2208 * 0x0f, Vaux4Sel
2209 */
2210 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
2211 /*
2212 * 0x04, Vaux1Disch
2213 * 0x08, Vaux2Disch
2214 * 0x10, Vaux3Disch
2215 * 0x20, Vintcore12Disch
2216 * 0x40, VTVoutDisch
2217 * 0x80, VaudioDisch
2218 */
2219 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
2220 /*
2221 * 0x02, VanaDisch
2222 * 0x04, VdmicPullDownEna
2223 * 0x10, VdmicDisch
2224 */
2225 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
2226 /*
2227 * 0x01, Vaux4Disch
2228 */
2229 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2230 /*
2231 * 0x07, Vaux5Sel
2232 * 0x08, Vaux5LP
2233 * 0x10, Vaux5Ena
2234 * 0x20, Vaux5Disch
2235 * 0x40, Vaux5DisSfst
2236 * 0x80, Vaux5DisPulld
2237 */
2238 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
2239 /*
2240 * 0x07, Vaux6Sel
2241 * 0x08, Vaux6LP
2242 * 0x10, Vaux6Ena
2243 * 0x80, Vaux6DisPulld
2244 */
2245 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
2246};
2247
8e6a8d7d
LJ		 2248/* AB9540 register init */
2249static struct ab8500_reg_init ab9540_reg_init[] = {
2250 /*
2251 * 0x03, VarmRequestCtrl
2252 * 0x0c, VapeRequestCtrl
2253 * 0x30, Vsmps1RequestCtrl
2254 * 0xc0, Vsmps2RequestCtrl
2255 */
2256 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2257 /*
2258 * 0x03, Vsmps3RequestCtrl
2259 * 0x0c, VpllRequestCtrl
2260 * 0x30, VanaRequestCtrl
2261 * 0xc0, VextSupply1RequestCtrl
2262 */
2263 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2264 /*
2265 * 0x03, VextSupply2RequestCtrl
2266 * 0x0c, VextSupply3RequestCtrl
2267 * 0x30, Vaux1RequestCtrl
2268 * 0xc0, Vaux2RequestCtrl
2269 */
2270 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2271 /*
2272 * 0x03, Vaux3RequestCtrl
2273 * 0x04, SwHPReq
2274 */
2275 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2276 /*
2277 * 0x01, Vsmps1SysClkReq1HPValid
2278 * 0x02, Vsmps2SysClkReq1HPValid
2279 * 0x04, Vsmps3SysClkReq1HPValid
2280 * 0x08, VanaSysClkReq1HPValid
2281 * 0x10, VpllSysClkReq1HPValid
2282 * 0x20, Vaux1SysClkReq1HPValid
2283 * 0x40, Vaux2SysClkReq1HPValid
2284 * 0x80, Vaux3SysClkReq1HPValid
2285 */
2286 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2287 /*
2288 * 0x01, VapeSysClkReq1HPValid
2289 * 0x02, VarmSysClkReq1HPValid
2290 * 0x04, VbbSysClkReq1HPValid
2291 * 0x08, VmodSysClkReq1HPValid
2292 * 0x10, VextSupply1SysClkReq1HPValid
2293 * 0x20, VextSupply2SysClkReq1HPValid
2294 * 0x40, VextSupply3SysClkReq1HPValid
2295 */
2296 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
2297 /*
2298 * 0x01, Vsmps1HwHPReq1Valid
2299 * 0x02, Vsmps2HwHPReq1Valid
2300 * 0x04, Vsmps3HwHPReq1Valid
2301 * 0x08, VanaHwHPReq1Valid
2302 * 0x10, VpllHwHPReq1Valid
2303 * 0x20, Vaux1HwHPReq1Valid
2304 * 0x40, Vaux2HwHPReq1Valid
2305 * 0x80, Vaux3HwHPReq1Valid
2306 */
2307 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2308 /*
2309 * 0x01, VextSupply1HwHPReq1Valid
2310 * 0x02, VextSupply2HwHPReq1Valid
2311 * 0x04, VextSupply3HwHPReq1Valid
2312 * 0x08, VmodHwHPReq1Valid
2313 */
2314 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
2315 /*
2316 * 0x01, Vsmps1HwHPReq2Valid
2317 * 0x02, Vsmps2HwHPReq2Valid
2318 * 0x03, Vsmps3HwHPReq2Valid
2319 * 0x08, VanaHwHPReq2Valid
2320 * 0x10, VpllHwHPReq2Valid
2321 * 0x20, Vaux1HwHPReq2Valid
2322 * 0x40, Vaux2HwHPReq2Valid
2323 * 0x80, Vaux3HwHPReq2Valid
2324 */
2325 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2326 /*
2327 * 0x01, VextSupply1HwHPReq2Valid
2328 * 0x02, VextSupply2HwHPReq2Valid
2329 * 0x04, VextSupply3HwHPReq2Valid
2330 * 0x08, VmodHwHPReq2Valid
2331 */
2332 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
2333 /*
2334 * 0x01, VapeSwHPReqValid
2335 * 0x02, VarmSwHPReqValid
2336 * 0x04, Vsmps1SwHPReqValid
2337 * 0x08, Vsmps2SwHPReqValid
2338 * 0x10, Vsmps3SwHPReqValid
2339 * 0x20, VanaSwHPReqValid
2340 * 0x40, VpllSwHPReqValid
2341 * 0x80, Vaux1SwHPReqValid
2342 */
2343 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2344 /*
2345 * 0x01, Vaux2SwHPReqValid
2346 * 0x02, Vaux3SwHPReqValid
2347 * 0x04, VextSupply1SwHPReqValid
2348 * 0x08, VextSupply2SwHPReqValid
2349 * 0x10, VextSupply3SwHPReqValid
2350 * 0x20, VmodSwHPReqValid
2351 */
2352 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
2353 /*
2354 * 0x02, SysClkReq2Valid1
2355 * ...
2356 * 0x80, SysClkReq8Valid1
2357 */
2358 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
2359 /*
2360 * 0x02, SysClkReq2Valid2
2361 * ...
2362 * 0x80, SysClkReq8Valid2
2363 */
2364 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
2365 /*
2366 * 0x01, Vaux4SwHPReqValid
2367 * 0x02, Vaux4HwHPReq2Valid
2368 * 0x04, Vaux4HwHPReq1Valid
2369 * 0x08, Vaux4SysClkReq1HPValid
2370 */
2371 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2372 /*
2373 * 0x02, VTVoutEna
2374 * 0x04, Vintcore12Ena
2375 * 0x38, Vintcore12Sel
2376 * 0x40, Vintcore12LP
2377 * 0x80, VTVoutLP
2378 */
2379 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
2380 /*
2381 * 0x02, VaudioEna
2382 * 0x04, VdmicEna
2383 * 0x08, Vamic1Ena
2384 * 0x10, Vamic2Ena
2385 */
2386 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2387 /*
2388 * 0x01, Vamic1_dzout
2389 * 0x02, Vamic2_dzout
2390 */
2391 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2392 /*
2393 * 0x03, Vsmps1Regu
2394 * 0x0c, Vsmps1SelCtrl
2395 * 0x10, Vsmps1AutoMode
2396 * 0x20, Vsmps1PWMMode
2397 */
2398 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2399 /*
2400 * 0x03, Vsmps2Regu
2401 * 0x0c, Vsmps2SelCtrl
2402 * 0x10, Vsmps2AutoMode
2403 * 0x20, Vsmps2PWMMode
2404 */
2405 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2406 /*
2407 * 0x03, Vsmps3Regu
2408 * 0x0c, Vsmps3SelCtrl
2409 * NOTE! PRCMU register
2410 */
2411 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2412 /*
2413 * 0x03, VpllRegu
2414 * 0x0c, VanaRegu
2415 */
2416 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2417 /*
2418 * 0x03, VextSupply1Regu
2419 * 0x0c, VextSupply2Regu
2420 * 0x30, VextSupply3Regu
2421 * 0x40, ExtSupply2Bypass
2422 * 0x80, ExtSupply3Bypass
2423 */
2424 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2425 /*
2426 * 0x03, Vaux1Regu
2427 * 0x0c, Vaux2Regu
2428 */
2429 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
2430 /*
2431 * 0x0c, Vrf1Regu
2432 * 0x03, Vaux3Regu
2433 */
2434 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2435 /*
2436 * 0x3f, Vsmps1Sel1
2437 */
2438 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2439 /*
2440 * 0x3f, Vsmps1Sel2
2441 */
2442 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2443 /*
2444 * 0x3f, Vsmps1Sel3
2445 */
2446 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2447 /*
2448 * 0x3f, Vsmps2Sel1
2449 */
2450 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2451 /*
2452 * 0x3f, Vsmps2Sel2
2453 */
2454 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2455 /*
2456 * 0x3f, Vsmps2Sel3
2457 */
2458 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2459 /*
2460 * 0x7f, Vsmps3Sel1
2461 * NOTE! PRCMU register
2462 */
2463 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2464 /*
2465 * 0x7f, Vsmps3Sel2
2466 * NOTE! PRCMU register
2467 */
2468 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2469 /*
2470 * 0x0f, Vaux1Sel
2471 */
2472 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2473 /*
2474 * 0x0f, Vaux2Sel
2475 */
2476 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
2477 /*
2478 * 0x07, Vaux3Sel
2479 * 0x30, Vrf1Sel
2480 */
2481 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2482 /*
2483 * 0x01, VextSupply12LP
2484 */
2485 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2486 /*
2487 * 0x03, Vaux4RequestCtrl
2488 */
2489 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2490 /*
2491 * 0x03, Vaux4Regu
2492 */
2493 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
2494 /*
2495 * 0x08, Vaux4Sel
2496 */
2497 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2498 /*
2499 * 0x01, VpllDisch
2500 * 0x02, Vrf1Disch
2501 * 0x04, Vaux1Disch
2502 * 0x08, Vaux2Disch
2503 * 0x10, Vaux3Disch
2504 * 0x20, Vintcore12Disch
2505 * 0x40, VTVoutDisch
2506 * 0x80, VaudioDisch
2507 */
2508 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2509 /*
2510 * 0x01, VsimDisch
2511 * 0x02, VanaDisch
2512 * 0x04, VdmicPullDownEna
2513 * 0x08, VpllPullDownEna
2514 * 0x10, VdmicDisch
2515 */
2516 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
2517 /*
2518 * 0x01, Vaux4Disch
2519 */
2520 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2521};
2522
ae0a9a3e
LJ		 2523/* AB8540 register init */
2524static struct ab8500_reg_init ab8540_reg_init[] = {
2525 /*
2526 * 0x01, VSimSycClkReq1Valid
2527 * 0x02, VSimSycClkReq2Valid
2528 * 0x04, VSimSycClkReq3Valid
2529 * 0x08, VSimSycClkReq4Valid
2530 * 0x10, VSimSycClkReq5Valid
2531 * 0x20, VSimSycClkReq6Valid
2532 * 0x40, VSimSycClkReq7Valid
2533 * 0x80, VSimSycClkReq8Valid
2534 */
2535 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff),
2536 /*
2537 * 0x03, VarmRequestCtrl
2538 * 0x0c, VapeRequestCtrl
2539 * 0x30, Vsmps1RequestCtrl
2540 * 0xc0, Vsmps2RequestCtrl
2541 */
2542 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2543 /*
2544 * 0x03, Vsmps3RequestCtrl
2545 * 0x0c, VpllRequestCtrl
2546 * 0x30, VanaRequestCtrl
2547 * 0xc0, VextSupply1RequestCtrl
2548 */
2549 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2550 /*
2551 * 0x03, VextSupply2RequestCtrl
2552 * 0x0c, VextSupply3RequestCtrl
2553 * 0x30, Vaux1RequestCtrl
2554 * 0xc0, Vaux2RequestCtrl
2555 */
2556 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2557 /*
2558 * 0x03, Vaux3RequestCtrl
2559 * 0x04, SwHPReq
2560 */
2561 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2562 /*
2563 * 0x01, Vsmps1SysClkReq1HPValid
2564 * 0x02, Vsmps2SysClkReq1HPValid
2565 * 0x04, Vsmps3SysClkReq1HPValid
2566 * 0x08, VanaSysClkReq1HPValid
2567 * 0x10, VpllSysClkReq1HPValid
2568 * 0x20, Vaux1SysClkReq1HPValid
2569 * 0x40, Vaux2SysClkReq1HPValid
2570 * 0x80, Vaux3SysClkReq1HPValid
2571 */
2572 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2573 /*
2574 * 0x01, VapeSysClkReq1HPValid
2575 * 0x02, VarmSysClkReq1HPValid
2576 * 0x04, VbbSysClkReq1HPValid
2577 * 0x10, VextSupply1SysClkReq1HPValid
2578 * 0x20, VextSupply2SysClkReq1HPValid
2579 * 0x40, VextSupply3SysClkReq1HPValid
2580 */
2581 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77),
2582 /*
2583 * 0x01, Vsmps1HwHPReq1Valid
2584 * 0x02, Vsmps2HwHPReq1Valid
2585 * 0x04, Vsmps3HwHPReq1Valid
2586 * 0x08, VanaHwHPReq1Valid
2587 * 0x10, VpllHwHPReq1Valid
2588 * 0x20, Vaux1HwHPReq1Valid
2589 * 0x40, Vaux2HwHPReq1Valid
2590 * 0x80, Vaux3HwHPReq1Valid
2591 */
2592 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2593 /*
2594 * 0x01, VextSupply1HwHPReq1Valid
2595 * 0x02, VextSupply2HwHPReq1Valid
2596 * 0x04, VextSupply3HwHPReq1Valid
2597 */
2598 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
2599 /*
2600 * 0x01, Vsmps1HwHPReq2Valid
2601 * 0x02, Vsmps2HwHPReq2Valid
2602 * 0x03, Vsmps3HwHPReq2Valid
2603 * 0x08, VanaHwHPReq2Valid
2604 * 0x10, VpllHwHPReq2Valid
2605 * 0x20, Vaux1HwHPReq2Valid
2606 * 0x40, Vaux2HwHPReq2Valid
2607 * 0x80, Vaux3HwHPReq2Valid
2608 */
2609 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2610 /*
2611 * 0x01, VextSupply1HwHPReq2Valid
2612 * 0x02, VextSupply2HwHPReq2Valid
2613 * 0x04, VextSupply3HwHPReq2Valid
2614 */
2615 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
2616 /*
2617 * 0x01, VapeSwHPReqValid
2618 * 0x02, VarmSwHPReqValid
2619 * 0x04, Vsmps1SwHPReqValid
2620 * 0x08, Vsmps2SwHPReqValid
2621 * 0x10, Vsmps3SwHPReqValid
2622 * 0x20, VanaSwHPReqValid
2623 * 0x40, VpllSwHPReqValid
2624 * 0x80, Vaux1SwHPReqValid
2625 */
2626 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2627 /*
2628 * 0x01, Vaux2SwHPReqValid
2629 * 0x02, Vaux3SwHPReqValid
2630 * 0x04, VextSupply1SwHPReqValid
2631 * 0x08, VextSupply2SwHPReqValid
2632 * 0x10, VextSupply3SwHPReqValid
2633 */
2634 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
2635 /*
2636 * 0x02, SysClkReq2Valid1
2637 * ...
2638 * 0x80, SysClkReq8Valid1
2639 */
2640 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff),
2641 /*
2642 * 0x02, SysClkReq2Valid2
2643 * ...
2644 * 0x80, SysClkReq8Valid2
2645 */
2646 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff),
2647 /*
2648 * 0x01, Vaux4SwHPReqValid
2649 * 0x02, Vaux4HwHPReq2Valid
2650 * 0x04, Vaux4HwHPReq1Valid
2651 * 0x08, Vaux4SysClkReq1HPValid
2652 */
2653 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2654 /*
2655 * 0x01, Vaux5SwHPReqValid
2656 * 0x02, Vaux5HwHPReq2Valid
2657 * 0x04, Vaux5HwHPReq1Valid
2658 * 0x08, Vaux5SysClkReq1HPValid
2659 */
2660 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f),
2661 /*
2662 * 0x01, Vaux6SwHPReqValid
2663 * 0x02, Vaux6HwHPReq2Valid
2664 * 0x04, Vaux6HwHPReq1Valid
2665 * 0x08, Vaux6SysClkReq1HPValid
2666 */
2667 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f),
2668 /*
2669 * 0x01, VclkbSwHPReqValid
2670 * 0x02, VclkbHwHPReq2Valid
2671 * 0x04, VclkbHwHPReq1Valid
2672 * 0x08, VclkbSysClkReq1HPValid
2673 */
2674 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f),
2675 /*
2676 * 0x01, Vrf1SwHPReqValid
2677 * 0x02, Vrf1HwHPReq2Valid
2678 * 0x04, Vrf1HwHPReq1Valid
2679 * 0x08, Vrf1SysClkReq1HPValid
2680 */
2681 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f),
2682 /*
2683 * 0x02, VTVoutEna
2684 * 0x04, Vintcore12Ena
2685 * 0x38, Vintcore12Sel
2686 * 0x40, Vintcore12LP
2687 * 0x80, VTVoutLP
2688 */
2689 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe),
2690 /*
2691 * 0x02, VaudioEna
2692 * 0x04, VdmicEna
2693 * 0x08, Vamic1Ena
2694 * 0x10, Vamic2Ena
2695 * 0x20, Vamic12LP
2696 * 0xC0, VdmicSel
2697 */
2698 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe),
2699 /*
2700 * 0x01, Vamic1_dzout
2701 * 0x02, Vamic2_dzout
2702 */
2703 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2704 /*
2705 * 0x07, VHSICSel
2706 * 0x08, VHSICOffState
2707 * 0x10, VHSIEna
2708 * 0x20, VHSICLP
2709 */
2710 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f),
2711 /*
2712 * 0x07, VSDIOSel
2713 * 0x08, VSDIOOffState
2714 * 0x10, VSDIOEna
2715 * 0x20, VSDIOLP
2716 */
2717 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f),
2718 /*
2719 * 0x03, Vsmps1Regu
2720 * 0x0c, Vsmps1SelCtrl
2721 * 0x10, Vsmps1AutoMode
2722 * 0x20, Vsmps1PWMMode
2723 */
2724 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2725 /*
2726 * 0x03, Vsmps2Regu
2727 * 0x0c, Vsmps2SelCtrl
2728 * 0x10, Vsmps2AutoMode
2729 * 0x20, Vsmps2PWMMode
2730 */
2731 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2732 /*
2733 * 0x03, Vsmps3Regu
2734 * 0x0c, Vsmps3SelCtrl
2735 * 0x10, Vsmps3AutoMode
2736 * 0x20, Vsmps3PWMMode
2737 * NOTE! PRCMU register
2738 */
2739 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2740 /*
2741 * 0x03, VpllRegu
2742 * 0x0c, VanaRegu
2743 */
2744 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2745 /*
2746 * 0x03, VextSupply1Regu
2747 * 0x0c, VextSupply2Regu
2748 * 0x30, VextSupply3Regu
2749 * 0x40, ExtSupply2Bypass
2750 * 0x80, ExtSupply3Bypass
2751 */
2752 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2753 /*
2754 * 0x03, Vaux1Regu
2755 * 0x0c, Vaux2Regu
2756 */
2757 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f),
2758 /*
2759 * 0x0c, VRF1Regu
2760 * 0x03, Vaux3Regu
2761 */
2762 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2763 /*
2764 * 0x3f, Vsmps1Sel1
2765 */
2766 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2767 /*
2768 * 0x3f, Vsmps1Sel2
2769 */
2770 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2771 /*
2772 * 0x3f, Vsmps1Sel3
2773 */
2774 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2775 /*
2776 * 0x3f, Vsmps2Sel1
2777 */
2778 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2779 /*
2780 * 0x3f, Vsmps2Sel2
2781 */
2782 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2783 /*
2784 * 0x3f, Vsmps2Sel3
2785 */
2786 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2787 /*
2788 * 0x7f, Vsmps3Sel1
2789 * NOTE! PRCMU register
2790 */
2791 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2792 /*
2793 * 0x7f, Vsmps3Sel2
2794 * NOTE! PRCMU register
2795 */
2796 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2797 /*
2798 * 0x0f, Vaux1Sel
2799 */
2800 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2801 /*
2802 * 0x0f, Vaux2Sel
2803 */
2804 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f),
2805 /*
2806 * 0x07, Vaux3Sel
2807 * 0x70, Vrf1Sel
2808 */
2809 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77),
2810 /*
2811 * 0x01, VextSupply12LP
2812 */
2813 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2814 /*
2815 * 0x07, Vanasel
2816 * 0x30, Vpllsel
2817 */
2818 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37),
2819 /*
2820 * 0x03, Vaux4RequestCtrl
2821 */
2822 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2823 /*
2824 * 0x03, Vaux4Regu
2825 */
2826 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03),
2827 /*
2828 * 0x0f, Vaux4Sel
2829 */
2830 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2831 /*
2832 * 0x03, Vaux5RequestCtrl
2833 */
2834 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03),
2835 /*
2836 * 0x03, Vaux5Regu
2837 */
2838 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03),
2839 /*
2840 * 0x3f, Vaux5Sel
2841 */
2842 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f),
2843 /*
2844 * 0x03, Vaux6RequestCtrl
2845 */
2846 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03),
2847 /*
2848 * 0x03, Vaux6Regu
2849 */
2850 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03),
2851 /*
2852 * 0x3f, Vaux6Sel
2853 */
2854 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f),
2855 /*
2856 * 0x03, VCLKBRequestCtrl
2857 */
2858 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03),
2859 /*
2860 * 0x03, VCLKBRegu
2861 */
2862 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03),
2863 /*
2864 * 0x07, VCLKBSel
2865 */
2866 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07),
2867 /*
2868 * 0x03, Vrf1RequestCtrl
2869 */
2870 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03),
2871 /*
2872 * 0x01, VpllDisch
2873 * 0x02, Vrf1Disch
2874 * 0x04, Vaux1Disch
2875 * 0x08, Vaux2Disch
2876 * 0x10, Vaux3Disch
2877 * 0x20, Vintcore12Disch
2878 * 0x40, VTVoutDisch
2879 * 0x80, VaudioDisch
2880 */
2881 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2882 /*
2883 * 0x02, VanaDisch
2884 * 0x04, VdmicPullDownEna
2885 * 0x08, VpllPullDownEna
2886 * 0x10, VdmicDisch
2887 */
2888 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e),
2889 /*
2890 * 0x01, Vaux4Disch
2891 */
2892 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2893 /*
2894 * 0x01, Vaux5Disch
2895 * 0x02, Vaux6Disch
2896 * 0x04, VCLKBDisch
2897 */
2898 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07),
2899};
2900
b54969ac 2901static struct of_regulator_match ab8500_regulator_match[] = {
7e715b95
LJ		 2902 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
2903 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
2904 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
2905 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
2906 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
7e715b95
LJ		 2907 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
2908 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
2909 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
2910 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
2911 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
3a8334b9
LJ		 2912};
2913
547f384f
LJ		 2914static struct of_regulator_match ab8505_regulator_match[] = {
2915 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
2916 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
2917 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
2918 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
2919 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
2920 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
2921 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
2922 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
2923 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
2924 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
2925 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
2926 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
2927 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
2928};
2929
ae0a9a3e
LJ		 2930static struct of_regulator_match ab8540_regulator_match[] = {
2931 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, },
2932 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, },
2933 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, },
2934 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, },
684d5ce4
ZH		 2935 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8540_LDO_AUX5, },
2936 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8540_LDO_AUX6, },
ae0a9a3e
LJ		 2937 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, },
2938 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, },
2939 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, },
2940 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
2941 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
2942 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, },
2943 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, },
2944 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, },
2945};
2946
8e6a8d7d
LJ		 2947static struct of_regulator_match ab9540_regulator_match[] = {
2948 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
2949 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
2950 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
2951 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
2952 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
2953 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
2954 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
2955 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
2956 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
2957 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
2958 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
2959};
2960
da45edc7
LJ		 2961static struct {
2962 struct ab8500_regulator_info *info;
2963 int info_size;
2964 struct ab8500_reg_init *init;
2965 int init_size;
2966 struct of_regulator_match *match;
2967 int match_size;
2968} abx500_regulator;
2969
33aeb49e
LJ		 2970static void abx500_get_regulator_info(struct ab8500 *ab8500)
2971{
2972 if (is_ab9540(ab8500)) {
2973 abx500_regulator.info = ab9540_regulator_info;
2974 abx500_regulator.info_size = ARRAY_SIZE(ab9540_regulator_info);
2975 abx500_regulator.init = ab9540_reg_init;
2976 abx500_regulator.init_size = AB9540_NUM_REGULATOR_REGISTERS;
2977 abx500_regulator.match = ab9540_regulator_match;
2978 abx500_regulator.match_size = ARRAY_SIZE(ab9540_regulator_match);
2979 } else if (is_ab8505(ab8500)) {
2980 abx500_regulator.info = ab8505_regulator_info;
2981 abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info);
2982 abx500_regulator.init = ab8505_reg_init;
2983 abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS;
2984 abx500_regulator.match = ab8505_regulator_match;
2985 abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match);
2986 } else if (is_ab8540(ab8500)) {
2987 abx500_regulator.info = ab8540_regulator_info;
2988 abx500_regulator.info_size = ARRAY_SIZE(ab8540_regulator_info);
2989 abx500_regulator.init = ab8540_reg_init;
2990 abx500_regulator.init_size = AB8540_NUM_REGULATOR_REGISTERS;
2991 abx500_regulator.match = ab8540_regulator_match;
2992 abx500_regulator.match_size = ARRAY_SIZE(ab8540_regulator_match);
2993 } else {
2994 abx500_regulator.info = ab8500_regulator_info;
2995 abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info);
2996 abx500_regulator.init = ab8500_reg_init;
2997 abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS;
2998 abx500_regulator.match = ab8500_regulator_match;
2999 abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match);
3000 }
3001}
3002
da45edc7
LJ		 3003static int ab8500_regulator_init_registers(struct platform_device *pdev,
3004 int id, int mask, int value)
3005{
3006 struct ab8500_reg_init *reg_init = abx500_regulator.init;
3007 int err;
3008
3009 BUG_ON(value & ~mask);
3010 BUG_ON(mask & ~reg_init[id].mask);
3011
3012 /* initialize register */
3013 err = abx500_mask_and_set_register_interruptible(
3014 &pdev->dev,
3015 reg_init[id].bank,
3016 reg_init[id].addr,
3017 mask, value);
3018 if (err < 0) {
3019 dev_err(&pdev->dev,
3020 "Failed to initialize 0x%02x, 0x%02x.\n",
3021 reg_init[id].bank,
3022 reg_init[id].addr);
3023 return err;
3024 }
3025 dev_vdbg(&pdev->dev,
3026 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
3027 reg_init[id].bank,
3028 reg_init[id].addr,
3029 mask, value);
3030
3031 return 0;
3032}
3033
3034static int ab8500_regulator_register(struct platform_device *pdev,
3035 struct regulator_init_data *init_data,
3036 int id, struct device_node *np)
3037{
3038 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3039 struct ab8500_regulator_info *info = NULL;
3040 struct regulator_config config = { };
3041 int err;
3042
3043 /* assign per-regulator data */
3044 info = &abx500_regulator.info[id];
3045 info->dev = &pdev->dev;
3046
3047 config.dev = &pdev->dev;
3048 config.init_data = init_data;
3049 config.driver_data = info;
3050 config.of_node = np;
3051
3052 /* fix for hardware before ab8500v2.0 */
3053 if (is_ab8500_1p1_or_earlier(ab8500)) {
3054 if (info->desc.id == AB8500_LDO_AUX3) {
3055 info->desc.n_voltages =
3056 ARRAY_SIZE(ldo_vauxn_voltages);
3057 info->desc.volt_table = ldo_vauxn_voltages;
3058 info->voltage_mask = 0xf;
3059 }
3060 }
3061
3062 /* register regulator with framework */
3063 info->regulator = regulator_register(&info->desc, &config);
3064 if (IS_ERR(info->regulator)) {
3065 err = PTR_ERR(info->regulator);
3066 dev_err(&pdev->dev, "failed to register regulator %s\n",
3067 info->desc.name);
3068 /* when we fail, un-register all earlier regulators */
3069 while (--id >= 0) {
3070 info = &abx500_regulator.info[id];
3071 regulator_unregister(info->regulator);
3072 }
3073 return err;
3074 }
3075
3076 return 0;
3077}
3078
a5023574 3079static int
b54969ac 3080ab8500_regulator_of_probe(struct platform_device *pdev,
b54969ac 3081 struct device_node *np)
3a8334b9 3082{
33aeb49e 3083 struct of_regulator_match *match = abx500_regulator.match;
3a8334b9
LJ		 3084 int err, i;
3085
33aeb49e 3086 for (i = 0; i < abx500_regulator.info_size; i++) {
3a8334b9 3087 err = ab8500_regulator_register(
33aeb49e 3088 pdev, match[i].init_data, i, match[i].of_node);
3a8334b9
LJ		 3089 if (err)
3090 return err;
3091 }
3092
3093 return 0;
3094}
3095
a5023574 3096static int ab8500_regulator_probe(struct platform_device *pdev)
c789ca20
SI		 3097{
3098 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3a8334b9 3099 struct device_node *np = pdev->dev.of_node;
732805a5
BJ		 3100 struct ab8500_platform_data *ppdata;
3101 struct ab8500_regulator_platform_data *pdata;
c789ca20 3102 int i, err;
b54969ac 3103
33aeb49e
LJ		 3104 if (!ab8500) {
3105 dev_err(&pdev->dev, "null mfd parent\n");
3106 return -EINVAL;
8e6a8d7d 3107 }
c789ca20 3108
33aeb49e
LJ		 3109 abx500_get_regulator_info(ab8500);
3110
3a8334b9 3111 if (np) {
33aeb49e
LJ		 3112 err = of_regulator_match(&pdev->dev, np,
3113 abx500_regulator.match,
3114 abx500_regulator.match_size);
3a8334b9
LJ		 3115 if (err < 0) {
3116 dev_err(&pdev->dev,
3117 "Error parsing regulator init data: %d\n", err);
3118 return err;
3119 }
3120
33aeb49e 3121 err = ab8500_regulator_of_probe(pdev, np);
3a8334b9
LJ		 3122 return err;
3123 }
3124
732805a5
BJ		 3125 ppdata = dev_get_platdata(ab8500->dev);
3126 if (!ppdata) {
3127 dev_err(&pdev->dev, "null parent pdata\n");
3128 return -EINVAL;
3129 }
3130
3131 pdata = ppdata->regulator;
fc24b426
BJ		 3132 if (!pdata) {
3133 dev_err(&pdev->dev, "null pdata\n");
3134 return -EINVAL;
3135 }
c789ca20 3136
cb189b07 3137 /* make sure the platform data has the correct size */
33aeb49e 3138 if (pdata->num_regulator != abx500_regulator.info_size) {
79568b94 3139 dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
cb189b07
BJ		 3140 return -EINVAL;
3141 }
3142
da0b0c47
LJ		 3143 /* initialize debug (initial state is recorded with this call) */
3144 err = ab8500_regulator_debug_init(pdev);
3145 if (err)
3146 return err;
3147
79568b94 3148 /* initialize registers */
732805a5 3149 for (i = 0; i < pdata->num_reg_init; i++) {
3c1b8438 3150 int id, mask, value;
79568b94 3151
732805a5
BJ		 3152 id = pdata->reg_init[i].id;
3153 mask = pdata->reg_init[i].mask;
3154 value = pdata->reg_init[i].value;
79568b94
BJ		 3155
3156 /* check for configuration errors */
33aeb49e 3157 BUG_ON(id >= abx500_regulator.init_size);
79568b94 3158
33aeb49e 3159 err = ab8500_regulator_init_registers(pdev, id, mask, value);
a7ac1d9e 3160 if (err < 0)
79568b94 3161 return err;
79568b94
BJ		 3162 }
3163
f7eae37f
RV		 3164 if (!is_ab8505(ab8500)) {
3165 /* register external regulators (before Vaux1, 2 and 3) */
3166 err = ab8500_ext_regulator_init(pdev);
3167 if (err)
3168 return err;
3169 }
d1a82001 3170
c789ca20 3171 /* register all regulators */
33aeb49e 3172 for (i = 0; i < abx500_regulator.info_size; i++) {
b54969ac 3173 err = ab8500_regulator_register(pdev, &pdata->regulator[i],
33aeb49e 3174 i, NULL);
a7ac1d9e 3175 if (err < 0)
c789ca20 3176 return err;
c789ca20
SI		 3177 }
3178
3179 return 0;
3180}
3181
8dc995f5 3182static int ab8500_regulator_remove(struct platform_device *pdev)
c789ca20 3183{
d1a82001 3184 int i, err;
8e6a8d7d 3185 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
b54969ac 3186
33aeb49e 3187 for (i = 0; i < abx500_regulator.info_size; i++) {
c789ca20 3188 struct ab8500_regulator_info *info = NULL;
33aeb49e 3189 info = &abx500_regulator.info[i];
09aefa12
BJ		 3190
3191 dev_vdbg(rdev_get_dev(info->regulator),
3192 "%s-remove\n", info->desc.name);
3193
c789ca20
SI		 3194 regulator_unregister(info->regulator);
3195 }
3196
f7eae37f
RV		 3197 if (!is_ab8505(ab8500)) {
3198 /* remove external regulators (after Vaux1, 2 and 3) */
3199 err = ab8500_ext_regulator_exit(pdev);
3200 if (err)
3201 return err;
3202 }
d1a82001 3203
da0b0c47
LJ		 3204 /* remove regulator debug */
3205 err = ab8500_regulator_debug_exit(pdev);
3206 if (err)
3207 return err;
3208
c789ca20
SI		 3209 return 0;
3210}
3211
3212static struct platform_driver ab8500_regulator_driver = {
3213 .probe = ab8500_regulator_probe,
5eb9f2b9 3214 .remove = ab8500_regulator_remove,
c789ca20
SI		 3215 .driver = {
3216 .name = "ab8500-regulator",
3217 .owner = THIS_MODULE,
3218 },
3219};
3220
3221static int __init ab8500_regulator_init(void)
3222{
3223 int ret;
3224
3225 ret = platform_driver_register(&ab8500_regulator_driver);
3226 if (ret != 0)
3227 pr_err("Failed to register ab8500 regulator: %d\n", ret);
3228
3229 return ret;
3230}
3231subsys_initcall(ab8500_regulator_init);
3232
3233static void __exit ab8500_regulator_exit(void)
3234{
3235 platform_driver_unregister(&ab8500_regulator_driver);
3236}
3237module_exit(ab8500_regulator_exit);
3238
3239MODULE_LICENSE("GPL v2");
3240MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
732805a5 3241MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
547f384f 3242MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
c789ca20
SI		 3243MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
3244MODULE_ALIAS("platform:ab8500-regulator");
Linux 6.x block layer and io_uring tree(s)