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regulator: ab8500: Remove unused voltage_shift field from struct expand_register
[linux-block.git] / drivers / regulator / ab8500.c
CommitLineData
c789ca20
SI		 1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
e1159e6d
BJ		 6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
547f384f 8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
c789ca20
SI		 9 *
10 * AB8500 peripheral regulators
11 *
e1159e6d 12 * AB8500 supports the following regulators:
ea05ef31 13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
547f384f
LJ		 14 *
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
c789ca20
SI		 17 */
18#include <linux/init.h>
19#include <linux/kernel.h>
65602c32 20#include <linux/module.h>
c789ca20
SI		 21#include <linux/err.h>
22#include <linux/platform_device.h>
47c16975 23#include <linux/mfd/abx500.h>
ee66e653 24#include <linux/mfd/abx500/ab8500.h>
3a8334b9
LJ		 25#include <linux/of.h>
26#include <linux/regulator/of_regulator.h>
c789ca20
SI		 27#include <linux/regulator/driver.h>
28#include <linux/regulator/machine.h>
29#include <linux/regulator/ab8500.h>
3a8334b9 30#include <linux/slab.h>
c789ca20 31
3fe52289
LJ		 32/**
33 * struct ab8500_shared_mode - is used when mode is shared between
34 * two regulators.
35 * @shared_regulator: pointer to the other sharing regulator
36 * @lp_mode_req: low power mode requested by this regulator
37 */
38struct ab8500_shared_mode {
39 struct ab8500_regulator_info *shared_regulator;
40 bool lp_mode_req;
41};
42
c789ca20
SI		 43/**
44 * struct ab8500_regulator_info - ab8500 regulator information
e1159e6d 45 * @dev: device pointer
c789ca20 46 * @desc: regulator description
c789ca20 47 * @regulator_dev: regulator device
3fe52289 48 * @shared_mode: used when mode is shared between two regulators
7ce4669c 49 * @load_lp_uA: maximum load in idle (low power) mode
47c16975 50 * @update_bank: bank to control on/off
c789ca20 51 * @update_reg: register to control on/off
bd28a157
EV		 52 * @update_mask: mask to enable/disable and set mode of regulator
53 * @update_val: bits holding the regulator current mode
54 * @update_val_idle: bits to enable the regulator in idle (low power) mode
55 * @update_val_normal: bits to enable the regulator in normal (high power) mode
3fe52289
LJ		 56 * @mode_bank: bank with location of mode register
57 * @mode_reg: mode register
58 * @mode_mask: mask for setting mode
59 * @mode_val_idle: mode setting for low power
60 * @mode_val_normal: mode setting for normal power
47c16975 61 * @voltage_bank: bank to control regulator voltage
c789ca20
SI		 62 * @voltage_reg: register to control regulator voltage
63 * @voltage_mask: mask to control regulator voltage
a0a7014c 64 * @voltage_shift: shift to control regulator voltage
c789ca20
SI		 65 */
66struct ab8500_regulator_info {
67 struct device *dev;
68 struct regulator_desc desc;
c789ca20 69 struct regulator_dev *regulator;
3fe52289 70 struct ab8500_shared_mode *shared_mode;
7ce4669c 71 int load_lp_uA;
47c16975
MW		 72 u8 update_bank;
73 u8 update_reg;
e1159e6d 74 u8 update_mask;
bd28a157
EV		 75 u8 update_val;
76 u8 update_val_idle;
77 u8 update_val_normal;
3fe52289
LJ		 78 u8 mode_bank;
79 u8 mode_reg;
80 u8 mode_mask;
81 u8 mode_val_idle;
82 u8 mode_val_normal;
47c16975
MW		 83 u8 voltage_bank;
84 u8 voltage_reg;
85 u8 voltage_mask;
a0a7014c 86 u8 voltage_shift;
d7607baf
LJ		 87 struct {
88 u8 voltage_limit;
89 u8 voltage_bank;
90 u8 voltage_reg;
91 u8 voltage_mask;
d7607baf 92 } expand_register;
c789ca20
SI		 93};
94
95/* voltage tables for the vauxn/vintcore supplies */
ec1cc4d9 96static const unsigned int ldo_vauxn_voltages[] = {
c789ca20
SI		 97 1100000,
98 1200000,
99 1300000,
100 1400000,
101 1500000,
102 1800000,
103 1850000,
104 1900000,
105 2500000,
106 2650000,
107 2700000,
108 2750000,
109 2800000,
110 2900000,
111 3000000,
112 3300000,
113};
114
ec1cc4d9 115static const unsigned int ldo_vaux3_voltages[] = {
2b75151a
BJ		 116 1200000,
117 1500000,
118 1800000,
119 2100000,
120 2500000,
121 2750000,
122 2790000,
123 2910000,
124};
125
62ab4111 126static const unsigned int ldo_vaux56_voltages[] = {
547f384f
LJ		 127 1800000,
128 1050000,
129 1100000,
130 1200000,
131 1500000,
132 2200000,
133 2500000,
134 2790000,
135};
136
62ab4111 137static const unsigned int ldo_vaux3_ab8540_voltages[] = {
ae0a9a3e
LJ		 138 1200000,
139 1500000,
140 1800000,
141 2100000,
142 2500000,
143 2750000,
144 2790000,
145 2910000,
146 3050000,
147};
148
684d5ce4
ZH		 149static const unsigned int ldo_vaux56_ab8540_voltages[] = {
150 750000, 760000, 770000, 780000, 790000, 800000,
151 810000, 820000, 830000, 840000, 850000, 860000,
152 870000, 880000, 890000, 900000, 910000, 920000,
153 930000, 940000, 950000, 960000, 970000, 980000,
154 990000, 1000000, 1010000, 1020000, 1030000,
155 1040000, 1050000, 1060000, 1070000, 1080000,
156 1090000, 1100000, 1110000, 1120000, 1130000,
157 1140000, 1150000, 1160000, 1170000, 1180000,
158 1190000, 1200000, 1210000, 1220000, 1230000,
159 1240000, 1250000, 1260000, 1270000, 1280000,
160 1290000, 1300000, 1310000, 1320000, 1330000,
161 1340000, 1350000, 1360000, 1800000, 2790000,
162};
163
ec1cc4d9 164static const unsigned int ldo_vintcore_voltages[] = {
c789ca20
SI		 165 1200000,
166 1225000,
167 1250000,
168 1275000,
169 1300000,
170 1325000,
171 1350000,
172};
173
62ab4111 174static const unsigned int ldo_sdio_voltages[] = {
ae0a9a3e
LJ		 175 1160000,
176 1050000,
177 1100000,
178 1500000,
179 1800000,
180 2200000,
181 2910000,
182 3050000,
183};
184
b080c78a
LJ		 185static const unsigned int fixed_1200000_voltage[] = {
186 1200000,
187};
188
189static const unsigned int fixed_1800000_voltage[] = {
190 1800000,
191};
192
193static const unsigned int fixed_2000000_voltage[] = {
194 2000000,
195};
196
197static const unsigned int fixed_2050000_voltage[] = {
198 2050000,
199};
200
201static const unsigned int fixed_3300000_voltage[] = {
202 3300000,
203};
204
8a3b1b87
LJ		 205static const unsigned int ldo_vana_voltages[] = {
206 1050000,
207 1075000,
208 1100000,
209 1125000,
210 1150000,
211 1175000,
212 1200000,
213 1225000,
214};
215
216static const unsigned int ldo_vaudio_voltages[] = {
217 2000000,
218 2100000,
219 2200000,
220 2300000,
221 2400000,
222 2500000,
223 2600000,
224 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
225};
226
4c84b4dd
LJ		 227static const unsigned int ldo_vdmic_voltages[] = {
228 1800000,
229 1900000,
230 2000000,
231 2850000,
232};
233
3fe52289
LJ		 234static DEFINE_MUTEX(shared_mode_mutex);
235static struct ab8500_shared_mode ldo_anamic1_shared;
236static struct ab8500_shared_mode ldo_anamic2_shared;
4c84b4dd
LJ		 237static struct ab8500_shared_mode ab8540_ldo_anamic1_shared;
238static struct ab8500_shared_mode ab8540_ldo_anamic2_shared;
3fe52289 239
c789ca20
SI		 240static int ab8500_regulator_enable(struct regulator_dev *rdev)
241{
fc24b426 242 int ret;
c789ca20
SI		 243 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
244
fc24b426
BJ		 245 if (info == NULL) {
246 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 247 return -EINVAL;
fc24b426 248 }
c789ca20 249
47c16975 250 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d 251 info->update_bank, info->update_reg,
bd28a157 252 info->update_mask, info->update_val);
f71bf528 253 if (ret < 0) {
c789ca20
SI		 254 dev_err(rdev_get_dev(rdev),
255 "couldn't set enable bits for regulator\n");
f71bf528
AL		 256 return ret;
257 }
09aefa12
BJ		 258
259 dev_vdbg(rdev_get_dev(rdev),
260 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
261 info->desc.name, info->update_bank, info->update_reg,
bd28a157 262 info->update_mask, info->update_val);
09aefa12 263
c789ca20
SI		 264 return ret;
265}
266
267static int ab8500_regulator_disable(struct regulator_dev *rdev)
268{
fc24b426 269 int ret;
c789ca20
SI		 270 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
271
fc24b426
BJ		 272 if (info == NULL) {
273 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 274 return -EINVAL;
fc24b426 275 }
c789ca20 276
47c16975 277 ret = abx500_mask_and_set_register_interruptible(info->dev,
e1159e6d
BJ		 278 info->update_bank, info->update_reg,
279 info->update_mask, 0x0);
f71bf528 280 if (ret < 0) {
c789ca20
SI		 281 dev_err(rdev_get_dev(rdev),
282 "couldn't set disable bits for regulator\n");
f71bf528
AL		 283 return ret;
284 }
09aefa12
BJ		 285
286 dev_vdbg(rdev_get_dev(rdev),
287 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
288 info->desc.name, info->update_bank, info->update_reg,
289 info->update_mask, 0x0);
290
c789ca20
SI		 291 return ret;
292}
293
438e695b
AL		 294static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
295{
296 int ret;
297 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
298 u8 regval;
299
300 if (info == NULL) {
301 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
302 return -EINVAL;
303 }
304
305 ret = abx500_get_register_interruptible(info->dev,
306 info->update_bank, info->update_reg, &regval);
307 if (ret < 0) {
308 dev_err(rdev_get_dev(rdev),
309 "couldn't read 0x%x register\n", info->update_reg);
310 return ret;
311 }
312
313 dev_vdbg(rdev_get_dev(rdev),
314 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
315 " 0x%x\n",
316 info->desc.name, info->update_bank, info->update_reg,
317 info->update_mask, regval);
318
319 if (regval & info->update_mask)
320 return 1;
321 else
322 return 0;
323}
324
7ce4669c
BJ		 325static unsigned int ab8500_regulator_get_optimum_mode(
326 struct regulator_dev *rdev, int input_uV,
327 int output_uV, int load_uA)
328{
329 unsigned int mode;
330
331 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
332
333 if (info == NULL) {
334 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
335 return -EINVAL;
336 }
337
338 if (load_uA <= info->load_lp_uA)
339 mode = REGULATOR_MODE_IDLE;
340 else
341 mode = REGULATOR_MODE_NORMAL;
342
343 return mode;
344}
345
bd28a157
EV		 346static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
347 unsigned int mode)
348{
3fe52289 349 int ret = 0;
0b665062
AL		 350 u8 bank, reg, mask, val;
351 bool lp_mode_req = false;
bd28a157
EV		 352 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
353
354 if (info == NULL) {
355 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
356 return -EINVAL;
357 }
358
3fe52289 359 if (info->mode_mask) {
3fe52289
LJ		 360 bank = info->mode_bank;
361 reg = info->mode_reg;
362 mask = info->mode_mask;
363 } else {
0b665062
AL		 364 bank = info->update_bank;
365 reg = info->update_reg;
366 mask = info->update_mask;
367 }
3fe52289 368
0b665062
AL		 369 if (info->shared_mode)
370 mutex_lock(&shared_mode_mutex);
371
372 switch (mode) {
373 case REGULATOR_MODE_NORMAL:
374 if (info->shared_mode)
375 lp_mode_req = false;
376
377 if (info->mode_mask)
378 val = info->mode_val_normal;
379 else
3fe52289 380 val = info->update_val_normal;
0b665062
AL		 381 break;
382 case REGULATOR_MODE_IDLE:
383 if (info->shared_mode) {
384 struct ab8500_regulator_info *shared_regulator;
385
386 shared_regulator = info->shared_mode->shared_regulator;
387 if (!shared_regulator->shared_mode->lp_mode_req) {
388 /* Other regulator prevent LP mode */
389 info->shared_mode->lp_mode_req = true;
390 goto out_unlock;
391 }
392
393 lp_mode_req = true;
3fe52289
LJ		 394 }
395
0b665062
AL		 396 if (info->mode_mask)
397 val = info->mode_val_idle;
398 else
399 val = info->update_val_idle;
400 break;
401 default:
402 ret = -EINVAL;
403 goto out_unlock;
bd28a157
EV		 404 }
405
0b665062 406 if (info->mode_mask || ab8500_regulator_is_enabled(rdev)) {
bd28a157 407 ret = abx500_mask_and_set_register_interruptible(info->dev,
3fe52289 408 bank, reg, mask, val);
f04adc5a 409 if (ret < 0) {
bd28a157
EV		 410 dev_err(rdev_get_dev(rdev),
411 "couldn't set regulator mode\n");
f04adc5a
AL		 412 goto out_unlock;
413 }
7ce4669c
BJ		 414
415 dev_vdbg(rdev_get_dev(rdev),
416 "%s-set_mode (bank, reg, mask, value): "
417 "0x%x, 0x%x, 0x%x, 0x%x\n",
3fe52289
LJ		 418 info->desc.name, bank, reg,
419 mask, val);
bd28a157
EV		 420 }
421
0b665062 422 if (!info->mode_mask)
f04adc5a
AL		 423 info->update_val = val;
424
0b665062
AL		 425 if (info->shared_mode)
426 info->shared_mode->lp_mode_req = lp_mode_req;
427
f04adc5a 428out_unlock:
3fe52289
LJ		 429 if (info->shared_mode)
430 mutex_unlock(&shared_mode_mutex);
742a7325 431
3fe52289 432 return ret;
bd28a157
EV		 433}
434
435static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
436{
437 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
438 int ret;
3fe52289
LJ		 439 u8 val;
440 u8 val_normal;
441 u8 val_idle;
bd28a157
EV		 442
443 if (info == NULL) {
444 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
445 return -EINVAL;
446 }
447
3fe52289
LJ		 448 /* Need special handling for shared mode */
449 if (info->shared_mode) {
450 if (info->shared_mode->lp_mode_req)
451 return REGULATOR_MODE_IDLE;
452 else
453 return REGULATOR_MODE_NORMAL;
454 }
455
456 if (info->mode_mask) {
457 /* Dedicated register for handling mode */
458 ret = abx500_get_register_interruptible(info->dev,
459 info->mode_bank, info->mode_reg, &val);
460 val = val & info->mode_mask;
461
462 val_normal = info->mode_val_normal;
463 val_idle = info->mode_val_idle;
464 } else {
465 /* Mode register same as enable register */
466 val = info->update_val;
467 val_normal = info->update_val_normal;
468 val_idle = info->update_val_idle;
469 }
470
471 if (val == val_normal)
bd28a157 472 ret = REGULATOR_MODE_NORMAL;
3fe52289 473 else if (val == val_idle)
bd28a157
EV		 474 ret = REGULATOR_MODE_IDLE;
475 else
476 ret = -EINVAL;
477
478 return ret;
479}
480
3bf6e90e 481static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
c789ca20 482{
09aefa12 483 int ret, val;
c789ca20 484 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 485 u8 regval;
c789ca20 486
fc24b426
BJ		 487 if (info == NULL) {
488 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 489 return -EINVAL;
fc24b426 490 }
c789ca20 491
09aefa12
BJ		 492 ret = abx500_get_register_interruptible(info->dev,
493 info->voltage_bank, info->voltage_reg, &regval);
c789ca20
SI		 494 if (ret < 0) {
495 dev_err(rdev_get_dev(rdev),
496 "couldn't read voltage reg for regulator\n");
497 return ret;
498 }
499
09aefa12 500 dev_vdbg(rdev_get_dev(rdev),
a0a7014c
LW		 501 "%s-get_voltage (bank, reg, mask, shift, value): "
502 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
503 info->desc.name, info->voltage_bank,
504 info->voltage_reg, info->voltage_mask,
505 info->voltage_shift, regval);
09aefa12 506
09aefa12 507 val = regval & info->voltage_mask;
a0a7014c 508 return val >> info->voltage_shift;
c789ca20
SI		 509}
510
d7607baf
LJ		 511static int ab8540_aux3_regulator_get_voltage_sel(struct regulator_dev *rdev)
512{
241896ce 513 int ret;
d7607baf
LJ		 514 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
515 u8 regval, regval_expand;
516
517 if (info == NULL) {
518 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
519 return -EINVAL;
520 }
521
522 ret = abx500_get_register_interruptible(info->dev,
241896ce
AL		 523 info->expand_register.voltage_bank,
524 info->expand_register.voltage_reg, &regval_expand);
d7607baf
LJ		 525 if (ret < 0) {
526 dev_err(rdev_get_dev(rdev),
241896ce 527 "couldn't read voltage expand reg for regulator\n");
d7607baf
LJ		 528 return ret;
529 }
530
241896ce
AL		 531 dev_vdbg(rdev_get_dev(rdev),
532 "%s-get_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
533 info->desc.name, info->expand_register.voltage_bank,
534 info->expand_register.voltage_reg,
535 info->expand_register.voltage_mask, regval_expand);
d7607baf 536
241896ce
AL		 537 if (regval_expand & info->expand_register.voltage_mask)
538 return info->expand_register.voltage_limit;
539
540 ret = abx500_get_register_interruptible(info->dev,
541 info->voltage_bank, info->voltage_reg, &regval);
d7607baf
LJ		 542 if (ret < 0) {
543 dev_err(rdev_get_dev(rdev),
544 "couldn't read voltage reg for regulator\n");
545 return ret;
546 }
547
548 dev_vdbg(rdev_get_dev(rdev),
241896ce
AL		 549 "%s-get_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
550 info->desc.name, info->voltage_bank, info->voltage_reg,
551 info->voltage_mask, regval);
d7607baf 552
241896ce 553 return (regval & info->voltage_mask) >> info->voltage_shift;
d7607baf
LJ		 554}
555
ae713d39
AL		 556static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
557 unsigned selector)
c789ca20 558{
fc24b426 559 int ret;
c789ca20 560 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
09aefa12 561 u8 regval;
c789ca20 562
fc24b426
BJ		 563 if (info == NULL) {
564 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
c789ca20 565 return -EINVAL;
fc24b426 566 }
c789ca20 567
c789ca20 568 /* set the registers for the request */
a0a7014c 569 regval = (u8)selector << info->voltage_shift;
47c16975 570 ret = abx500_mask_and_set_register_interruptible(info->dev,
09aefa12
BJ		 571 info->voltage_bank, info->voltage_reg,
572 info->voltage_mask, regval);
c789ca20
SI		 573 if (ret < 0)
574 dev_err(rdev_get_dev(rdev),
575 "couldn't set voltage reg for regulator\n");
576
09aefa12
BJ		 577 dev_vdbg(rdev_get_dev(rdev),
578 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
579 " 0x%x\n",
580 info->desc.name, info->voltage_bank, info->voltage_reg,
581 info->voltage_mask, regval);
582
c789ca20
SI		 583 return ret;
584}
585
d7607baf
LJ		 586static int ab8540_aux3_regulator_set_voltage_sel(struct regulator_dev *rdev,
587 unsigned selector)
588{
589 int ret;
590 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
b4d12a79 591 u8 regval, regval_expand;
d7607baf
LJ		 592
593 if (info == NULL) {
594 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
595 return -EINVAL;
596 }
597
b4d12a79 598 if (selector < info->expand_register.voltage_limit) {
d7607baf
LJ		 599 regval = (u8)selector << info->voltage_shift;
600 ret = abx500_mask_and_set_register_interruptible(info->dev,
b4d12a79
AL		 601 info->voltage_bank, info->voltage_reg,
602 info->voltage_mask, regval);
603 if (ret < 0) {
604 dev_err(rdev_get_dev(rdev),
605 "couldn't set voltage reg for regulator\n");
606 return ret;
607 }
608
609 dev_vdbg(rdev_get_dev(rdev),
610 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
611 info->desc.name, info->voltage_bank, info->voltage_reg,
612 info->voltage_mask, regval);
613
614 regval_expand = 0;
615 } else {
616 regval_expand = info->expand_register.voltage_mask;
d7607baf 617 }
b4d12a79
AL		 618
619 ret = abx500_mask_and_set_register_interruptible(info->dev,
620 info->expand_register.voltage_bank,
621 info->expand_register.voltage_reg,
622 info->expand_register.voltage_mask,
623 regval_expand);
624 if (ret < 0) {
d7607baf 625 dev_err(rdev_get_dev(rdev),
b4d12a79
AL		 626 "couldn't set expand voltage reg for regulator\n");
627 return ret;
628 }
d7607baf
LJ		 629
630 dev_vdbg(rdev_get_dev(rdev),
b4d12a79
AL		 631 "%s-set_voltage expand (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
632 info->desc.name, info->expand_register.voltage_bank,
633 info->expand_register.voltage_reg,
634 info->expand_register.voltage_mask, regval_expand);
d7607baf 635
b4d12a79 636 return 0;
d7607baf
LJ		 637}
638
7ce4669c
BJ		 639static struct regulator_ops ab8500_regulator_volt_mode_ops = {
640 .enable = ab8500_regulator_enable,
641 .disable = ab8500_regulator_disable,
642 .is_enabled = ab8500_regulator_is_enabled,
643 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
644 .set_mode = ab8500_regulator_set_mode,
645 .get_mode = ab8500_regulator_get_mode,
646 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
647 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
648 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 649};
650
d7607baf
LJ		 651static struct regulator_ops ab8540_aux3_regulator_volt_mode_ops = {
652 .enable = ab8500_regulator_enable,
653 .disable = ab8500_regulator_disable,
654 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
655 .set_mode = ab8500_regulator_set_mode,
656 .get_mode = ab8500_regulator_get_mode,
657 .is_enabled = ab8500_regulator_is_enabled,
658 .get_voltage_sel = ab8540_aux3_regulator_get_voltage_sel,
659 .set_voltage_sel = ab8540_aux3_regulator_set_voltage_sel,
660 .list_voltage = regulator_list_voltage_table,
d7607baf
LJ		 661};
662
8a3b1b87
LJ		 663static struct regulator_ops ab8500_regulator_volt_ops = {
664 .enable = ab8500_regulator_enable,
665 .disable = ab8500_regulator_disable,
666 .is_enabled = ab8500_regulator_is_enabled,
667 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
668 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
669 .list_voltage = regulator_list_voltage_table,
8a3b1b87
LJ		 670};
671
7ce4669c
BJ		 672static struct regulator_ops ab8500_regulator_mode_ops = {
673 .enable = ab8500_regulator_enable,
674 .disable = ab8500_regulator_disable,
675 .is_enabled = ab8500_regulator_is_enabled,
676 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
677 .set_mode = ab8500_regulator_set_mode,
678 .get_mode = ab8500_regulator_get_mode,
d7816ab0 679 .list_voltage = regulator_list_voltage_table,
7ce4669c
BJ		 680};
681
682static struct regulator_ops ab8500_regulator_ops = {
683 .enable = ab8500_regulator_enable,
684 .disable = ab8500_regulator_disable,
685 .is_enabled = ab8500_regulator_is_enabled,
d7816ab0 686 .list_voltage = regulator_list_voltage_table,
c789ca20
SI		 687};
688
3fe52289
LJ		 689static struct regulator_ops ab8500_regulator_anamic_mode_ops = {
690 .enable = ab8500_regulator_enable,
691 .disable = ab8500_regulator_disable,
692 .is_enabled = ab8500_regulator_is_enabled,
693 .set_mode = ab8500_regulator_set_mode,
694 .get_mode = ab8500_regulator_get_mode,
695 .list_voltage = regulator_list_voltage_table,
696};
697
8e6a8d7d 698/* AB8500 regulator information */
6909b452
BJ		 699static struct ab8500_regulator_info
700 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
c789ca20 701 /*
e1159e6d
BJ		 702 * Variable Voltage Regulators
703 * name, min mV, max mV,
704 * update bank, reg, mask, enable val
ec1cc4d9 705 * volt bank, reg, mask
c789ca20 706 */
6909b452
BJ		 707 [AB8500_LDO_AUX1] = {
708 .desc = {
709 .name = "LDO-AUX1",
7ce4669c 710 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 711 .type = REGULATOR_VOLTAGE,
712 .id = AB8500_LDO_AUX1,
713 .owner = THIS_MODULE,
714 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 715 .volt_table = ldo_vauxn_voltages,
530158b6 716 .enable_time = 200,
6909b452 717 },
7ce4669c 718 .load_lp_uA = 5000,
6909b452
BJ		 719 .update_bank = 0x04,
720 .update_reg = 0x09,
721 .update_mask = 0x03,
bd28a157
EV		 722 .update_val = 0x01,
723 .update_val_idle = 0x03,
724 .update_val_normal = 0x01,
6909b452
BJ		 725 .voltage_bank = 0x04,
726 .voltage_reg = 0x1f,
727 .voltage_mask = 0x0f,
6909b452
BJ		 728 },
729 [AB8500_LDO_AUX2] = {
730 .desc = {
731 .name = "LDO-AUX2",
7ce4669c 732 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 733 .type = REGULATOR_VOLTAGE,
734 .id = AB8500_LDO_AUX2,
735 .owner = THIS_MODULE,
736 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
ec1cc4d9 737 .volt_table = ldo_vauxn_voltages,
530158b6 738 .enable_time = 200,
6909b452 739 },
7ce4669c 740 .load_lp_uA = 5000,
6909b452
BJ		 741 .update_bank = 0x04,
742 .update_reg = 0x09,
743 .update_mask = 0x0c,
bd28a157
EV		 744 .update_val = 0x04,
745 .update_val_idle = 0x0c,
746 .update_val_normal = 0x04,
6909b452
BJ		 747 .voltage_bank = 0x04,
748 .voltage_reg = 0x20,
749 .voltage_mask = 0x0f,
6909b452
BJ		 750 },
751 [AB8500_LDO_AUX3] = {
752 .desc = {
753 .name = "LDO-AUX3",
7ce4669c 754 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 755 .type = REGULATOR_VOLTAGE,
756 .id = AB8500_LDO_AUX3,
757 .owner = THIS_MODULE,
758 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
ec1cc4d9 759 .volt_table = ldo_vaux3_voltages,
530158b6 760 .enable_time = 450,
6909b452 761 },
7ce4669c 762 .load_lp_uA = 5000,
6909b452
BJ		 763 .update_bank = 0x04,
764 .update_reg = 0x0a,
765 .update_mask = 0x03,
bd28a157
EV		 766 .update_val = 0x01,
767 .update_val_idle = 0x03,
768 .update_val_normal = 0x01,
6909b452
BJ		 769 .voltage_bank = 0x04,
770 .voltage_reg = 0x21,
771 .voltage_mask = 0x07,
6909b452
BJ		 772 },
773 [AB8500_LDO_INTCORE] = {
774 .desc = {
775 .name = "LDO-INTCORE",
7ce4669c 776 .ops = &ab8500_regulator_volt_mode_ops,
6909b452
BJ		 777 .type = REGULATOR_VOLTAGE,
778 .id = AB8500_LDO_INTCORE,
779 .owner = THIS_MODULE,
780 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
ec1cc4d9 781 .volt_table = ldo_vintcore_voltages,
530158b6 782 .enable_time = 750,
6909b452 783 },
7ce4669c 784 .load_lp_uA = 5000,
6909b452
BJ		 785 .update_bank = 0x03,
786 .update_reg = 0x80,
787 .update_mask = 0x44,
cc40dc29 788 .update_val = 0x44,
bd28a157
EV		 789 .update_val_idle = 0x44,
790 .update_val_normal = 0x04,
6909b452
BJ		 791 .voltage_bank = 0x03,
792 .voltage_reg = 0x80,
793 .voltage_mask = 0x38,
a0a7014c 794 .voltage_shift = 3,
6909b452 795 },
c789ca20
SI		 796
797 /*
e1159e6d
BJ		 798 * Fixed Voltage Regulators
799 * name, fixed mV,
800 * update bank, reg, mask, enable val
c789ca20 801 */
6909b452
BJ		 802 [AB8500_LDO_TVOUT] = {
803 .desc = {
804 .name = "LDO-TVOUT",
7ce4669c 805 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 806 .type = REGULATOR_VOLTAGE,
807 .id = AB8500_LDO_TVOUT,
808 .owner = THIS_MODULE,
809 .n_voltages = 1,
b080c78a 810 .volt_table = fixed_2000000_voltage,
ed3c138e 811 .enable_time = 500,
6909b452 812 },
7ce4669c 813 .load_lp_uA = 1000,
6909b452
BJ		 814 .update_bank = 0x03,
815 .update_reg = 0x80,
816 .update_mask = 0x82,
bd28a157 817 .update_val = 0x02,
7ce4669c
BJ		 818 .update_val_idle = 0x82,
819 .update_val_normal = 0x02,
6909b452
BJ		 820 },
821 [AB8500_LDO_AUDIO] = {
822 .desc = {
823 .name = "LDO-AUDIO",
7ce4669c 824 .ops = &ab8500_regulator_ops,
6909b452
BJ		 825 .type = REGULATOR_VOLTAGE,
826 .id = AB8500_LDO_AUDIO,
827 .owner = THIS_MODULE,
828 .n_voltages = 1,
530158b6 829 .enable_time = 140,
b080c78a 830 .volt_table = fixed_2000000_voltage,
6909b452 831 },
6909b452
BJ		 832 .update_bank = 0x03,
833 .update_reg = 0x83,
834 .update_mask = 0x02,
bd28a157 835 .update_val = 0x02,
6909b452
BJ		 836 },
837 [AB8500_LDO_ANAMIC1] = {
838 .desc = {
839 .name = "LDO-ANAMIC1",
7ce4669c 840 .ops = &ab8500_regulator_ops,
6909b452
BJ		 841 .type = REGULATOR_VOLTAGE,
842 .id = AB8500_LDO_ANAMIC1,
843 .owner = THIS_MODULE,
844 .n_voltages = 1,
530158b6 845 .enable_time = 500,
b080c78a 846 .volt_table = fixed_2050000_voltage,
6909b452 847 },
6909b452
BJ		 848 .update_bank = 0x03,
849 .update_reg = 0x83,
850 .update_mask = 0x08,
bd28a157 851 .update_val = 0x08,
6909b452
BJ		 852 },
853 [AB8500_LDO_ANAMIC2] = {
854 .desc = {
855 .name = "LDO-ANAMIC2",
7ce4669c 856 .ops = &ab8500_regulator_ops,
6909b452
BJ		 857 .type = REGULATOR_VOLTAGE,
858 .id = AB8500_LDO_ANAMIC2,
859 .owner = THIS_MODULE,
860 .n_voltages = 1,
530158b6 861 .enable_time = 500,
b080c78a 862 .volt_table = fixed_2050000_voltage,
6909b452 863 },
6909b452
BJ		 864 .update_bank = 0x03,
865 .update_reg = 0x83,
866 .update_mask = 0x10,
bd28a157 867 .update_val = 0x10,
6909b452
BJ		 868 },
869 [AB8500_LDO_DMIC] = {
870 .desc = {
871 .name = "LDO-DMIC",
7ce4669c 872 .ops = &ab8500_regulator_ops,
6909b452
BJ		 873 .type = REGULATOR_VOLTAGE,
874 .id = AB8500_LDO_DMIC,
875 .owner = THIS_MODULE,
876 .n_voltages = 1,
530158b6 877 .enable_time = 420,
b080c78a 878 .volt_table = fixed_1800000_voltage,
6909b452 879 },
6909b452
BJ		 880 .update_bank = 0x03,
881 .update_reg = 0x83,
882 .update_mask = 0x04,
bd28a157 883 .update_val = 0x04,
6909b452 884 },
7ce4669c
BJ		 885
886 /*
887 * Regulators with fixed voltage and normal/idle modes
888 */
6909b452
BJ		 889 [AB8500_LDO_ANA] = {
890 .desc = {
891 .name = "LDO-ANA",
7ce4669c 892 .ops = &ab8500_regulator_mode_ops,
6909b452
BJ		 893 .type = REGULATOR_VOLTAGE,
894 .id = AB8500_LDO_ANA,
895 .owner = THIS_MODULE,
896 .n_voltages = 1,
530158b6 897 .enable_time = 140,
b080c78a 898 .volt_table = fixed_1200000_voltage,
6909b452 899 },
7ce4669c 900 .load_lp_uA = 1000,
6909b452
BJ		 901 .update_bank = 0x04,
902 .update_reg = 0x06,
903 .update_mask = 0x0c,
bd28a157 904 .update_val = 0x04,
7ce4669c
BJ		 905 .update_val_idle = 0x0c,
906 .update_val_normal = 0x04,
6909b452 907 },
8e6a8d7d 908};
6909b452 909
547f384f
LJ		 910/* AB8505 regulator information */
911static struct ab8500_regulator_info
912 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
913 /*
914 * Variable Voltage Regulators
915 * name, min mV, max mV,
916 * update bank, reg, mask, enable val
d3193103 917 * volt bank, reg, mask
547f384f
LJ		 918 */
919 [AB8505_LDO_AUX1] = {
920 .desc = {
921 .name = "LDO-AUX1",
922 .ops = &ab8500_regulator_volt_mode_ops,
923 .type = REGULATOR_VOLTAGE,
0b946411 924 .id = AB8505_LDO_AUX1,
547f384f
LJ		 925 .owner = THIS_MODULE,
926 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 927 .volt_table = ldo_vauxn_voltages,
547f384f 928 },
547f384f
LJ		 929 .load_lp_uA = 5000,
930 .update_bank = 0x04,
931 .update_reg = 0x09,
932 .update_mask = 0x03,
933 .update_val = 0x01,
934 .update_val_idle = 0x03,
935 .update_val_normal = 0x01,
936 .voltage_bank = 0x04,
937 .voltage_reg = 0x1f,
938 .voltage_mask = 0x0f,
547f384f
LJ		 939 },
940 [AB8505_LDO_AUX2] = {
941 .desc = {
942 .name = "LDO-AUX2",
943 .ops = &ab8500_regulator_volt_mode_ops,
944 .type = REGULATOR_VOLTAGE,
0b946411 945 .id = AB8505_LDO_AUX2,
547f384f
LJ		 946 .owner = THIS_MODULE,
947 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 948 .volt_table = ldo_vauxn_voltages,
547f384f 949 },
547f384f
LJ		 950 .load_lp_uA = 5000,
951 .update_bank = 0x04,
952 .update_reg = 0x09,
953 .update_mask = 0x0c,
954 .update_val = 0x04,
955 .update_val_idle = 0x0c,
956 .update_val_normal = 0x04,
957 .voltage_bank = 0x04,
958 .voltage_reg = 0x20,
959 .voltage_mask = 0x0f,
547f384f
LJ		 960 },
961 [AB8505_LDO_AUX3] = {
962 .desc = {
963 .name = "LDO-AUX3",
964 .ops = &ab8500_regulator_volt_mode_ops,
965 .type = REGULATOR_VOLTAGE,
0b946411 966 .id = AB8505_LDO_AUX3,
547f384f
LJ		 967 .owner = THIS_MODULE,
968 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 969 .volt_table = ldo_vaux3_voltages,
547f384f 970 },
547f384f
LJ		 971 .load_lp_uA = 5000,
972 .update_bank = 0x04,
973 .update_reg = 0x0a,
974 .update_mask = 0x03,
975 .update_val = 0x01,
976 .update_val_idle = 0x03,
977 .update_val_normal = 0x01,
978 .voltage_bank = 0x04,
979 .voltage_reg = 0x21,
980 .voltage_mask = 0x07,
547f384f
LJ		 981 },
982 [AB8505_LDO_AUX4] = {
983 .desc = {
984 .name = "LDO-AUX4",
985 .ops = &ab8500_regulator_volt_mode_ops,
986 .type = REGULATOR_VOLTAGE,
0b946411 987 .id = AB8505_LDO_AUX4,
547f384f
LJ		 988 .owner = THIS_MODULE,
989 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 990 .volt_table = ldo_vauxn_voltages,
547f384f 991 },
547f384f
LJ		 992 .load_lp_uA = 5000,
993 /* values for Vaux4Regu register */
994 .update_bank = 0x04,
995 .update_reg = 0x2e,
996 .update_mask = 0x03,
997 .update_val = 0x01,
998 .update_val_idle = 0x03,
999 .update_val_normal = 0x01,
1000 /* values for Vaux4SEL register */
1001 .voltage_bank = 0x04,
1002 .voltage_reg = 0x2f,
1003 .voltage_mask = 0x0f,
547f384f
LJ		 1004 },
1005 [AB8505_LDO_AUX5] = {
1006 .desc = {
1007 .name = "LDO-AUX5",
1008 .ops = &ab8500_regulator_volt_mode_ops,
1009 .type = REGULATOR_VOLTAGE,
1010 .id = AB8505_LDO_AUX5,
1011 .owner = THIS_MODULE,
1012 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1013 .volt_table = ldo_vaux56_voltages,
547f384f 1014 },
547f384f
LJ		 1015 .load_lp_uA = 2000,
1016 /* values for CtrlVaux5 register */
1017 .update_bank = 0x01,
1018 .update_reg = 0x55,
ae0a9a3e
LJ		 1019 .update_mask = 0x18,
1020 .update_val = 0x10,
1021 .update_val_idle = 0x18,
1022 .update_val_normal = 0x10,
547f384f
LJ		 1023 .voltage_bank = 0x01,
1024 .voltage_reg = 0x55,
1025 .voltage_mask = 0x07,
547f384f
LJ		 1026 },
1027 [AB8505_LDO_AUX6] = {
1028 .desc = {
1029 .name = "LDO-AUX6",
1030 .ops = &ab8500_regulator_volt_mode_ops,
1031 .type = REGULATOR_VOLTAGE,
1032 .id = AB8505_LDO_AUX6,
1033 .owner = THIS_MODULE,
1034 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
62ab4111 1035 .volt_table = ldo_vaux56_voltages,
547f384f 1036 },
547f384f
LJ		 1037 .load_lp_uA = 2000,
1038 /* values for CtrlVaux6 register */
1039 .update_bank = 0x01,
1040 .update_reg = 0x56,
ae0a9a3e
LJ		 1041 .update_mask = 0x18,
1042 .update_val = 0x10,
1043 .update_val_idle = 0x18,
1044 .update_val_normal = 0x10,
547f384f
LJ		 1045 .voltage_bank = 0x01,
1046 .voltage_reg = 0x56,
1047 .voltage_mask = 0x07,
547f384f
LJ		 1048 },
1049 [AB8505_LDO_INTCORE] = {
1050 .desc = {
1051 .name = "LDO-INTCORE",
1052 .ops = &ab8500_regulator_volt_mode_ops,
1053 .type = REGULATOR_VOLTAGE,
0b946411 1054 .id = AB8505_LDO_INTCORE,
547f384f
LJ		 1055 .owner = THIS_MODULE,
1056 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1057 .volt_table = ldo_vintcore_voltages,
547f384f 1058 },
547f384f
LJ		 1059 .load_lp_uA = 5000,
1060 .update_bank = 0x03,
1061 .update_reg = 0x80,
1062 .update_mask = 0x44,
1063 .update_val = 0x04,
1064 .update_val_idle = 0x44,
1065 .update_val_normal = 0x04,
1066 .voltage_bank = 0x03,
1067 .voltage_reg = 0x80,
1068 .voltage_mask = 0x38,
547f384f
LJ		 1069 .voltage_shift = 3,
1070 },
1071
1072 /*
1073 * Fixed Voltage Regulators
1074 * name, fixed mV,
1075 * update bank, reg, mask, enable val
1076 */
1077 [AB8505_LDO_ADC] = {
1078 .desc = {
1079 .name = "LDO-ADC",
1080 .ops = &ab8500_regulator_mode_ops,
1081 .type = REGULATOR_VOLTAGE,
1082 .id = AB8505_LDO_ADC,
1083 .owner = THIS_MODULE,
1084 .n_voltages = 1,
b080c78a 1085 .volt_table = fixed_2000000_voltage,
a4d68468 1086 .enable_time = 10000,
547f384f 1087 },
547f384f
LJ		 1088 .load_lp_uA = 1000,
1089 .update_bank = 0x03,
1090 .update_reg = 0x80,
1091 .update_mask = 0x82,
1092 .update_val = 0x02,
1093 .update_val_idle = 0x82,
1094 .update_val_normal = 0x02,
1095 },
1096 [AB8505_LDO_USB] = {
1097 .desc = {
1098 .name = "LDO-USB",
1099 .ops = &ab8500_regulator_mode_ops,
1100 .type = REGULATOR_VOLTAGE,
0b946411 1101 .id = AB8505_LDO_USB,
547f384f
LJ		 1102 .owner = THIS_MODULE,
1103 .n_voltages = 1,
b080c78a 1104 .volt_table = fixed_3300000_voltage,
547f384f 1105 },
547f384f
LJ		 1106 .update_bank = 0x03,
1107 .update_reg = 0x82,
1108 .update_mask = 0x03,
1109 .update_val = 0x01,
1110 .update_val_idle = 0x03,
1111 .update_val_normal = 0x01,
1112 },
1113 [AB8505_LDO_AUDIO] = {
1114 .desc = {
1115 .name = "LDO-AUDIO",
8a3b1b87 1116 .ops = &ab8500_regulator_volt_ops,
547f384f 1117 .type = REGULATOR_VOLTAGE,
0b946411 1118 .id = AB8505_LDO_AUDIO,
547f384f 1119 .owner = THIS_MODULE,
8a3b1b87
LJ		 1120 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
1121 .volt_table = ldo_vaudio_voltages,
547f384f 1122 },
547f384f
LJ		 1123 .update_bank = 0x03,
1124 .update_reg = 0x83,
1125 .update_mask = 0x02,
1126 .update_val = 0x02,
8a3b1b87
LJ		 1127 .voltage_bank = 0x01,
1128 .voltage_reg = 0x57,
e4fc9d6d 1129 .voltage_mask = 0x70,
8a3b1b87 1130 .voltage_shift = 4,
547f384f
LJ		 1131 },
1132 [AB8505_LDO_ANAMIC1] = {
1133 .desc = {
1134 .name = "LDO-ANAMIC1",
3fe52289 1135 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1136 .type = REGULATOR_VOLTAGE,
0b946411 1137 .id = AB8505_LDO_ANAMIC1,
547f384f
LJ		 1138 .owner = THIS_MODULE,
1139 .n_voltages = 1,
b080c78a 1140 .volt_table = fixed_2050000_voltage,
547f384f 1141 },
4c84b4dd 1142 .shared_mode = &ldo_anamic1_shared,
547f384f
LJ		 1143 .update_bank = 0x03,
1144 .update_reg = 0x83,
1145 .update_mask = 0x08,
1146 .update_val = 0x08,
3fe52289
LJ		 1147 .mode_bank = 0x01,
1148 .mode_reg = 0x54,
1149 .mode_mask = 0x04,
1150 .mode_val_idle = 0x04,
1151 .mode_val_normal = 0x00,
547f384f
LJ		 1152 },
1153 [AB8505_LDO_ANAMIC2] = {
1154 .desc = {
1155 .name = "LDO-ANAMIC2",
3fe52289 1156 .ops = &ab8500_regulator_anamic_mode_ops,
547f384f 1157 .type = REGULATOR_VOLTAGE,
0b946411 1158 .id = AB8505_LDO_ANAMIC2,
547f384f
LJ		 1159 .owner = THIS_MODULE,
1160 .n_voltages = 1,
b080c78a 1161 .volt_table = fixed_2050000_voltage,
547f384f 1162 },
3fe52289 1163 .shared_mode = &ldo_anamic2_shared,
547f384f
LJ		 1164 .update_bank = 0x03,
1165 .update_reg = 0x83,
1166 .update_mask = 0x10,
1167 .update_val = 0x10,
3fe52289
LJ		 1168 .mode_bank = 0x01,
1169 .mode_reg = 0x54,
1170 .mode_mask = 0x04,
1171 .mode_val_idle = 0x04,
1172 .mode_val_normal = 0x00,
547f384f
LJ		 1173 },
1174 [AB8505_LDO_AUX8] = {
1175 .desc = {
1176 .name = "LDO-AUX8",
1177 .ops = &ab8500_regulator_ops,
1178 .type = REGULATOR_VOLTAGE,
1179 .id = AB8505_LDO_AUX8,
1180 .owner = THIS_MODULE,
1181 .n_voltages = 1,
b080c78a 1182 .volt_table = fixed_1800000_voltage,
547f384f 1183 },
547f384f
LJ		 1184 .update_bank = 0x03,
1185 .update_reg = 0x83,
1186 .update_mask = 0x04,
1187 .update_val = 0x04,
1188 },
1189 /*
1190 * Regulators with fixed voltage and normal/idle modes
1191 */
1192 [AB8505_LDO_ANA] = {
1193 .desc = {
1194 .name = "LDO-ANA",
8a3b1b87 1195 .ops = &ab8500_regulator_volt_mode_ops,
547f384f 1196 .type = REGULATOR_VOLTAGE,
0b946411 1197 .id = AB8505_LDO_ANA,
547f384f 1198 .owner = THIS_MODULE,
8a3b1b87
LJ		 1199 .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
1200 .volt_table = ldo_vana_voltages,
547f384f 1201 },
547f384f
LJ		 1202 .load_lp_uA = 1000,
1203 .update_bank = 0x04,
1204 .update_reg = 0x06,
1205 .update_mask = 0x0c,
1206 .update_val = 0x04,
1207 .update_val_idle = 0x0c,
1208 .update_val_normal = 0x04,
8a3b1b87
LJ		 1209 .voltage_bank = 0x04,
1210 .voltage_reg = 0x29,
1211 .voltage_mask = 0x7,
547f384f
LJ		 1212 },
1213};
1214
8e6a8d7d
LJ		 1215/* AB9540 regulator information */
1216static struct ab8500_regulator_info
1217 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
1218 /*
1219 * Variable Voltage Regulators
1220 * name, min mV, max mV,
1221 * update bank, reg, mask, enable val
d3193103 1222 * volt bank, reg, mask
8e6a8d7d
LJ		 1223 */
1224 [AB9540_LDO_AUX1] = {
1225 .desc = {
1226 .name = "LDO-AUX1",
1227 .ops = &ab8500_regulator_volt_mode_ops,
1228 .type = REGULATOR_VOLTAGE,
0b946411 1229 .id = AB9540_LDO_AUX1,
8e6a8d7d
LJ		 1230 .owner = THIS_MODULE,
1231 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1232 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1233 },
8e6a8d7d
LJ		 1234 .load_lp_uA = 5000,
1235 .update_bank = 0x04,
1236 .update_reg = 0x09,
1237 .update_mask = 0x03,
1238 .update_val = 0x01,
1239 .update_val_idle = 0x03,
1240 .update_val_normal = 0x01,
1241 .voltage_bank = 0x04,
1242 .voltage_reg = 0x1f,
1243 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1244 },
1245 [AB9540_LDO_AUX2] = {
1246 .desc = {
1247 .name = "LDO-AUX2",
1248 .ops = &ab8500_regulator_volt_mode_ops,
1249 .type = REGULATOR_VOLTAGE,
0b946411 1250 .id = AB9540_LDO_AUX2,
8e6a8d7d
LJ		 1251 .owner = THIS_MODULE,
1252 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1253 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1254 },
8e6a8d7d
LJ		 1255 .load_lp_uA = 5000,
1256 .update_bank = 0x04,
1257 .update_reg = 0x09,
1258 .update_mask = 0x0c,
1259 .update_val = 0x04,
1260 .update_val_idle = 0x0c,
1261 .update_val_normal = 0x04,
1262 .voltage_bank = 0x04,
1263 .voltage_reg = 0x20,
1264 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1265 },
1266 [AB9540_LDO_AUX3] = {
1267 .desc = {
1268 .name = "LDO-AUX3",
1269 .ops = &ab8500_regulator_volt_mode_ops,
1270 .type = REGULATOR_VOLTAGE,
0b946411 1271 .id = AB9540_LDO_AUX3,
8e6a8d7d
LJ		 1272 .owner = THIS_MODULE,
1273 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
62ab4111 1274 .volt_table = ldo_vaux3_voltages,
8e6a8d7d 1275 },
8e6a8d7d
LJ		 1276 .load_lp_uA = 5000,
1277 .update_bank = 0x04,
1278 .update_reg = 0x0a,
1279 .update_mask = 0x03,
1280 .update_val = 0x01,
1281 .update_val_idle = 0x03,
1282 .update_val_normal = 0x01,
1283 .voltage_bank = 0x04,
1284 .voltage_reg = 0x21,
1285 .voltage_mask = 0x07,
8e6a8d7d
LJ		 1286 },
1287 [AB9540_LDO_AUX4] = {
1288 .desc = {
1289 .name = "LDO-AUX4",
1290 .ops = &ab8500_regulator_volt_mode_ops,
1291 .type = REGULATOR_VOLTAGE,
1292 .id = AB9540_LDO_AUX4,
1293 .owner = THIS_MODULE,
1294 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1295 .volt_table = ldo_vauxn_voltages,
8e6a8d7d 1296 },
8e6a8d7d
LJ		 1297 .load_lp_uA = 5000,
1298 /* values for Vaux4Regu register */
1299 .update_bank = 0x04,
1300 .update_reg = 0x2e,
1301 .update_mask = 0x03,
1302 .update_val = 0x01,
1303 .update_val_idle = 0x03,
1304 .update_val_normal = 0x01,
1305 /* values for Vaux4SEL register */
1306 .voltage_bank = 0x04,
1307 .voltage_reg = 0x2f,
1308 .voltage_mask = 0x0f,
8e6a8d7d
LJ		 1309 },
1310 [AB9540_LDO_INTCORE] = {
1311 .desc = {
1312 .name = "LDO-INTCORE",
1313 .ops = &ab8500_regulator_volt_mode_ops,
1314 .type = REGULATOR_VOLTAGE,
0b946411 1315 .id = AB9540_LDO_INTCORE,
8e6a8d7d
LJ		 1316 .owner = THIS_MODULE,
1317 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1318 .volt_table = ldo_vintcore_voltages,
8e6a8d7d 1319 },
8e6a8d7d
LJ		 1320 .load_lp_uA = 5000,
1321 .update_bank = 0x03,
1322 .update_reg = 0x80,
1323 .update_mask = 0x44,
1324 .update_val = 0x44,
1325 .update_val_idle = 0x44,
1326 .update_val_normal = 0x04,
1327 .voltage_bank = 0x03,
1328 .voltage_reg = 0x80,
1329 .voltage_mask = 0x38,
8e6a8d7d
LJ		 1330 .voltage_shift = 3,
1331 },
6909b452 1332
8e6a8d7d
LJ		 1333 /*
1334 * Fixed Voltage Regulators
1335 * name, fixed mV,
1336 * update bank, reg, mask, enable val
1337 */
1338 [AB9540_LDO_TVOUT] = {
1339 .desc = {
1340 .name = "LDO-TVOUT",
1341 .ops = &ab8500_regulator_mode_ops,
1342 .type = REGULATOR_VOLTAGE,
0b946411 1343 .id = AB9540_LDO_TVOUT,
8e6a8d7d
LJ		 1344 .owner = THIS_MODULE,
1345 .n_voltages = 1,
b080c78a 1346 .volt_table = fixed_2000000_voltage,
a4d68468 1347 .enable_time = 10000,
8e6a8d7d 1348 },
8e6a8d7d
LJ		 1349 .load_lp_uA = 1000,
1350 .update_bank = 0x03,
1351 .update_reg = 0x80,
1352 .update_mask = 0x82,
1353 .update_val = 0x02,
1354 .update_val_idle = 0x82,
1355 .update_val_normal = 0x02,
1356 },
1357 [AB9540_LDO_USB] = {
1358 .desc = {
1359 .name = "LDO-USB",
1360 .ops = &ab8500_regulator_ops,
1361 .type = REGULATOR_VOLTAGE,
1362 .id = AB9540_LDO_USB,
1363 .owner = THIS_MODULE,
1364 .n_voltages = 1,
b080c78a 1365 .volt_table = fixed_3300000_voltage,
8e6a8d7d 1366 },
8e6a8d7d
LJ		 1367 .update_bank = 0x03,
1368 .update_reg = 0x82,
1369 .update_mask = 0x03,
1370 .update_val = 0x01,
1371 .update_val_idle = 0x03,
1372 .update_val_normal = 0x01,
1373 },
1374 [AB9540_LDO_AUDIO] = {
1375 .desc = {
1376 .name = "LDO-AUDIO",
1377 .ops = &ab8500_regulator_ops,
1378 .type = REGULATOR_VOLTAGE,
0b946411 1379 .id = AB9540_LDO_AUDIO,
8e6a8d7d
LJ		 1380 .owner = THIS_MODULE,
1381 .n_voltages = 1,
b080c78a 1382 .volt_table = fixed_2000000_voltage,
8e6a8d7d 1383 },
8e6a8d7d
LJ		 1384 .update_bank = 0x03,
1385 .update_reg = 0x83,
1386 .update_mask = 0x02,
1387 .update_val = 0x02,
1388 },
1389 [AB9540_LDO_ANAMIC1] = {
1390 .desc = {
1391 .name = "LDO-ANAMIC1",
1392 .ops = &ab8500_regulator_ops,
1393 .type = REGULATOR_VOLTAGE,
0b946411 1394 .id = AB9540_LDO_ANAMIC1,
8e6a8d7d
LJ		 1395 .owner = THIS_MODULE,
1396 .n_voltages = 1,
b080c78a 1397 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1398 },
8e6a8d7d
LJ		 1399 .update_bank = 0x03,
1400 .update_reg = 0x83,
1401 .update_mask = 0x08,
1402 .update_val = 0x08,
1403 },
1404 [AB9540_LDO_ANAMIC2] = {
1405 .desc = {
1406 .name = "LDO-ANAMIC2",
1407 .ops = &ab8500_regulator_ops,
1408 .type = REGULATOR_VOLTAGE,
0b946411 1409 .id = AB9540_LDO_ANAMIC2,
8e6a8d7d
LJ		 1410 .owner = THIS_MODULE,
1411 .n_voltages = 1,
b080c78a 1412 .volt_table = fixed_2050000_voltage,
8e6a8d7d 1413 },
8e6a8d7d
LJ		 1414 .update_bank = 0x03,
1415 .update_reg = 0x83,
1416 .update_mask = 0x10,
1417 .update_val = 0x10,
1418 },
1419 [AB9540_LDO_DMIC] = {
1420 .desc = {
1421 .name = "LDO-DMIC",
1422 .ops = &ab8500_regulator_ops,
1423 .type = REGULATOR_VOLTAGE,
0b946411 1424 .id = AB9540_LDO_DMIC,
8e6a8d7d
LJ		 1425 .owner = THIS_MODULE,
1426 .n_voltages = 1,
b080c78a 1427 .volt_table = fixed_1800000_voltage,
8e6a8d7d 1428 },
8e6a8d7d
LJ		 1429 .update_bank = 0x03,
1430 .update_reg = 0x83,
1431 .update_mask = 0x04,
1432 .update_val = 0x04,
1433 },
1434
1435 /*
1436 * Regulators with fixed voltage and normal/idle modes
1437 */
1438 [AB9540_LDO_ANA] = {
1439 .desc = {
1440 .name = "LDO-ANA",
1441 .ops = &ab8500_regulator_mode_ops,
1442 .type = REGULATOR_VOLTAGE,
0b946411 1443 .id = AB9540_LDO_ANA,
8e6a8d7d
LJ		 1444 .owner = THIS_MODULE,
1445 .n_voltages = 1,
b080c78a 1446 .volt_table = fixed_1200000_voltage,
8e6a8d7d 1447 },
8e6a8d7d
LJ		 1448 .load_lp_uA = 1000,
1449 .update_bank = 0x04,
1450 .update_reg = 0x06,
1451 .update_mask = 0x0c,
1452 .update_val = 0x08,
1453 .update_val_idle = 0x0c,
1454 .update_val_normal = 0x08,
1455 },
c789ca20
SI		 1456};
1457
ae0a9a3e
LJ		 1458/* AB8540 regulator information */
1459static struct ab8500_regulator_info
1460 ab8540_regulator_info[AB8540_NUM_REGULATORS] = {
1461 /*
1462 * Variable Voltage Regulators
1463 * name, min mV, max mV,
1464 * update bank, reg, mask, enable val
d3193103 1465 * volt bank, reg, mask
ae0a9a3e
LJ		 1466 */
1467 [AB8540_LDO_AUX1] = {
1468 .desc = {
1469 .name = "LDO-AUX1",
1470 .ops = &ab8500_regulator_volt_mode_ops,
1471 .type = REGULATOR_VOLTAGE,
0b946411 1472 .id = AB8540_LDO_AUX1,
ae0a9a3e
LJ		 1473 .owner = THIS_MODULE,
1474 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1475 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1476 },
1477 .load_lp_uA = 5000,
1478 .update_bank = 0x04,
1479 .update_reg = 0x09,
1480 .update_mask = 0x03,
1481 .update_val = 0x01,
1482 .update_val_idle = 0x03,
1483 .update_val_normal = 0x01,
1484 .voltage_bank = 0x04,
1485 .voltage_reg = 0x1f,
1486 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1487 },
1488 [AB8540_LDO_AUX2] = {
1489 .desc = {
1490 .name = "LDO-AUX2",
1491 .ops = &ab8500_regulator_volt_mode_ops,
1492 .type = REGULATOR_VOLTAGE,
0b946411 1493 .id = AB8540_LDO_AUX2,
ae0a9a3e
LJ		 1494 .owner = THIS_MODULE,
1495 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1496 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1497 },
1498 .load_lp_uA = 5000,
1499 .update_bank = 0x04,
1500 .update_reg = 0x09,
1501 .update_mask = 0x0c,
1502 .update_val = 0x04,
1503 .update_val_idle = 0x0c,
1504 .update_val_normal = 0x04,
1505 .voltage_bank = 0x04,
1506 .voltage_reg = 0x20,
1507 .voltage_mask = 0x0f,
ae0a9a3e
LJ		 1508 },
1509 [AB8540_LDO_AUX3] = {
1510 .desc = {
1511 .name = "LDO-AUX3",
d7607baf 1512 .ops = &ab8540_aux3_regulator_volt_mode_ops,
ae0a9a3e 1513 .type = REGULATOR_VOLTAGE,
0b946411 1514 .id = AB8540_LDO_AUX3,
ae0a9a3e
LJ		 1515 .owner = THIS_MODULE,
1516 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
62ab4111 1517 .volt_table = ldo_vaux3_ab8540_voltages,
ae0a9a3e
LJ		 1518 },
1519 .load_lp_uA = 5000,
1520 .update_bank = 0x04,
1521 .update_reg = 0x0a,
1522 .update_mask = 0x03,
1523 .update_val = 0x01,
1524 .update_val_idle = 0x03,
1525 .update_val_normal = 0x01,
1526 .voltage_bank = 0x04,
1527 .voltage_reg = 0x21,
1528 .voltage_mask = 0x07,
d7607baf
LJ		 1529 .expand_register = {
1530 .voltage_limit = 8,
1531 .voltage_bank = 0x04,
1532 .voltage_reg = 0x01,
1533 .voltage_mask = 0x10,
d7607baf 1534 }
ae0a9a3e
LJ		 1535 },
1536 [AB8540_LDO_AUX4] = {
1537 .desc = {
1538 .name = "LDO-AUX4",
1539 .ops = &ab8500_regulator_volt_mode_ops,
1540 .type = REGULATOR_VOLTAGE,
0b946411 1541 .id = AB8540_LDO_AUX4,
ae0a9a3e
LJ		 1542 .owner = THIS_MODULE,
1543 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
62ab4111 1544 .volt_table = ldo_vauxn_voltages,
ae0a9a3e
LJ		 1545 },
1546 .load_lp_uA = 5000,
1547 /* values for Vaux4Regu register */
1548 .update_bank = 0x04,
1549 .update_reg = 0x2e,
1550 .update_mask = 0x03,
1551 .update_val = 0x01,
1552 .update_val_idle = 0x03,
1553 .update_val_normal = 0x01,
1554 /* values for Vaux4SEL register */
1555 .voltage_bank = 0x04,
1556 .voltage_reg = 0x2f,
1557 .voltage_mask = 0x0f,
ae0a9a3e 1558 },
684d5ce4
ZH		 1559 [AB8540_LDO_AUX5] = {
1560 .desc = {
1561 .name = "LDO-AUX5",
1562 .ops = &ab8500_regulator_volt_mode_ops,
1563 .type = REGULATOR_VOLTAGE,
1564 .id = AB8540_LDO_AUX5,
1565 .owner = THIS_MODULE,
1566 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
d3193103 1567 .volt_table = ldo_vaux56_ab8540_voltages,
684d5ce4
ZH		 1568 },
1569 .load_lp_uA = 20000,
1570 /* values for Vaux5Regu register */
1571 .update_bank = 0x04,
1572 .update_reg = 0x32,
1573 .update_mask = 0x03,
1574 .update_val = 0x01,
1575 .update_val_idle = 0x03,
1576 .update_val_normal = 0x01,
1577 /* values for Vaux5SEL register */
1578 .voltage_bank = 0x04,
1579 .voltage_reg = 0x33,
1580 .voltage_mask = 0x3f,
684d5ce4
ZH		 1581 },
1582 [AB8540_LDO_AUX6] = {
1583 .desc = {
1584 .name = "LDO-AUX6",
1585 .ops = &ab8500_regulator_volt_mode_ops,
1586 .type = REGULATOR_VOLTAGE,
1587 .id = AB8540_LDO_AUX6,
1588 .owner = THIS_MODULE,
1589 .n_voltages = ARRAY_SIZE(ldo_vaux56_ab8540_voltages),
d3193103 1590 .volt_table = ldo_vaux56_ab8540_voltages,
684d5ce4
ZH		 1591 },
1592 .load_lp_uA = 20000,
1593 /* values for Vaux6Regu register */
1594 .update_bank = 0x04,
1595 .update_reg = 0x35,
1596 .update_mask = 0x03,
1597 .update_val = 0x01,
1598 .update_val_idle = 0x03,
1599 .update_val_normal = 0x01,
1600 /* values for Vaux6SEL register */
1601 .voltage_bank = 0x04,
1602 .voltage_reg = 0x36,
1603 .voltage_mask = 0x3f,
684d5ce4 1604 },
ae0a9a3e
LJ		 1605 [AB8540_LDO_INTCORE] = {
1606 .desc = {
1607 .name = "LDO-INTCORE",
1608 .ops = &ab8500_regulator_volt_mode_ops,
1609 .type = REGULATOR_VOLTAGE,
0b946411 1610 .id = AB8540_LDO_INTCORE,
ae0a9a3e
LJ		 1611 .owner = THIS_MODULE,
1612 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
62ab4111 1613 .volt_table = ldo_vintcore_voltages,
ae0a9a3e
LJ		 1614 },
1615 .load_lp_uA = 5000,
1616 .update_bank = 0x03,
1617 .update_reg = 0x80,
1618 .update_mask = 0x44,
1619 .update_val = 0x44,
1620 .update_val_idle = 0x44,
1621 .update_val_normal = 0x04,
1622 .voltage_bank = 0x03,
1623 .voltage_reg = 0x80,
1624 .voltage_mask = 0x38,
ae0a9a3e
LJ		 1625 .voltage_shift = 3,
1626 },
1627
1628 /*
1629 * Fixed Voltage Regulators
1630 * name, fixed mV,
1631 * update bank, reg, mask, enable val
1632 */
1633 [AB8540_LDO_TVOUT] = {
1634 .desc = {
1635 .name = "LDO-TVOUT",
1636 .ops = &ab8500_regulator_mode_ops,
1637 .type = REGULATOR_VOLTAGE,
0b946411 1638 .id = AB8540_LDO_TVOUT,
ae0a9a3e
LJ		 1639 .owner = THIS_MODULE,
1640 .n_voltages = 1,
aca45e9e 1641 .volt_table = fixed_2000000_voltage,
a4d68468 1642 .enable_time = 10000,
ae0a9a3e 1643 },
ae0a9a3e
LJ		 1644 .load_lp_uA = 1000,
1645 .update_bank = 0x03,
1646 .update_reg = 0x80,
1647 .update_mask = 0x82,
1648 .update_val = 0x02,
1649 .update_val_idle = 0x82,
1650 .update_val_normal = 0x02,
1651 },
1652 [AB8540_LDO_AUDIO] = {
1653 .desc = {
1654 .name = "LDO-AUDIO",
1655 .ops = &ab8500_regulator_ops,
1656 .type = REGULATOR_VOLTAGE,
0b946411 1657 .id = AB8540_LDO_AUDIO,
ae0a9a3e
LJ		 1658 .owner = THIS_MODULE,
1659 .n_voltages = 1,
b080c78a 1660 .volt_table = fixed_2000000_voltage,
ae0a9a3e
LJ		 1661 },
1662 .update_bank = 0x03,
1663 .update_reg = 0x83,
1664 .update_mask = 0x02,
1665 .update_val = 0x02,
1666 },
1667 [AB8540_LDO_ANAMIC1] = {
1668 .desc = {
1669 .name = "LDO-ANAMIC1",
4c84b4dd 1670 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1671 .type = REGULATOR_VOLTAGE,
0b946411 1672 .id = AB8540_LDO_ANAMIC1,
ae0a9a3e
LJ		 1673 .owner = THIS_MODULE,
1674 .n_voltages = 1,
b080c78a 1675 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1676 },
4c84b4dd 1677 .shared_mode = &ab8540_ldo_anamic1_shared,
ae0a9a3e
LJ		 1678 .update_bank = 0x03,
1679 .update_reg = 0x83,
1680 .update_mask = 0x08,
1681 .update_val = 0x08,
4c84b4dd
LJ		 1682 .mode_bank = 0x03,
1683 .mode_reg = 0x83,
1684 .mode_mask = 0x20,
1685 .mode_val_idle = 0x20,
1686 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1687 },
1688 [AB8540_LDO_ANAMIC2] = {
1689 .desc = {
1690 .name = "LDO-ANAMIC2",
4c84b4dd 1691 .ops = &ab8500_regulator_anamic_mode_ops,
ae0a9a3e 1692 .type = REGULATOR_VOLTAGE,
0b946411 1693 .id = AB8540_LDO_ANAMIC2,
ae0a9a3e
LJ		 1694 .owner = THIS_MODULE,
1695 .n_voltages = 1,
b080c78a 1696 .volt_table = fixed_2050000_voltage,
ae0a9a3e 1697 },
4c84b4dd 1698 .shared_mode = &ab8540_ldo_anamic2_shared,
ae0a9a3e
LJ		 1699 .update_bank = 0x03,
1700 .update_reg = 0x83,
1701 .update_mask = 0x10,
1702 .update_val = 0x10,
4c84b4dd
LJ		 1703 .mode_bank = 0x03,
1704 .mode_reg = 0x83,
1705 .mode_mask = 0x20,
1706 .mode_val_idle = 0x20,
1707 .mode_val_normal = 0x00,
ae0a9a3e
LJ		 1708 },
1709 [AB8540_LDO_DMIC] = {
1710 .desc = {
1711 .name = "LDO-DMIC",
4c84b4dd 1712 .ops = &ab8500_regulator_volt_mode_ops,
ae0a9a3e 1713 .type = REGULATOR_VOLTAGE,
0b946411 1714 .id = AB8540_LDO_DMIC,
ae0a9a3e 1715 .owner = THIS_MODULE,
4c84b4dd 1716 .n_voltages = ARRAY_SIZE(ldo_vdmic_voltages),
d3193103 1717 .volt_table = ldo_vdmic_voltages,
ae0a9a3e 1718 },
4c84b4dd 1719 .load_lp_uA = 1000,
ae0a9a3e
LJ		 1720 .update_bank = 0x03,
1721 .update_reg = 0x83,
1722 .update_mask = 0x04,
1723 .update_val = 0x04,
4c84b4dd
LJ		 1724 .voltage_bank = 0x03,
1725 .voltage_reg = 0x83,
1726 .voltage_mask = 0xc0,
375dc9c1 1727 .voltage_shift = 6,
ae0a9a3e
LJ		 1728 },
1729
1730 /*
1731 * Regulators with fixed voltage and normal/idle modes
1732 */
1733 [AB8540_LDO_ANA] = {
1734 .desc = {
1735 .name = "LDO-ANA",
1736 .ops = &ab8500_regulator_mode_ops,
1737 .type = REGULATOR_VOLTAGE,
0b946411 1738 .id = AB8540_LDO_ANA,
ae0a9a3e
LJ		 1739 .owner = THIS_MODULE,
1740 .n_voltages = 1,
b080c78a 1741 .volt_table = fixed_1200000_voltage,
ae0a9a3e
LJ		 1742 },
1743 .load_lp_uA = 1000,
1744 .update_bank = 0x04,
1745 .update_reg = 0x06,
1746 .update_mask = 0x0c,
1747 .update_val = 0x04,
1748 .update_val_idle = 0x0c,
1749 .update_val_normal = 0x04,
1750 },
1751 [AB8540_LDO_SDIO] = {
1752 .desc = {
1753 .name = "LDO-SDIO",
1754 .ops = &ab8500_regulator_volt_mode_ops,
1755 .type = REGULATOR_VOLTAGE,
1756 .id = AB8540_LDO_SDIO,
1757 .owner = THIS_MODULE,
62ab4111
LJ		 1758 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages),
1759 .volt_table = ldo_sdio_voltages,
ae0a9a3e 1760 },
ae0a9a3e
LJ		 1761 .load_lp_uA = 5000,
1762 .update_bank = 0x03,
1763 .update_reg = 0x88,
1764 .update_mask = 0x30,
1765 .update_val = 0x10,
1766 .update_val_idle = 0x30,
1767 .update_val_normal = 0x10,
1768 .voltage_bank = 0x03,
1769 .voltage_reg = 0x88,
1770 .voltage_mask = 0x07,
ae0a9a3e
LJ		 1771 },
1772};
1773
3fe52289
LJ		 1774static struct ab8500_shared_mode ldo_anamic1_shared = {
1775 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2],
1776};
1777
1778static struct ab8500_shared_mode ldo_anamic2_shared = {
1779 .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1],
1780};
1781
4c84b4dd
LJ		 1782static struct ab8500_shared_mode ab8540_ldo_anamic1_shared = {
1783 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC2],
1784};
1785
1786static struct ab8500_shared_mode ab8540_ldo_anamic2_shared = {
1787 .shared_regulator = &ab8540_regulator_info[AB8540_LDO_ANAMIC1],
1788};
1789
79568b94
BJ		 1790struct ab8500_reg_init {
1791 u8 bank;
1792 u8 addr;
1793 u8 mask;
1794};
1795
1796#define REG_INIT(_id, _bank, _addr, _mask) \
1797 [_id] = { \
1798 .bank = _bank, \
1799 .addr = _addr, \
1800 .mask = _mask, \
1801 }
1802
8e6a8d7d 1803/* AB8500 register init */
79568b94
BJ		 1804static struct ab8500_reg_init ab8500_reg_init[] = {
1805 /*
33bc8f46 1806 * 0x30, VanaRequestCtrl
79568b94
BJ		 1807 * 0xc0, VextSupply1RequestCtrl
1808 */
43a5911b 1809 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
79568b94
BJ		 1810 /*
1811 * 0x03, VextSupply2RequestCtrl
1812 * 0x0c, VextSupply3RequestCtrl
1813 * 0x30, Vaux1RequestCtrl
1814 * 0xc0, Vaux2RequestCtrl
1815 */
1816 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1817 /*
1818 * 0x03, Vaux3RequestCtrl
1819 * 0x04, SwHPReq
1820 */
1821 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1822 /*
1823 * 0x08, VanaSysClkReq1HPValid
1824 * 0x20, Vaux1SysClkReq1HPValid
1825 * 0x40, Vaux2SysClkReq1HPValid
1826 * 0x80, Vaux3SysClkReq1HPValid
1827 */
43a5911b 1828 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
79568b94
BJ		 1829 /*
1830 * 0x10, VextSupply1SysClkReq1HPValid
1831 * 0x20, VextSupply2SysClkReq1HPValid
1832 * 0x40, VextSupply3SysClkReq1HPValid
1833 */
43a5911b 1834 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
79568b94
BJ		 1835 /*
1836 * 0x08, VanaHwHPReq1Valid
1837 * 0x20, Vaux1HwHPReq1Valid
1838 * 0x40, Vaux2HwHPReq1Valid
1839 * 0x80, Vaux3HwHPReq1Valid
1840 */
43a5911b 1841 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
79568b94
BJ		 1842 /*
1843 * 0x01, VextSupply1HwHPReq1Valid
1844 * 0x02, VextSupply2HwHPReq1Valid
1845 * 0x04, VextSupply3HwHPReq1Valid
1846 */
43a5911b 1847 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
79568b94
BJ		 1848 /*
1849 * 0x08, VanaHwHPReq2Valid
1850 * 0x20, Vaux1HwHPReq2Valid
1851 * 0x40, Vaux2HwHPReq2Valid
1852 * 0x80, Vaux3HwHPReq2Valid
1853 */
43a5911b 1854 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
79568b94
BJ		 1855 /*
1856 * 0x01, VextSupply1HwHPReq2Valid
1857 * 0x02, VextSupply2HwHPReq2Valid
1858 * 0x04, VextSupply3HwHPReq2Valid
1859 */
43a5911b 1860 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
79568b94
BJ		 1861 /*
1862 * 0x20, VanaSwHPReqValid
1863 * 0x80, Vaux1SwHPReqValid
1864 */
43a5911b 1865 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
79568b94
BJ		 1866 /*
1867 * 0x01, Vaux2SwHPReqValid
1868 * 0x02, Vaux3SwHPReqValid
1869 * 0x04, VextSupply1SwHPReqValid
1870 * 0x08, VextSupply2SwHPReqValid
1871 * 0x10, VextSupply3SwHPReqValid
1872 */
43a5911b 1873 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
79568b94
BJ		 1874 /*
1875 * 0x02, SysClkReq2Valid1
43a5911b
LJ		 1876 * 0x04, SysClkReq3Valid1
1877 * 0x08, SysClkReq4Valid1
1878 * 0x10, SysClkReq5Valid1
1879 * 0x20, SysClkReq6Valid1
1880 * 0x40, SysClkReq7Valid1
79568b94
BJ		 1881 * 0x80, SysClkReq8Valid1
1882 */
1883 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1884 /*
1885 * 0x02, SysClkReq2Valid2
43a5911b
LJ		 1886 * 0x04, SysClkReq3Valid2
1887 * 0x08, SysClkReq4Valid2
1888 * 0x10, SysClkReq5Valid2
1889 * 0x20, SysClkReq6Valid2
1890 * 0x40, SysClkReq7Valid2
79568b94
BJ		 1891 * 0x80, SysClkReq8Valid2
1892 */
1893 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1894 /*
1895 * 0x02, VTVoutEna
1896 * 0x04, Vintcore12Ena
1897 * 0x38, Vintcore12Sel
1898 * 0x40, Vintcore12LP
1899 * 0x80, VTVoutLP
1900 */
1901 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1902 /*
1903 * 0x02, VaudioEna
1904 * 0x04, VdmicEna
1905 * 0x08, Vamic1Ena
1906 * 0x10, Vamic2Ena
1907 */
1908 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1909 /*
1910 * 0x01, Vamic1_dzout
1911 * 0x02, Vamic2_dzout
1912 */
1913 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
d79df329 1914 /*
43a5911b 1915 * 0x03, VpllRegu (NOTE! PRCMU register bits)
33bc8f46 1916 * 0x0c, VanaRegu
79568b94
BJ		 1917 */
1918 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1919 /*
1920 * 0x01, VrefDDREna
1921 * 0x02, VrefDDRSleepMode
1922 */
1923 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1924 /*
1925 * 0x03, VextSupply1Regu
1926 * 0x0c, VextSupply2Regu
1927 * 0x30, VextSupply3Regu
1928 * 0x40, ExtSupply2Bypass
1929 * 0x80, ExtSupply3Bypass
1930 */
1931 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1932 /*
1933 * 0x03, Vaux1Regu
1934 * 0x0c, Vaux2Regu
1935 */
1936 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1937 /*
1938 * 0x03, Vaux3Regu
1939 */
43a5911b 1940 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
79568b94
BJ		 1941 /*
1942 * 0x0f, Vaux1Sel
1943 */
1944 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1945 /*
1946 * 0x0f, Vaux2Sel
1947 */
1948 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1949 /*
1950 * 0x07, Vaux3Sel
1951 */
43a5911b 1952 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
79568b94
BJ		 1953 /*
1954 * 0x01, VextSupply12LP
1955 */
1956 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1957 /*
1958 * 0x04, Vaux1Disch
1959 * 0x08, Vaux2Disch
1960 * 0x10, Vaux3Disch
1961 * 0x20, Vintcore12Disch
1962 * 0x40, VTVoutDisch
1963 * 0x80, VaudioDisch
1964 */
43a5911b 1965 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
79568b94
BJ		 1966 /*
1967 * 0x02, VanaDisch
1968 * 0x04, VdmicPullDownEna
1969 * 0x10, VdmicDisch
1970 */
43a5911b 1971 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
79568b94
BJ		 1972};
1973
547f384f
LJ		 1974/* AB8505 register init */
1975static struct ab8500_reg_init ab8505_reg_init[] = {
1976 /*
1977 * 0x03, VarmRequestCtrl
1978 * 0x0c, VsmpsCRequestCtrl
1979 * 0x30, VsmpsARequestCtrl
1980 * 0xc0, VsmpsBRequestCtrl
1981 */
1982 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1983 /*
1984 * 0x03, VsafeRequestCtrl
1985 * 0x0c, VpllRequestCtrl
1986 * 0x30, VanaRequestCtrl
1987 */
1988 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
1989 /*
1990 * 0x30, Vaux1RequestCtrl
1991 * 0xc0, Vaux2RequestCtrl
1992 */
1993 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
1994 /*
1995 * 0x03, Vaux3RequestCtrl
1996 * 0x04, SwHPReq
1997 */
1998 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1999 /*
2000 * 0x01, VsmpsASysClkReq1HPValid
2001 * 0x02, VsmpsBSysClkReq1HPValid
2002 * 0x04, VsafeSysClkReq1HPValid
2003 * 0x08, VanaSysClkReq1HPValid
2004 * 0x10, VpllSysClkReq1HPValid
2005 * 0x20, Vaux1SysClkReq1HPValid
2006 * 0x40, Vaux2SysClkReq1HPValid
2007 * 0x80, Vaux3SysClkReq1HPValid
2008 */
2009 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2010 /*
2011 * 0x01, VsmpsCSysClkReq1HPValid
2012 * 0x02, VarmSysClkReq1HPValid
2013 * 0x04, VbbSysClkReq1HPValid
2014 * 0x08, VsmpsMSysClkReq1HPValid
2015 */
2016 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
2017 /*
2018 * 0x01, VsmpsAHwHPReq1Valid
2019 * 0x02, VsmpsBHwHPReq1Valid
2020 * 0x04, VsafeHwHPReq1Valid
2021 * 0x08, VanaHwHPReq1Valid
2022 * 0x10, VpllHwHPReq1Valid
2023 * 0x20, Vaux1HwHPReq1Valid
2024 * 0x40, Vaux2HwHPReq1Valid
2025 * 0x80, Vaux3HwHPReq1Valid
2026 */
2027 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2028 /*
2029 * 0x08, VsmpsMHwHPReq1Valid
2030 */
2031 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
2032 /*
2033 * 0x01, VsmpsAHwHPReq2Valid
2034 * 0x02, VsmpsBHwHPReq2Valid
2035 * 0x04, VsafeHwHPReq2Valid
2036 * 0x08, VanaHwHPReq2Valid
2037 * 0x10, VpllHwHPReq2Valid
2038 * 0x20, Vaux1HwHPReq2Valid
2039 * 0x40, Vaux2HwHPReq2Valid
2040 * 0x80, Vaux3HwHPReq2Valid
2041 */
2042 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2043 /*
2044 * 0x08, VsmpsMHwHPReq2Valid
2045 */
2046 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
2047 /*
2048 * 0x01, VsmpsCSwHPReqValid
2049 * 0x02, VarmSwHPReqValid
2050 * 0x04, VsmpsASwHPReqValid
2051 * 0x08, VsmpsBSwHPReqValid
2052 * 0x10, VsafeSwHPReqValid
2053 * 0x20, VanaSwHPReqValid
2054 * 0x40, VpllSwHPReqValid
2055 * 0x80, Vaux1SwHPReqValid
2056 */
2057 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2058 /*
2059 * 0x01, Vaux2SwHPReqValid
2060 * 0x02, Vaux3SwHPReqValid
2061 * 0x20, VsmpsMSwHPReqValid
2062 */
2063 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
2064 /*
2065 * 0x02, SysClkReq2Valid1
2066 * 0x04, SysClkReq3Valid1
2067 * 0x08, SysClkReq4Valid1
2068 */
2069 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
2070 /*
2071 * 0x02, SysClkReq2Valid2
2072 * 0x04, SysClkReq3Valid2
2073 * 0x08, SysClkReq4Valid2
2074 */
2075 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
2076 /*
2077 * 0x01, Vaux4SwHPReqValid
2078 * 0x02, Vaux4HwHPReq2Valid
2079 * 0x04, Vaux4HwHPReq1Valid
2080 * 0x08, Vaux4SysClkReq1HPValid
2081 */
2082 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2083 /*
2084 * 0x02, VadcEna
2085 * 0x04, VintCore12Ena
2086 * 0x38, VintCore12Sel
2087 * 0x40, VintCore12LP
2088 * 0x80, VadcLP
2089 */
2090 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
2091 /*
2092 * 0x02, VaudioEna
2093 * 0x04, VdmicEna
2094 * 0x08, Vamic1Ena
2095 * 0x10, Vamic2Ena
2096 */
2097 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2098 /*
2099 * 0x01, Vamic1_dzout
2100 * 0x02, Vamic2_dzout
2101 */
2102 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2103 /*
2104 * 0x03, VsmpsARegu
2105 * 0x0c, VsmpsASelCtrl
2106 * 0x10, VsmpsAAutoMode
2107 * 0x20, VsmpsAPWMMode
2108 */
2109 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
2110 /*
2111 * 0x03, VsmpsBRegu
2112 * 0x0c, VsmpsBSelCtrl
2113 * 0x10, VsmpsBAutoMode
2114 * 0x20, VsmpsBPWMMode
2115 */
2116 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
2117 /*
2118 * 0x03, VsafeRegu
2119 * 0x0c, VsafeSelCtrl
2120 * 0x10, VsafeAutoMode
2121 * 0x20, VsafePWMMode
2122 */
2123 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
2124 /*
2125 * 0x03, VpllRegu (NOTE! PRCMU register bits)
2126 * 0x0c, VanaRegu
2127 */
2128 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2129 /*
2130 * 0x03, VextSupply1Regu
2131 * 0x0c, VextSupply2Regu
2132 * 0x30, VextSupply3Regu
2133 * 0x40, ExtSupply2Bypass
2134 * 0x80, ExtSupply3Bypass
2135 */
2136 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2137 /*
2138 * 0x03, Vaux1Regu
2139 * 0x0c, Vaux2Regu
2140 */
2141 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
2142 /*
2143 * 0x0f, Vaux3Regu
2144 */
2145 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2146 /*
2147 * 0x3f, VsmpsASel1
2148 */
2149 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
2150 /*
2151 * 0x3f, VsmpsASel2
2152 */
2153 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
2154 /*
2155 * 0x3f, VsmpsASel3
2156 */
2157 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
2158 /*
2159 * 0x3f, VsmpsBSel1
2160 */
2161 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
2162 /*
2163 * 0x3f, VsmpsBSel2
2164 */
2165 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
2166 /*
2167 * 0x3f, VsmpsBSel3
2168 */
2169 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
2170 /*
2171 * 0x7f, VsafeSel1
2172 */
2173 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
2174 /*
2175 * 0x3f, VsafeSel2
2176 */
2177 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
2178 /*
2179 * 0x3f, VsafeSel3
2180 */
2181 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
2182 /*
2183 * 0x0f, Vaux1Sel
2184 */
2185 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
2186 /*
2187 * 0x0f, Vaux2Sel
2188 */
2189 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
2190 /*
2191 * 0x07, Vaux3Sel
2192 * 0x30, VRF1Sel
2193 */
2194 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2195 /*
2196 * 0x03, Vaux4RequestCtrl
2197 */
2198 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2199 /*
2200 * 0x03, Vaux4Regu
2201 */
2202 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
2203 /*
2204 * 0x0f, Vaux4Sel
2205 */
2206 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
2207 /*
2208 * 0x04, Vaux1Disch
2209 * 0x08, Vaux2Disch
2210 * 0x10, Vaux3Disch
2211 * 0x20, Vintcore12Disch
2212 * 0x40, VTVoutDisch
2213 * 0x80, VaudioDisch
2214 */
2215 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
2216 /*
2217 * 0x02, VanaDisch
2218 * 0x04, VdmicPullDownEna
2219 * 0x10, VdmicDisch
2220 */
2221 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
2222 /*
2223 * 0x01, Vaux4Disch
2224 */
2225 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2226 /*
2227 * 0x07, Vaux5Sel
2228 * 0x08, Vaux5LP
2229 * 0x10, Vaux5Ena
2230 * 0x20, Vaux5Disch
2231 * 0x40, Vaux5DisSfst
2232 * 0x80, Vaux5DisPulld
2233 */
2234 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
2235 /*
2236 * 0x07, Vaux6Sel
2237 * 0x08, Vaux6LP
2238 * 0x10, Vaux6Ena
2239 * 0x80, Vaux6DisPulld
2240 */
2241 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
2242};
2243
8e6a8d7d
LJ		 2244/* AB9540 register init */
2245static struct ab8500_reg_init ab9540_reg_init[] = {
2246 /*
2247 * 0x03, VarmRequestCtrl
2248 * 0x0c, VapeRequestCtrl
2249 * 0x30, Vsmps1RequestCtrl
2250 * 0xc0, Vsmps2RequestCtrl
2251 */
2252 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2253 /*
2254 * 0x03, Vsmps3RequestCtrl
2255 * 0x0c, VpllRequestCtrl
2256 * 0x30, VanaRequestCtrl
2257 * 0xc0, VextSupply1RequestCtrl
2258 */
2259 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2260 /*
2261 * 0x03, VextSupply2RequestCtrl
2262 * 0x0c, VextSupply3RequestCtrl
2263 * 0x30, Vaux1RequestCtrl
2264 * 0xc0, Vaux2RequestCtrl
2265 */
2266 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2267 /*
2268 * 0x03, Vaux3RequestCtrl
2269 * 0x04, SwHPReq
2270 */
2271 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2272 /*
2273 * 0x01, Vsmps1SysClkReq1HPValid
2274 * 0x02, Vsmps2SysClkReq1HPValid
2275 * 0x04, Vsmps3SysClkReq1HPValid
2276 * 0x08, VanaSysClkReq1HPValid
2277 * 0x10, VpllSysClkReq1HPValid
2278 * 0x20, Vaux1SysClkReq1HPValid
2279 * 0x40, Vaux2SysClkReq1HPValid
2280 * 0x80, Vaux3SysClkReq1HPValid
2281 */
2282 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2283 /*
2284 * 0x01, VapeSysClkReq1HPValid
2285 * 0x02, VarmSysClkReq1HPValid
2286 * 0x04, VbbSysClkReq1HPValid
2287 * 0x08, VmodSysClkReq1HPValid
2288 * 0x10, VextSupply1SysClkReq1HPValid
2289 * 0x20, VextSupply2SysClkReq1HPValid
2290 * 0x40, VextSupply3SysClkReq1HPValid
2291 */
2292 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
2293 /*
2294 * 0x01, Vsmps1HwHPReq1Valid
2295 * 0x02, Vsmps2HwHPReq1Valid
2296 * 0x04, Vsmps3HwHPReq1Valid
2297 * 0x08, VanaHwHPReq1Valid
2298 * 0x10, VpllHwHPReq1Valid
2299 * 0x20, Vaux1HwHPReq1Valid
2300 * 0x40, Vaux2HwHPReq1Valid
2301 * 0x80, Vaux3HwHPReq1Valid
2302 */
2303 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2304 /*
2305 * 0x01, VextSupply1HwHPReq1Valid
2306 * 0x02, VextSupply2HwHPReq1Valid
2307 * 0x04, VextSupply3HwHPReq1Valid
2308 * 0x08, VmodHwHPReq1Valid
2309 */
2310 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
2311 /*
2312 * 0x01, Vsmps1HwHPReq2Valid
2313 * 0x02, Vsmps2HwHPReq2Valid
2314 * 0x03, Vsmps3HwHPReq2Valid
2315 * 0x08, VanaHwHPReq2Valid
2316 * 0x10, VpllHwHPReq2Valid
2317 * 0x20, Vaux1HwHPReq2Valid
2318 * 0x40, Vaux2HwHPReq2Valid
2319 * 0x80, Vaux3HwHPReq2Valid
2320 */
2321 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2322 /*
2323 * 0x01, VextSupply1HwHPReq2Valid
2324 * 0x02, VextSupply2HwHPReq2Valid
2325 * 0x04, VextSupply3HwHPReq2Valid
2326 * 0x08, VmodHwHPReq2Valid
2327 */
2328 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
2329 /*
2330 * 0x01, VapeSwHPReqValid
2331 * 0x02, VarmSwHPReqValid
2332 * 0x04, Vsmps1SwHPReqValid
2333 * 0x08, Vsmps2SwHPReqValid
2334 * 0x10, Vsmps3SwHPReqValid
2335 * 0x20, VanaSwHPReqValid
2336 * 0x40, VpllSwHPReqValid
2337 * 0x80, Vaux1SwHPReqValid
2338 */
2339 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2340 /*
2341 * 0x01, Vaux2SwHPReqValid
2342 * 0x02, Vaux3SwHPReqValid
2343 * 0x04, VextSupply1SwHPReqValid
2344 * 0x08, VextSupply2SwHPReqValid
2345 * 0x10, VextSupply3SwHPReqValid
2346 * 0x20, VmodSwHPReqValid
2347 */
2348 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
2349 /*
2350 * 0x02, SysClkReq2Valid1
2351 * ...
2352 * 0x80, SysClkReq8Valid1
2353 */
2354 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
2355 /*
2356 * 0x02, SysClkReq2Valid2
2357 * ...
2358 * 0x80, SysClkReq8Valid2
2359 */
2360 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
2361 /*
2362 * 0x01, Vaux4SwHPReqValid
2363 * 0x02, Vaux4HwHPReq2Valid
2364 * 0x04, Vaux4HwHPReq1Valid
2365 * 0x08, Vaux4SysClkReq1HPValid
2366 */
2367 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2368 /*
2369 * 0x02, VTVoutEna
2370 * 0x04, Vintcore12Ena
2371 * 0x38, Vintcore12Sel
2372 * 0x40, Vintcore12LP
2373 * 0x80, VTVoutLP
2374 */
2375 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
2376 /*
2377 * 0x02, VaudioEna
2378 * 0x04, VdmicEna
2379 * 0x08, Vamic1Ena
2380 * 0x10, Vamic2Ena
2381 */
2382 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2383 /*
2384 * 0x01, Vamic1_dzout
2385 * 0x02, Vamic2_dzout
2386 */
2387 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2388 /*
2389 * 0x03, Vsmps1Regu
2390 * 0x0c, Vsmps1SelCtrl
2391 * 0x10, Vsmps1AutoMode
2392 * 0x20, Vsmps1PWMMode
2393 */
2394 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2395 /*
2396 * 0x03, Vsmps2Regu
2397 * 0x0c, Vsmps2SelCtrl
2398 * 0x10, Vsmps2AutoMode
2399 * 0x20, Vsmps2PWMMode
2400 */
2401 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2402 /*
2403 * 0x03, Vsmps3Regu
2404 * 0x0c, Vsmps3SelCtrl
2405 * NOTE! PRCMU register
2406 */
2407 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2408 /*
2409 * 0x03, VpllRegu
2410 * 0x0c, VanaRegu
2411 */
2412 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2413 /*
2414 * 0x03, VextSupply1Regu
2415 * 0x0c, VextSupply2Regu
2416 * 0x30, VextSupply3Regu
2417 * 0x40, ExtSupply2Bypass
2418 * 0x80, ExtSupply3Bypass
2419 */
2420 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2421 /*
2422 * 0x03, Vaux1Regu
2423 * 0x0c, Vaux2Regu
2424 */
2425 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
2426 /*
2427 * 0x0c, Vrf1Regu
2428 * 0x03, Vaux3Regu
2429 */
2430 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2431 /*
2432 * 0x3f, Vsmps1Sel1
2433 */
2434 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2435 /*
2436 * 0x3f, Vsmps1Sel2
2437 */
2438 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2439 /*
2440 * 0x3f, Vsmps1Sel3
2441 */
2442 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2443 /*
2444 * 0x3f, Vsmps2Sel1
2445 */
2446 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2447 /*
2448 * 0x3f, Vsmps2Sel2
2449 */
2450 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2451 /*
2452 * 0x3f, Vsmps2Sel3
2453 */
2454 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2455 /*
2456 * 0x7f, Vsmps3Sel1
2457 * NOTE! PRCMU register
2458 */
2459 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2460 /*
2461 * 0x7f, Vsmps3Sel2
2462 * NOTE! PRCMU register
2463 */
2464 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2465 /*
2466 * 0x0f, Vaux1Sel
2467 */
2468 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2469 /*
2470 * 0x0f, Vaux2Sel
2471 */
2472 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
2473 /*
2474 * 0x07, Vaux3Sel
2475 * 0x30, Vrf1Sel
2476 */
2477 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2478 /*
2479 * 0x01, VextSupply12LP
2480 */
2481 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2482 /*
2483 * 0x03, Vaux4RequestCtrl
2484 */
2485 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2486 /*
2487 * 0x03, Vaux4Regu
2488 */
2489 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
2490 /*
2491 * 0x08, Vaux4Sel
2492 */
2493 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2494 /*
2495 * 0x01, VpllDisch
2496 * 0x02, Vrf1Disch
2497 * 0x04, Vaux1Disch
2498 * 0x08, Vaux2Disch
2499 * 0x10, Vaux3Disch
2500 * 0x20, Vintcore12Disch
2501 * 0x40, VTVoutDisch
2502 * 0x80, VaudioDisch
2503 */
2504 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2505 /*
2506 * 0x01, VsimDisch
2507 * 0x02, VanaDisch
2508 * 0x04, VdmicPullDownEna
2509 * 0x08, VpllPullDownEna
2510 * 0x10, VdmicDisch
2511 */
2512 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
2513 /*
2514 * 0x01, Vaux4Disch
2515 */
2516 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2517};
2518
ae0a9a3e
LJ		 2519/* AB8540 register init */
2520static struct ab8500_reg_init ab8540_reg_init[] = {
2521 /*
2522 * 0x01, VSimSycClkReq1Valid
2523 * 0x02, VSimSycClkReq2Valid
2524 * 0x04, VSimSycClkReq3Valid
2525 * 0x08, VSimSycClkReq4Valid
2526 * 0x10, VSimSycClkReq5Valid
2527 * 0x20, VSimSycClkReq6Valid
2528 * 0x40, VSimSycClkReq7Valid
2529 * 0x80, VSimSycClkReq8Valid
2530 */
2531 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff),
2532 /*
2533 * 0x03, VarmRequestCtrl
2534 * 0x0c, VapeRequestCtrl
2535 * 0x30, Vsmps1RequestCtrl
2536 * 0xc0, Vsmps2RequestCtrl
2537 */
2538 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2539 /*
2540 * 0x03, Vsmps3RequestCtrl
2541 * 0x0c, VpllRequestCtrl
2542 * 0x30, VanaRequestCtrl
2543 * 0xc0, VextSupply1RequestCtrl
2544 */
2545 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2546 /*
2547 * 0x03, VextSupply2RequestCtrl
2548 * 0x0c, VextSupply3RequestCtrl
2549 * 0x30, Vaux1RequestCtrl
2550 * 0xc0, Vaux2RequestCtrl
2551 */
2552 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2553 /*
2554 * 0x03, Vaux3RequestCtrl
2555 * 0x04, SwHPReq
2556 */
2557 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2558 /*
2559 * 0x01, Vsmps1SysClkReq1HPValid
2560 * 0x02, Vsmps2SysClkReq1HPValid
2561 * 0x04, Vsmps3SysClkReq1HPValid
2562 * 0x08, VanaSysClkReq1HPValid
2563 * 0x10, VpllSysClkReq1HPValid
2564 * 0x20, Vaux1SysClkReq1HPValid
2565 * 0x40, Vaux2SysClkReq1HPValid
2566 * 0x80, Vaux3SysClkReq1HPValid
2567 */
2568 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2569 /*
2570 * 0x01, VapeSysClkReq1HPValid
2571 * 0x02, VarmSysClkReq1HPValid
2572 * 0x04, VbbSysClkReq1HPValid
2573 * 0x10, VextSupply1SysClkReq1HPValid
2574 * 0x20, VextSupply2SysClkReq1HPValid
2575 * 0x40, VextSupply3SysClkReq1HPValid
2576 */
2577 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77),
2578 /*
2579 * 0x01, Vsmps1HwHPReq1Valid
2580 * 0x02, Vsmps2HwHPReq1Valid
2581 * 0x04, Vsmps3HwHPReq1Valid
2582 * 0x08, VanaHwHPReq1Valid
2583 * 0x10, VpllHwHPReq1Valid
2584 * 0x20, Vaux1HwHPReq1Valid
2585 * 0x40, Vaux2HwHPReq1Valid
2586 * 0x80, Vaux3HwHPReq1Valid
2587 */
2588 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2589 /*
2590 * 0x01, VextSupply1HwHPReq1Valid
2591 * 0x02, VextSupply2HwHPReq1Valid
2592 * 0x04, VextSupply3HwHPReq1Valid
2593 */
2594 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
2595 /*
2596 * 0x01, Vsmps1HwHPReq2Valid
2597 * 0x02, Vsmps2HwHPReq2Valid
2598 * 0x03, Vsmps3HwHPReq2Valid
2599 * 0x08, VanaHwHPReq2Valid
2600 * 0x10, VpllHwHPReq2Valid
2601 * 0x20, Vaux1HwHPReq2Valid
2602 * 0x40, Vaux2HwHPReq2Valid
2603 * 0x80, Vaux3HwHPReq2Valid
2604 */
2605 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2606 /*
2607 * 0x01, VextSupply1HwHPReq2Valid
2608 * 0x02, VextSupply2HwHPReq2Valid
2609 * 0x04, VextSupply3HwHPReq2Valid
2610 */
2611 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
2612 /*
2613 * 0x01, VapeSwHPReqValid
2614 * 0x02, VarmSwHPReqValid
2615 * 0x04, Vsmps1SwHPReqValid
2616 * 0x08, Vsmps2SwHPReqValid
2617 * 0x10, Vsmps3SwHPReqValid
2618 * 0x20, VanaSwHPReqValid
2619 * 0x40, VpllSwHPReqValid
2620 * 0x80, Vaux1SwHPReqValid
2621 */
2622 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2623 /*
2624 * 0x01, Vaux2SwHPReqValid
2625 * 0x02, Vaux3SwHPReqValid
2626 * 0x04, VextSupply1SwHPReqValid
2627 * 0x08, VextSupply2SwHPReqValid
2628 * 0x10, VextSupply3SwHPReqValid
2629 */
2630 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
2631 /*
2632 * 0x02, SysClkReq2Valid1
2633 * ...
2634 * 0x80, SysClkReq8Valid1
2635 */
2636 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff),
2637 /*
2638 * 0x02, SysClkReq2Valid2
2639 * ...
2640 * 0x80, SysClkReq8Valid2
2641 */
2642 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff),
2643 /*
2644 * 0x01, Vaux4SwHPReqValid
2645 * 0x02, Vaux4HwHPReq2Valid
2646 * 0x04, Vaux4HwHPReq1Valid
2647 * 0x08, Vaux4SysClkReq1HPValid
2648 */
2649 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2650 /*
2651 * 0x01, Vaux5SwHPReqValid
2652 * 0x02, Vaux5HwHPReq2Valid
2653 * 0x04, Vaux5HwHPReq1Valid
2654 * 0x08, Vaux5SysClkReq1HPValid
2655 */
2656 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f),
2657 /*
2658 * 0x01, Vaux6SwHPReqValid
2659 * 0x02, Vaux6HwHPReq2Valid
2660 * 0x04, Vaux6HwHPReq1Valid
2661 * 0x08, Vaux6SysClkReq1HPValid
2662 */
2663 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f),
2664 /*
2665 * 0x01, VclkbSwHPReqValid
2666 * 0x02, VclkbHwHPReq2Valid
2667 * 0x04, VclkbHwHPReq1Valid
2668 * 0x08, VclkbSysClkReq1HPValid
2669 */
2670 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f),
2671 /*
2672 * 0x01, Vrf1SwHPReqValid
2673 * 0x02, Vrf1HwHPReq2Valid
2674 * 0x04, Vrf1HwHPReq1Valid
2675 * 0x08, Vrf1SysClkReq1HPValid
2676 */
2677 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f),
2678 /*
2679 * 0x02, VTVoutEna
2680 * 0x04, Vintcore12Ena
2681 * 0x38, Vintcore12Sel
2682 * 0x40, Vintcore12LP
2683 * 0x80, VTVoutLP
2684 */
2685 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe),
2686 /*
2687 * 0x02, VaudioEna
2688 * 0x04, VdmicEna
2689 * 0x08, Vamic1Ena
2690 * 0x10, Vamic2Ena
2691 * 0x20, Vamic12LP
2692 * 0xC0, VdmicSel
2693 */
2694 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe),
2695 /*
2696 * 0x01, Vamic1_dzout
2697 * 0x02, Vamic2_dzout
2698 */
2699 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2700 /*
2701 * 0x07, VHSICSel
2702 * 0x08, VHSICOffState
2703 * 0x10, VHSIEna
2704 * 0x20, VHSICLP
2705 */
2706 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f),
2707 /*
2708 * 0x07, VSDIOSel
2709 * 0x08, VSDIOOffState
2710 * 0x10, VSDIOEna
2711 * 0x20, VSDIOLP
2712 */
2713 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f),
2714 /*
2715 * 0x03, Vsmps1Regu
2716 * 0x0c, Vsmps1SelCtrl
2717 * 0x10, Vsmps1AutoMode
2718 * 0x20, Vsmps1PWMMode
2719 */
2720 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2721 /*
2722 * 0x03, Vsmps2Regu
2723 * 0x0c, Vsmps2SelCtrl
2724 * 0x10, Vsmps2AutoMode
2725 * 0x20, Vsmps2PWMMode
2726 */
2727 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2728 /*
2729 * 0x03, Vsmps3Regu
2730 * 0x0c, Vsmps3SelCtrl
2731 * 0x10, Vsmps3AutoMode
2732 * 0x20, Vsmps3PWMMode
2733 * NOTE! PRCMU register
2734 */
2735 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2736 /*
2737 * 0x03, VpllRegu
2738 * 0x0c, VanaRegu
2739 */
2740 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2741 /*
2742 * 0x03, VextSupply1Regu
2743 * 0x0c, VextSupply2Regu
2744 * 0x30, VextSupply3Regu
2745 * 0x40, ExtSupply2Bypass
2746 * 0x80, ExtSupply3Bypass
2747 */
2748 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2749 /*
2750 * 0x03, Vaux1Regu
2751 * 0x0c, Vaux2Regu
2752 */
2753 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f),
2754 /*
2755 * 0x0c, VRF1Regu
2756 * 0x03, Vaux3Regu
2757 */
2758 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2759 /*
2760 * 0x3f, Vsmps1Sel1
2761 */
2762 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2763 /*
2764 * 0x3f, Vsmps1Sel2
2765 */
2766 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2767 /*
2768 * 0x3f, Vsmps1Sel3
2769 */
2770 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2771 /*
2772 * 0x3f, Vsmps2Sel1
2773 */
2774 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2775 /*
2776 * 0x3f, Vsmps2Sel2
2777 */
2778 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2779 /*
2780 * 0x3f, Vsmps2Sel3
2781 */
2782 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2783 /*
2784 * 0x7f, Vsmps3Sel1
2785 * NOTE! PRCMU register
2786 */
2787 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2788 /*
2789 * 0x7f, Vsmps3Sel2
2790 * NOTE! PRCMU register
2791 */
2792 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2793 /*
2794 * 0x0f, Vaux1Sel
2795 */
2796 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2797 /*
2798 * 0x0f, Vaux2Sel
2799 */
2800 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f),
2801 /*
2802 * 0x07, Vaux3Sel
2803 * 0x70, Vrf1Sel
2804 */
2805 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77),
2806 /*
2807 * 0x01, VextSupply12LP
2808 */
2809 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2810 /*
2811 * 0x07, Vanasel
2812 * 0x30, Vpllsel
2813 */
2814 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37),
2815 /*
2816 * 0x03, Vaux4RequestCtrl
2817 */
2818 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2819 /*
2820 * 0x03, Vaux4Regu
2821 */
2822 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03),
2823 /*
2824 * 0x0f, Vaux4Sel
2825 */
2826 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2827 /*
2828 * 0x03, Vaux5RequestCtrl
2829 */
2830 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03),
2831 /*
2832 * 0x03, Vaux5Regu
2833 */
2834 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03),
2835 /*
2836 * 0x3f, Vaux5Sel
2837 */
2838 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f),
2839 /*
2840 * 0x03, Vaux6RequestCtrl
2841 */
2842 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03),
2843 /*
2844 * 0x03, Vaux6Regu
2845 */
2846 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03),
2847 /*
2848 * 0x3f, Vaux6Sel
2849 */
2850 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f),
2851 /*
2852 * 0x03, VCLKBRequestCtrl
2853 */
2854 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03),
2855 /*
2856 * 0x03, VCLKBRegu
2857 */
2858 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03),
2859 /*
2860 * 0x07, VCLKBSel
2861 */
2862 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07),
2863 /*
2864 * 0x03, Vrf1RequestCtrl
2865 */
2866 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03),
2867 /*
2868 * 0x01, VpllDisch
2869 * 0x02, Vrf1Disch
2870 * 0x04, Vaux1Disch
2871 * 0x08, Vaux2Disch
2872 * 0x10, Vaux3Disch
2873 * 0x20, Vintcore12Disch
2874 * 0x40, VTVoutDisch
2875 * 0x80, VaudioDisch
2876 */
2877 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2878 /*
2879 * 0x02, VanaDisch
2880 * 0x04, VdmicPullDownEna
2881 * 0x08, VpllPullDownEna
2882 * 0x10, VdmicDisch
2883 */
2884 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e),
2885 /*
2886 * 0x01, Vaux4Disch
2887 */
2888 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2889 /*
2890 * 0x01, Vaux5Disch
2891 * 0x02, Vaux6Disch
2892 * 0x04, VCLKBDisch
2893 */
2894 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07),
2895};
2896
b54969ac 2897static struct of_regulator_match ab8500_regulator_match[] = {
7e715b95
LJ		 2898 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
2899 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
2900 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
2901 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
2902 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
7e715b95
LJ		 2903 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
2904 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
2905 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
2906 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
2907 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
3a8334b9
LJ		 2908};
2909
547f384f
LJ		 2910static struct of_regulator_match ab8505_regulator_match[] = {
2911 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
2912 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
2913 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
2914 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
2915 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
2916 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
2917 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
2918 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
2919 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
2920 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
2921 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
2922 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
2923 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
2924};
2925
ae0a9a3e
LJ		 2926static struct of_regulator_match ab8540_regulator_match[] = {
2927 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, },
2928 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, },
2929 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, },
2930 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, },
684d5ce4
ZH		 2931 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8540_LDO_AUX5, },
2932 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8540_LDO_AUX6, },
ae0a9a3e
LJ		 2933 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, },
2934 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, },
2935 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, },
2936 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
2937 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
2938 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, },
2939 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, },
2940 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, },
2941};
2942
8e6a8d7d
LJ		 2943static struct of_regulator_match ab9540_regulator_match[] = {
2944 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
2945 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
2946 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
2947 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
2948 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
2949 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
2950 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
2951 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
2952 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
2953 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
2954 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
2955};
2956
da45edc7
LJ		 2957static struct {
2958 struct ab8500_regulator_info *info;
2959 int info_size;
2960 struct ab8500_reg_init *init;
2961 int init_size;
2962 struct of_regulator_match *match;
2963 int match_size;
2964} abx500_regulator;
2965
33aeb49e
LJ		 2966static void abx500_get_regulator_info(struct ab8500 *ab8500)
2967{
2968 if (is_ab9540(ab8500)) {
2969 abx500_regulator.info = ab9540_regulator_info;
2970 abx500_regulator.info_size = ARRAY_SIZE(ab9540_regulator_info);
2971 abx500_regulator.init = ab9540_reg_init;
2972 abx500_regulator.init_size = AB9540_NUM_REGULATOR_REGISTERS;
2973 abx500_regulator.match = ab9540_regulator_match;
2974 abx500_regulator.match_size = ARRAY_SIZE(ab9540_regulator_match);
2975 } else if (is_ab8505(ab8500)) {
2976 abx500_regulator.info = ab8505_regulator_info;
2977 abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info);
2978 abx500_regulator.init = ab8505_reg_init;
2979 abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS;
2980 abx500_regulator.match = ab8505_regulator_match;
2981 abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match);
2982 } else if (is_ab8540(ab8500)) {
2983 abx500_regulator.info = ab8540_regulator_info;
2984 abx500_regulator.info_size = ARRAY_SIZE(ab8540_regulator_info);
2985 abx500_regulator.init = ab8540_reg_init;
2986 abx500_regulator.init_size = AB8540_NUM_REGULATOR_REGISTERS;
2987 abx500_regulator.match = ab8540_regulator_match;
2988 abx500_regulator.match_size = ARRAY_SIZE(ab8540_regulator_match);
2989 } else {
2990 abx500_regulator.info = ab8500_regulator_info;
2991 abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info);
2992 abx500_regulator.init = ab8500_reg_init;
2993 abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS;
2994 abx500_regulator.match = ab8500_regulator_match;
2995 abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match);
2996 }
2997}
2998
da45edc7
LJ		 2999static int ab8500_regulator_init_registers(struct platform_device *pdev,
3000 int id, int mask, int value)
3001{
3002 struct ab8500_reg_init *reg_init = abx500_regulator.init;
3003 int err;
3004
3005 BUG_ON(value & ~mask);
3006 BUG_ON(mask & ~reg_init[id].mask);
3007
3008 /* initialize register */
3009 err = abx500_mask_and_set_register_interruptible(
3010 &pdev->dev,
3011 reg_init[id].bank,
3012 reg_init[id].addr,
3013 mask, value);
3014 if (err < 0) {
3015 dev_err(&pdev->dev,
3016 "Failed to initialize 0x%02x, 0x%02x.\n",
3017 reg_init[id].bank,
3018 reg_init[id].addr);
3019 return err;
3020 }
3021 dev_vdbg(&pdev->dev,
3022 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
3023 reg_init[id].bank,
3024 reg_init[id].addr,
3025 mask, value);
3026
3027 return 0;
3028}
3029
3030static int ab8500_regulator_register(struct platform_device *pdev,
3031 struct regulator_init_data *init_data,
3032 int id, struct device_node *np)
3033{
3034 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3035 struct ab8500_regulator_info *info = NULL;
3036 struct regulator_config config = { };
3037 int err;
3038
3039 /* assign per-regulator data */
3040 info = &abx500_regulator.info[id];
3041 info->dev = &pdev->dev;
3042
3043 config.dev = &pdev->dev;
3044 config.init_data = init_data;
3045 config.driver_data = info;
3046 config.of_node = np;
3047
3048 /* fix for hardware before ab8500v2.0 */
3049 if (is_ab8500_1p1_or_earlier(ab8500)) {
3050 if (info->desc.id == AB8500_LDO_AUX3) {
3051 info->desc.n_voltages =
3052 ARRAY_SIZE(ldo_vauxn_voltages);
3053 info->desc.volt_table = ldo_vauxn_voltages;
3054 info->voltage_mask = 0xf;
3055 }
3056 }
3057
3058 /* register regulator with framework */
3059 info->regulator = regulator_register(&info->desc, &config);
3060 if (IS_ERR(info->regulator)) {
3061 err = PTR_ERR(info->regulator);
3062 dev_err(&pdev->dev, "failed to register regulator %s\n",
3063 info->desc.name);
3064 /* when we fail, un-register all earlier regulators */
3065 while (--id >= 0) {
3066 info = &abx500_regulator.info[id];
3067 regulator_unregister(info->regulator);
3068 }
3069 return err;
3070 }
3071
3072 return 0;
3073}
3074
a5023574 3075static int
b54969ac 3076ab8500_regulator_of_probe(struct platform_device *pdev,
b54969ac 3077 struct device_node *np)
3a8334b9 3078{
33aeb49e 3079 struct of_regulator_match *match = abx500_regulator.match;
3a8334b9
LJ		 3080 int err, i;
3081
33aeb49e 3082 for (i = 0; i < abx500_regulator.info_size; i++) {
3a8334b9 3083 err = ab8500_regulator_register(
33aeb49e 3084 pdev, match[i].init_data, i, match[i].of_node);
3a8334b9
LJ		 3085 if (err)
3086 return err;
3087 }
3088
3089 return 0;
3090}
3091
a5023574 3092static int ab8500_regulator_probe(struct platform_device *pdev)
c789ca20
SI		 3093{
3094 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
3a8334b9 3095 struct device_node *np = pdev->dev.of_node;
732805a5
BJ		 3096 struct ab8500_platform_data *ppdata;
3097 struct ab8500_regulator_platform_data *pdata;
c789ca20 3098 int i, err;
b54969ac 3099
33aeb49e
LJ		 3100 if (!ab8500) {
3101 dev_err(&pdev->dev, "null mfd parent\n");
3102 return -EINVAL;
8e6a8d7d 3103 }
c789ca20 3104
33aeb49e
LJ		 3105 abx500_get_regulator_info(ab8500);
3106
3a8334b9 3107 if (np) {
33aeb49e
LJ		 3108 err = of_regulator_match(&pdev->dev, np,
3109 abx500_regulator.match,
3110 abx500_regulator.match_size);
3a8334b9
LJ		 3111 if (err < 0) {
3112 dev_err(&pdev->dev,
3113 "Error parsing regulator init data: %d\n", err);
3114 return err;
3115 }
3116
33aeb49e 3117 err = ab8500_regulator_of_probe(pdev, np);
3a8334b9
LJ		 3118 return err;
3119 }
3120
732805a5
BJ		 3121 ppdata = dev_get_platdata(ab8500->dev);
3122 if (!ppdata) {
3123 dev_err(&pdev->dev, "null parent pdata\n");
3124 return -EINVAL;
3125 }
3126
3127 pdata = ppdata->regulator;
fc24b426
BJ		 3128 if (!pdata) {
3129 dev_err(&pdev->dev, "null pdata\n");
3130 return -EINVAL;
3131 }
c789ca20 3132
cb189b07 3133 /* make sure the platform data has the correct size */
33aeb49e 3134 if (pdata->num_regulator != abx500_regulator.info_size) {
79568b94 3135 dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
cb189b07
BJ		 3136 return -EINVAL;
3137 }
3138
da0b0c47
LJ		 3139 /* initialize debug (initial state is recorded with this call) */
3140 err = ab8500_regulator_debug_init(pdev);
3141 if (err)
3142 return err;
3143
79568b94 3144 /* initialize registers */
732805a5 3145 for (i = 0; i < pdata->num_reg_init; i++) {
3c1b8438 3146 int id, mask, value;
79568b94 3147
732805a5
BJ		 3148 id = pdata->reg_init[i].id;
3149 mask = pdata->reg_init[i].mask;
3150 value = pdata->reg_init[i].value;
79568b94
BJ		 3151
3152 /* check for configuration errors */
33aeb49e 3153 BUG_ON(id >= abx500_regulator.init_size);
79568b94 3154
33aeb49e 3155 err = ab8500_regulator_init_registers(pdev, id, mask, value);
a7ac1d9e 3156 if (err < 0)
79568b94 3157 return err;
79568b94
BJ		 3158 }
3159
f7eae37f
RV		 3160 if (!is_ab8505(ab8500)) {
3161 /* register external regulators (before Vaux1, 2 and 3) */
3162 err = ab8500_ext_regulator_init(pdev);
3163 if (err)
3164 return err;
3165 }
d1a82001 3166
c789ca20 3167 /* register all regulators */
33aeb49e 3168 for (i = 0; i < abx500_regulator.info_size; i++) {
b54969ac 3169 err = ab8500_regulator_register(pdev, &pdata->regulator[i],
33aeb49e 3170 i, NULL);
42e8c811
AL		 3171 if (err < 0) {
3172 if (!is_ab8505(ab8500))
3173 ab8500_ext_regulator_exit(pdev);
c789ca20 3174 return err;
42e8c811 3175 }
c789ca20
SI		 3176 }
3177
3178 return 0;
3179}
3180
8dc995f5 3181static int ab8500_regulator_remove(struct platform_device *pdev)
c789ca20 3182{
d1a82001 3183 int i, err;
8e6a8d7d 3184 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
b54969ac 3185
33aeb49e 3186 for (i = 0; i < abx500_regulator.info_size; i++) {
c789ca20 3187 struct ab8500_regulator_info *info = NULL;
33aeb49e 3188 info = &abx500_regulator.info[i];
09aefa12
BJ		 3189
3190 dev_vdbg(rdev_get_dev(info->regulator),
3191 "%s-remove\n", info->desc.name);
3192
c789ca20
SI		 3193 regulator_unregister(info->regulator);
3194 }
3195
3480c0ca
AL		 3196 /* remove external regulators (after Vaux1, 2 and 3) */
3197 if (!is_ab8505(ab8500))
3198 ab8500_ext_regulator_exit(pdev);
d1a82001 3199
da0b0c47
LJ		 3200 /* remove regulator debug */
3201 err = ab8500_regulator_debug_exit(pdev);
3202 if (err)
3203 return err;
3204
c789ca20
SI		 3205 return 0;
3206}
3207
3208static struct platform_driver ab8500_regulator_driver = {
3209 .probe = ab8500_regulator_probe,
5eb9f2b9 3210 .remove = ab8500_regulator_remove,
c789ca20
SI		 3211 .driver = {
3212 .name = "ab8500-regulator",
3213 .owner = THIS_MODULE,
3214 },
3215};
3216
3217static int __init ab8500_regulator_init(void)
3218{
3219 int ret;
3220
3221 ret = platform_driver_register(&ab8500_regulator_driver);
3222 if (ret != 0)
3223 pr_err("Failed to register ab8500 regulator: %d\n", ret);
3224
3225 return ret;
3226}
3227subsys_initcall(ab8500_regulator_init);
3228
3229static void __exit ab8500_regulator_exit(void)
3230{
3231 platform_driver_unregister(&ab8500_regulator_driver);
3232}
3233module_exit(ab8500_regulator_exit);
3234
3235MODULE_LICENSE("GPL v2");
3236MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
732805a5 3237MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
547f384f 3238MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
c789ca20
SI		 3239MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
3240MODULE_ALIAS("platform:ab8500-regulator");
Linux 6.x block layer and io_uring tree(s)