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0376148f | 1 | // SPDX-License-Identifier: GPL-2.0-only |
c789ca20 SI |
2 | /* |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
4 | * | |
e1159e6d BJ |
5 | * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson |
6 | * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson | |
547f384f | 7 | * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson |
c789ca20 SI |
8 | * |
9 | * AB8500 peripheral regulators | |
10 | * | |
e1159e6d | 11 | * AB8500 supports the following regulators: |
ea05ef31 | 12 | * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA |
547f384f LJ |
13 | * |
14 | * AB8505 supports the following regulators: | |
15 | * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA | |
c789ca20 SI |
16 | */ |
17 | #include <linux/init.h> | |
18 | #include <linux/kernel.h> | |
65602c32 | 19 | #include <linux/module.h> |
c789ca20 SI |
20 | #include <linux/err.h> |
21 | #include <linux/platform_device.h> | |
47c16975 | 22 | #include <linux/mfd/abx500.h> |
ee66e653 | 23 | #include <linux/mfd/abx500/ab8500.h> |
3a8334b9 LJ |
24 | #include <linux/of.h> |
25 | #include <linux/regulator/of_regulator.h> | |
c789ca20 SI |
26 | #include <linux/regulator/driver.h> |
27 | #include <linux/regulator/machine.h> | |
3a8334b9 | 28 | #include <linux/slab.h> |
c789ca20 | 29 | |
3acb64c0 LW |
30 | /* AB8500 regulators */ |
31 | enum ab8500_regulator_id { | |
32 | AB8500_LDO_AUX1, | |
33 | AB8500_LDO_AUX2, | |
34 | AB8500_LDO_AUX3, | |
35 | AB8500_LDO_INTCORE, | |
36 | AB8500_LDO_TVOUT, | |
37 | AB8500_LDO_AUDIO, | |
38 | AB8500_LDO_ANAMIC1, | |
39 | AB8500_LDO_ANAMIC2, | |
40 | AB8500_LDO_DMIC, | |
41 | AB8500_LDO_ANA, | |
42 | AB8500_NUM_REGULATORS, | |
43 | }; | |
44 | ||
45 | /* AB8505 regulators */ | |
46 | enum ab8505_regulator_id { | |
47 | AB8505_LDO_AUX1, | |
48 | AB8505_LDO_AUX2, | |
49 | AB8505_LDO_AUX3, | |
50 | AB8505_LDO_AUX4, | |
51 | AB8505_LDO_AUX5, | |
52 | AB8505_LDO_AUX6, | |
53 | AB8505_LDO_INTCORE, | |
54 | AB8505_LDO_ADC, | |
55 | AB8505_LDO_AUDIO, | |
56 | AB8505_LDO_ANAMIC1, | |
57 | AB8505_LDO_ANAMIC2, | |
58 | AB8505_LDO_AUX8, | |
59 | AB8505_LDO_ANA, | |
60 | AB8505_NUM_REGULATORS, | |
61 | }; | |
62 | ||
63 | /* AB8500 registers */ | |
64 | enum ab8500_regulator_reg { | |
65 | AB8500_REGUREQUESTCTRL2, | |
66 | AB8500_REGUREQUESTCTRL3, | |
67 | AB8500_REGUREQUESTCTRL4, | |
68 | AB8500_REGUSYSCLKREQ1HPVALID1, | |
69 | AB8500_REGUSYSCLKREQ1HPVALID2, | |
70 | AB8500_REGUHWHPREQ1VALID1, | |
71 | AB8500_REGUHWHPREQ1VALID2, | |
72 | AB8500_REGUHWHPREQ2VALID1, | |
73 | AB8500_REGUHWHPREQ2VALID2, | |
74 | AB8500_REGUSWHPREQVALID1, | |
75 | AB8500_REGUSWHPREQVALID2, | |
76 | AB8500_REGUSYSCLKREQVALID1, | |
77 | AB8500_REGUSYSCLKREQVALID2, | |
78 | AB8500_REGUMISC1, | |
79 | AB8500_VAUDIOSUPPLY, | |
80 | AB8500_REGUCTRL1VAMIC, | |
81 | AB8500_VPLLVANAREGU, | |
82 | AB8500_VREFDDR, | |
83 | AB8500_EXTSUPPLYREGU, | |
84 | AB8500_VAUX12REGU, | |
85 | AB8500_VRF1VAUX3REGU, | |
86 | AB8500_VAUX1SEL, | |
87 | AB8500_VAUX2SEL, | |
88 | AB8500_VRF1VAUX3SEL, | |
89 | AB8500_REGUCTRL2SPARE, | |
90 | AB8500_REGUCTRLDISCH, | |
91 | AB8500_REGUCTRLDISCH2, | |
92 | AB8500_NUM_REGULATOR_REGISTERS, | |
93 | }; | |
94 | ||
95 | /* AB8505 registers */ | |
96 | enum ab8505_regulator_reg { | |
97 | AB8505_REGUREQUESTCTRL1, | |
98 | AB8505_REGUREQUESTCTRL2, | |
99 | AB8505_REGUREQUESTCTRL3, | |
100 | AB8505_REGUREQUESTCTRL4, | |
101 | AB8505_REGUSYSCLKREQ1HPVALID1, | |
102 | AB8505_REGUSYSCLKREQ1HPVALID2, | |
103 | AB8505_REGUHWHPREQ1VALID1, | |
104 | AB8505_REGUHWHPREQ1VALID2, | |
105 | AB8505_REGUHWHPREQ2VALID1, | |
106 | AB8505_REGUHWHPREQ2VALID2, | |
107 | AB8505_REGUSWHPREQVALID1, | |
108 | AB8505_REGUSWHPREQVALID2, | |
109 | AB8505_REGUSYSCLKREQVALID1, | |
110 | AB8505_REGUSYSCLKREQVALID2, | |
111 | AB8505_REGUVAUX4REQVALID, | |
112 | AB8505_REGUMISC1, | |
113 | AB8505_VAUDIOSUPPLY, | |
114 | AB8505_REGUCTRL1VAMIC, | |
115 | AB8505_VSMPSAREGU, | |
116 | AB8505_VSMPSBREGU, | |
117 | AB8505_VSAFEREGU, /* NOTE! PRCMU register */ | |
118 | AB8505_VPLLVANAREGU, | |
119 | AB8505_EXTSUPPLYREGU, | |
120 | AB8505_VAUX12REGU, | |
121 | AB8505_VRF1VAUX3REGU, | |
122 | AB8505_VSMPSASEL1, | |
123 | AB8505_VSMPSASEL2, | |
124 | AB8505_VSMPSASEL3, | |
125 | AB8505_VSMPSBSEL1, | |
126 | AB8505_VSMPSBSEL2, | |
127 | AB8505_VSMPSBSEL3, | |
128 | AB8505_VSAFESEL1, /* NOTE! PRCMU register */ | |
129 | AB8505_VSAFESEL2, /* NOTE! PRCMU register */ | |
130 | AB8505_VSAFESEL3, /* NOTE! PRCMU register */ | |
131 | AB8505_VAUX1SEL, | |
132 | AB8505_VAUX2SEL, | |
133 | AB8505_VRF1VAUX3SEL, | |
134 | AB8505_VAUX4REQCTRL, | |
135 | AB8505_VAUX4REGU, | |
136 | AB8505_VAUX4SEL, | |
137 | AB8505_REGUCTRLDISCH, | |
138 | AB8505_REGUCTRLDISCH2, | |
139 | AB8505_REGUCTRLDISCH3, | |
140 | AB8505_CTRLVAUX5, | |
141 | AB8505_CTRLVAUX6, | |
142 | AB8505_NUM_REGULATOR_REGISTERS, | |
143 | }; | |
144 | ||
3fe52289 LJ |
145 | /** |
146 | * struct ab8500_shared_mode - is used when mode is shared between | |
147 | * two regulators. | |
148 | * @shared_regulator: pointer to the other sharing regulator | |
149 | * @lp_mode_req: low power mode requested by this regulator | |
150 | */ | |
151 | struct ab8500_shared_mode { | |
152 | struct ab8500_regulator_info *shared_regulator; | |
153 | bool lp_mode_req; | |
154 | }; | |
155 | ||
c789ca20 SI |
156 | /** |
157 | * struct ab8500_regulator_info - ab8500 regulator information | |
e1159e6d | 158 | * @dev: device pointer |
c789ca20 | 159 | * @desc: regulator description |
3fe52289 | 160 | * @shared_mode: used when mode is shared between two regulators |
7ce4669c | 161 | * @load_lp_uA: maximum load in idle (low power) mode |
47c16975 | 162 | * @update_bank: bank to control on/off |
c789ca20 | 163 | * @update_reg: register to control on/off |
bd28a157 EV |
164 | * @update_mask: mask to enable/disable and set mode of regulator |
165 | * @update_val: bits holding the regulator current mode | |
166 | * @update_val_idle: bits to enable the regulator in idle (low power) mode | |
167 | * @update_val_normal: bits to enable the regulator in normal (high power) mode | |
3fe52289 LJ |
168 | * @mode_bank: bank with location of mode register |
169 | * @mode_reg: mode register | |
170 | * @mode_mask: mask for setting mode | |
171 | * @mode_val_idle: mode setting for low power | |
172 | * @mode_val_normal: mode setting for normal power | |
47c16975 | 173 | * @voltage_bank: bank to control regulator voltage |
c789ca20 SI |
174 | * @voltage_reg: register to control regulator voltage |
175 | * @voltage_mask: mask to control regulator voltage | |
aeee55b7 | 176 | * @expand_register: |
c789ca20 SI |
177 | */ |
178 | struct ab8500_regulator_info { | |
179 | struct device *dev; | |
180 | struct regulator_desc desc; | |
3fe52289 | 181 | struct ab8500_shared_mode *shared_mode; |
7ce4669c | 182 | int load_lp_uA; |
47c16975 MW |
183 | u8 update_bank; |
184 | u8 update_reg; | |
e1159e6d | 185 | u8 update_mask; |
bd28a157 EV |
186 | u8 update_val; |
187 | u8 update_val_idle; | |
188 | u8 update_val_normal; | |
3fe52289 LJ |
189 | u8 mode_bank; |
190 | u8 mode_reg; | |
191 | u8 mode_mask; | |
192 | u8 mode_val_idle; | |
193 | u8 mode_val_normal; | |
47c16975 MW |
194 | u8 voltage_bank; |
195 | u8 voltage_reg; | |
196 | u8 voltage_mask; | |
c789ca20 SI |
197 | }; |
198 | ||
199 | /* voltage tables for the vauxn/vintcore supplies */ | |
ec1cc4d9 | 200 | static const unsigned int ldo_vauxn_voltages[] = { |
c789ca20 SI |
201 | 1100000, |
202 | 1200000, | |
203 | 1300000, | |
204 | 1400000, | |
205 | 1500000, | |
206 | 1800000, | |
207 | 1850000, | |
208 | 1900000, | |
209 | 2500000, | |
210 | 2650000, | |
211 | 2700000, | |
212 | 2750000, | |
213 | 2800000, | |
214 | 2900000, | |
215 | 3000000, | |
216 | 3300000, | |
217 | }; | |
218 | ||
ec1cc4d9 | 219 | static const unsigned int ldo_vaux3_voltages[] = { |
2b75151a BJ |
220 | 1200000, |
221 | 1500000, | |
222 | 1800000, | |
223 | 2100000, | |
224 | 2500000, | |
225 | 2750000, | |
226 | 2790000, | |
227 | 2910000, | |
228 | }; | |
229 | ||
62ab4111 | 230 | static const unsigned int ldo_vaux56_voltages[] = { |
547f384f LJ |
231 | 1800000, |
232 | 1050000, | |
233 | 1100000, | |
234 | 1200000, | |
235 | 1500000, | |
236 | 2200000, | |
237 | 2500000, | |
238 | 2790000, | |
239 | }; | |
240 | ||
ec1cc4d9 | 241 | static const unsigned int ldo_vintcore_voltages[] = { |
c789ca20 SI |
242 | 1200000, |
243 | 1225000, | |
244 | 1250000, | |
245 | 1275000, | |
246 | 1300000, | |
247 | 1325000, | |
248 | 1350000, | |
249 | }; | |
250 | ||
b080c78a LJ |
251 | static const unsigned int fixed_1200000_voltage[] = { |
252 | 1200000, | |
253 | }; | |
254 | ||
255 | static const unsigned int fixed_1800000_voltage[] = { | |
256 | 1800000, | |
257 | }; | |
258 | ||
259 | static const unsigned int fixed_2000000_voltage[] = { | |
260 | 2000000, | |
261 | }; | |
262 | ||
263 | static const unsigned int fixed_2050000_voltage[] = { | |
264 | 2050000, | |
265 | }; | |
266 | ||
8a3b1b87 LJ |
267 | static const unsigned int ldo_vana_voltages[] = { |
268 | 1050000, | |
269 | 1075000, | |
270 | 1100000, | |
271 | 1125000, | |
272 | 1150000, | |
273 | 1175000, | |
274 | 1200000, | |
275 | 1225000, | |
276 | }; | |
277 | ||
278 | static const unsigned int ldo_vaudio_voltages[] = { | |
279 | 2000000, | |
280 | 2100000, | |
281 | 2200000, | |
282 | 2300000, | |
283 | 2400000, | |
284 | 2500000, | |
285 | 2600000, | |
286 | 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */ | |
287 | }; | |
288 | ||
3fe52289 LJ |
289 | static DEFINE_MUTEX(shared_mode_mutex); |
290 | static struct ab8500_shared_mode ldo_anamic1_shared; | |
291 | static struct ab8500_shared_mode ldo_anamic2_shared; | |
292 | ||
c789ca20 SI |
293 | static int ab8500_regulator_enable(struct regulator_dev *rdev) |
294 | { | |
fc24b426 | 295 | int ret; |
c789ca20 SI |
296 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); |
297 | ||
fc24b426 BJ |
298 | if (info == NULL) { |
299 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
c789ca20 | 300 | return -EINVAL; |
fc24b426 | 301 | } |
c789ca20 | 302 | |
47c16975 | 303 | ret = abx500_mask_and_set_register_interruptible(info->dev, |
e1159e6d | 304 | info->update_bank, info->update_reg, |
bd28a157 | 305 | info->update_mask, info->update_val); |
f71bf528 | 306 | if (ret < 0) { |
c789ca20 SI |
307 | dev_err(rdev_get_dev(rdev), |
308 | "couldn't set enable bits for regulator\n"); | |
f71bf528 AL |
309 | return ret; |
310 | } | |
09aefa12 BJ |
311 | |
312 | dev_vdbg(rdev_get_dev(rdev), | |
313 | "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", | |
314 | info->desc.name, info->update_bank, info->update_reg, | |
bd28a157 | 315 | info->update_mask, info->update_val); |
09aefa12 | 316 | |
c789ca20 SI |
317 | return ret; |
318 | } | |
319 | ||
320 | static int ab8500_regulator_disable(struct regulator_dev *rdev) | |
321 | { | |
fc24b426 | 322 | int ret; |
c789ca20 SI |
323 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); |
324 | ||
fc24b426 BJ |
325 | if (info == NULL) { |
326 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
c789ca20 | 327 | return -EINVAL; |
fc24b426 | 328 | } |
c789ca20 | 329 | |
47c16975 | 330 | ret = abx500_mask_and_set_register_interruptible(info->dev, |
e1159e6d BJ |
331 | info->update_bank, info->update_reg, |
332 | info->update_mask, 0x0); | |
f71bf528 | 333 | if (ret < 0) { |
c789ca20 SI |
334 | dev_err(rdev_get_dev(rdev), |
335 | "couldn't set disable bits for regulator\n"); | |
f71bf528 AL |
336 | return ret; |
337 | } | |
09aefa12 BJ |
338 | |
339 | dev_vdbg(rdev_get_dev(rdev), | |
340 | "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n", | |
341 | info->desc.name, info->update_bank, info->update_reg, | |
342 | info->update_mask, 0x0); | |
343 | ||
c789ca20 SI |
344 | return ret; |
345 | } | |
346 | ||
438e695b AL |
347 | static int ab8500_regulator_is_enabled(struct regulator_dev *rdev) |
348 | { | |
349 | int ret; | |
350 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); | |
351 | u8 regval; | |
352 | ||
353 | if (info == NULL) { | |
354 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
355 | return -EINVAL; | |
356 | } | |
357 | ||
358 | ret = abx500_get_register_interruptible(info->dev, | |
359 | info->update_bank, info->update_reg, ®val); | |
360 | if (ret < 0) { | |
361 | dev_err(rdev_get_dev(rdev), | |
362 | "couldn't read 0x%x register\n", info->update_reg); | |
363 | return ret; | |
364 | } | |
365 | ||
366 | dev_vdbg(rdev_get_dev(rdev), | |
367 | "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x," | |
368 | " 0x%x\n", | |
369 | info->desc.name, info->update_bank, info->update_reg, | |
370 | info->update_mask, regval); | |
371 | ||
372 | if (regval & info->update_mask) | |
373 | return 1; | |
374 | else | |
375 | return 0; | |
376 | } | |
377 | ||
7ce4669c BJ |
378 | static unsigned int ab8500_regulator_get_optimum_mode( |
379 | struct regulator_dev *rdev, int input_uV, | |
380 | int output_uV, int load_uA) | |
381 | { | |
382 | unsigned int mode; | |
383 | ||
384 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); | |
385 | ||
386 | if (info == NULL) { | |
387 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
388 | return -EINVAL; | |
389 | } | |
390 | ||
391 | if (load_uA <= info->load_lp_uA) | |
392 | mode = REGULATOR_MODE_IDLE; | |
393 | else | |
394 | mode = REGULATOR_MODE_NORMAL; | |
395 | ||
396 | return mode; | |
397 | } | |
398 | ||
bd28a157 EV |
399 | static int ab8500_regulator_set_mode(struct regulator_dev *rdev, |
400 | unsigned int mode) | |
401 | { | |
3fe52289 | 402 | int ret = 0; |
0b665062 AL |
403 | u8 bank, reg, mask, val; |
404 | bool lp_mode_req = false; | |
bd28a157 EV |
405 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); |
406 | ||
407 | if (info == NULL) { | |
408 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
409 | return -EINVAL; | |
410 | } | |
411 | ||
3fe52289 | 412 | if (info->mode_mask) { |
3fe52289 LJ |
413 | bank = info->mode_bank; |
414 | reg = info->mode_reg; | |
415 | mask = info->mode_mask; | |
416 | } else { | |
0b665062 AL |
417 | bank = info->update_bank; |
418 | reg = info->update_reg; | |
419 | mask = info->update_mask; | |
420 | } | |
3fe52289 | 421 | |
0b665062 AL |
422 | if (info->shared_mode) |
423 | mutex_lock(&shared_mode_mutex); | |
424 | ||
425 | switch (mode) { | |
426 | case REGULATOR_MODE_NORMAL: | |
427 | if (info->shared_mode) | |
428 | lp_mode_req = false; | |
429 | ||
430 | if (info->mode_mask) | |
431 | val = info->mode_val_normal; | |
432 | else | |
3fe52289 | 433 | val = info->update_val_normal; |
0b665062 AL |
434 | break; |
435 | case REGULATOR_MODE_IDLE: | |
436 | if (info->shared_mode) { | |
437 | struct ab8500_regulator_info *shared_regulator; | |
438 | ||
439 | shared_regulator = info->shared_mode->shared_regulator; | |
440 | if (!shared_regulator->shared_mode->lp_mode_req) { | |
441 | /* Other regulator prevent LP mode */ | |
442 | info->shared_mode->lp_mode_req = true; | |
443 | goto out_unlock; | |
444 | } | |
445 | ||
446 | lp_mode_req = true; | |
3fe52289 LJ |
447 | } |
448 | ||
0b665062 AL |
449 | if (info->mode_mask) |
450 | val = info->mode_val_idle; | |
451 | else | |
452 | val = info->update_val_idle; | |
453 | break; | |
454 | default: | |
455 | ret = -EINVAL; | |
456 | goto out_unlock; | |
bd28a157 EV |
457 | } |
458 | ||
0b665062 | 459 | if (info->mode_mask || ab8500_regulator_is_enabled(rdev)) { |
bd28a157 | 460 | ret = abx500_mask_and_set_register_interruptible(info->dev, |
3fe52289 | 461 | bank, reg, mask, val); |
f04adc5a | 462 | if (ret < 0) { |
bd28a157 EV |
463 | dev_err(rdev_get_dev(rdev), |
464 | "couldn't set regulator mode\n"); | |
f04adc5a AL |
465 | goto out_unlock; |
466 | } | |
7ce4669c BJ |
467 | |
468 | dev_vdbg(rdev_get_dev(rdev), | |
469 | "%s-set_mode (bank, reg, mask, value): " | |
470 | "0x%x, 0x%x, 0x%x, 0x%x\n", | |
3fe52289 LJ |
471 | info->desc.name, bank, reg, |
472 | mask, val); | |
bd28a157 EV |
473 | } |
474 | ||
0b665062 | 475 | if (!info->mode_mask) |
f04adc5a AL |
476 | info->update_val = val; |
477 | ||
0b665062 AL |
478 | if (info->shared_mode) |
479 | info->shared_mode->lp_mode_req = lp_mode_req; | |
480 | ||
f04adc5a | 481 | out_unlock: |
3fe52289 LJ |
482 | if (info->shared_mode) |
483 | mutex_unlock(&shared_mode_mutex); | |
742a7325 | 484 | |
3fe52289 | 485 | return ret; |
bd28a157 EV |
486 | } |
487 | ||
488 | static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev) | |
489 | { | |
490 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); | |
491 | int ret; | |
3fe52289 LJ |
492 | u8 val; |
493 | u8 val_normal; | |
494 | u8 val_idle; | |
bd28a157 EV |
495 | |
496 | if (info == NULL) { | |
497 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
498 | return -EINVAL; | |
499 | } | |
500 | ||
3fe52289 LJ |
501 | /* Need special handling for shared mode */ |
502 | if (info->shared_mode) { | |
503 | if (info->shared_mode->lp_mode_req) | |
504 | return REGULATOR_MODE_IDLE; | |
505 | else | |
506 | return REGULATOR_MODE_NORMAL; | |
507 | } | |
508 | ||
509 | if (info->mode_mask) { | |
510 | /* Dedicated register for handling mode */ | |
511 | ret = abx500_get_register_interruptible(info->dev, | |
512 | info->mode_bank, info->mode_reg, &val); | |
513 | val = val & info->mode_mask; | |
514 | ||
515 | val_normal = info->mode_val_normal; | |
516 | val_idle = info->mode_val_idle; | |
517 | } else { | |
518 | /* Mode register same as enable register */ | |
519 | val = info->update_val; | |
520 | val_normal = info->update_val_normal; | |
521 | val_idle = info->update_val_idle; | |
522 | } | |
523 | ||
524 | if (val == val_normal) | |
bd28a157 | 525 | ret = REGULATOR_MODE_NORMAL; |
3fe52289 | 526 | else if (val == val_idle) |
bd28a157 EV |
527 | ret = REGULATOR_MODE_IDLE; |
528 | else | |
529 | ret = -EINVAL; | |
530 | ||
531 | return ret; | |
532 | } | |
533 | ||
3bf6e90e | 534 | static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev) |
c789ca20 | 535 | { |
5d9de8b1 | 536 | int ret, voltage_shift; |
c789ca20 | 537 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); |
09aefa12 | 538 | u8 regval; |
c789ca20 | 539 | |
fc24b426 BJ |
540 | if (info == NULL) { |
541 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
c789ca20 | 542 | return -EINVAL; |
fc24b426 | 543 | } |
c789ca20 | 544 | |
5d9de8b1 AL |
545 | voltage_shift = ffs(info->voltage_mask) - 1; |
546 | ||
09aefa12 BJ |
547 | ret = abx500_get_register_interruptible(info->dev, |
548 | info->voltage_bank, info->voltage_reg, ®val); | |
c789ca20 SI |
549 | if (ret < 0) { |
550 | dev_err(rdev_get_dev(rdev), | |
551 | "couldn't read voltage reg for regulator\n"); | |
552 | return ret; | |
553 | } | |
554 | ||
09aefa12 | 555 | dev_vdbg(rdev_get_dev(rdev), |
a0a7014c LW |
556 | "%s-get_voltage (bank, reg, mask, shift, value): " |
557 | "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", | |
558 | info->desc.name, info->voltage_bank, | |
559 | info->voltage_reg, info->voltage_mask, | |
5d9de8b1 | 560 | voltage_shift, regval); |
09aefa12 | 561 | |
5d9de8b1 | 562 | return (regval & info->voltage_mask) >> voltage_shift; |
c789ca20 SI |
563 | } |
564 | ||
ae713d39 AL |
565 | static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev, |
566 | unsigned selector) | |
c789ca20 | 567 | { |
5d9de8b1 | 568 | int ret, voltage_shift; |
c789ca20 | 569 | struct ab8500_regulator_info *info = rdev_get_drvdata(rdev); |
09aefa12 | 570 | u8 regval; |
c789ca20 | 571 | |
fc24b426 BJ |
572 | if (info == NULL) { |
573 | dev_err(rdev_get_dev(rdev), "regulator info null pointer\n"); | |
c789ca20 | 574 | return -EINVAL; |
fc24b426 | 575 | } |
c789ca20 | 576 | |
5d9de8b1 AL |
577 | voltage_shift = ffs(info->voltage_mask) - 1; |
578 | ||
c789ca20 | 579 | /* set the registers for the request */ |
5d9de8b1 | 580 | regval = (u8)selector << voltage_shift; |
47c16975 | 581 | ret = abx500_mask_and_set_register_interruptible(info->dev, |
09aefa12 BJ |
582 | info->voltage_bank, info->voltage_reg, |
583 | info->voltage_mask, regval); | |
c789ca20 SI |
584 | if (ret < 0) |
585 | dev_err(rdev_get_dev(rdev), | |
586 | "couldn't set voltage reg for regulator\n"); | |
587 | ||
09aefa12 BJ |
588 | dev_vdbg(rdev_get_dev(rdev), |
589 | "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x," | |
590 | " 0x%x\n", | |
591 | info->desc.name, info->voltage_bank, info->voltage_reg, | |
592 | info->voltage_mask, regval); | |
593 | ||
c789ca20 SI |
594 | return ret; |
595 | } | |
596 | ||
6d66d995 | 597 | static const struct regulator_ops ab8500_regulator_volt_mode_ops = { |
7ce4669c BJ |
598 | .enable = ab8500_regulator_enable, |
599 | .disable = ab8500_regulator_disable, | |
600 | .is_enabled = ab8500_regulator_is_enabled, | |
601 | .get_optimum_mode = ab8500_regulator_get_optimum_mode, | |
602 | .set_mode = ab8500_regulator_set_mode, | |
603 | .get_mode = ab8500_regulator_get_mode, | |
604 | .get_voltage_sel = ab8500_regulator_get_voltage_sel, | |
605 | .set_voltage_sel = ab8500_regulator_set_voltage_sel, | |
606 | .list_voltage = regulator_list_voltage_table, | |
c789ca20 SI |
607 | }; |
608 | ||
6d66d995 | 609 | static const struct regulator_ops ab8500_regulator_volt_ops = { |
8a3b1b87 LJ |
610 | .enable = ab8500_regulator_enable, |
611 | .disable = ab8500_regulator_disable, | |
612 | .is_enabled = ab8500_regulator_is_enabled, | |
613 | .get_voltage_sel = ab8500_regulator_get_voltage_sel, | |
614 | .set_voltage_sel = ab8500_regulator_set_voltage_sel, | |
615 | .list_voltage = regulator_list_voltage_table, | |
8a3b1b87 LJ |
616 | }; |
617 | ||
6d66d995 | 618 | static const struct regulator_ops ab8500_regulator_mode_ops = { |
7ce4669c BJ |
619 | .enable = ab8500_regulator_enable, |
620 | .disable = ab8500_regulator_disable, | |
621 | .is_enabled = ab8500_regulator_is_enabled, | |
622 | .get_optimum_mode = ab8500_regulator_get_optimum_mode, | |
623 | .set_mode = ab8500_regulator_set_mode, | |
624 | .get_mode = ab8500_regulator_get_mode, | |
d7816ab0 | 625 | .list_voltage = regulator_list_voltage_table, |
7ce4669c BJ |
626 | }; |
627 | ||
6d66d995 | 628 | static const struct regulator_ops ab8500_regulator_ops = { |
7ce4669c BJ |
629 | .enable = ab8500_regulator_enable, |
630 | .disable = ab8500_regulator_disable, | |
631 | .is_enabled = ab8500_regulator_is_enabled, | |
d7816ab0 | 632 | .list_voltage = regulator_list_voltage_table, |
c789ca20 SI |
633 | }; |
634 | ||
6d66d995 | 635 | static const struct regulator_ops ab8500_regulator_anamic_mode_ops = { |
3fe52289 LJ |
636 | .enable = ab8500_regulator_enable, |
637 | .disable = ab8500_regulator_disable, | |
638 | .is_enabled = ab8500_regulator_is_enabled, | |
639 | .set_mode = ab8500_regulator_set_mode, | |
640 | .get_mode = ab8500_regulator_get_mode, | |
641 | .list_voltage = regulator_list_voltage_table, | |
642 | }; | |
643 | ||
8e6a8d7d | 644 | /* AB8500 regulator information */ |
6909b452 BJ |
645 | static struct ab8500_regulator_info |
646 | ab8500_regulator_info[AB8500_NUM_REGULATORS] = { | |
c789ca20 | 647 | /* |
e1159e6d BJ |
648 | * Variable Voltage Regulators |
649 | * name, min mV, max mV, | |
650 | * update bank, reg, mask, enable val | |
ec1cc4d9 | 651 | * volt bank, reg, mask |
c789ca20 | 652 | */ |
6909b452 BJ |
653 | [AB8500_LDO_AUX1] = { |
654 | .desc = { | |
655 | .name = "LDO-AUX1", | |
7ce4669c | 656 | .ops = &ab8500_regulator_volt_mode_ops, |
6909b452 BJ |
657 | .type = REGULATOR_VOLTAGE, |
658 | .id = AB8500_LDO_AUX1, | |
659 | .owner = THIS_MODULE, | |
660 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
ec1cc4d9 | 661 | .volt_table = ldo_vauxn_voltages, |
530158b6 | 662 | .enable_time = 200, |
ce6f5ea3 | 663 | .supply_name = "vin", |
6909b452 | 664 | }, |
7ce4669c | 665 | .load_lp_uA = 5000, |
6909b452 BJ |
666 | .update_bank = 0x04, |
667 | .update_reg = 0x09, | |
668 | .update_mask = 0x03, | |
bd28a157 EV |
669 | .update_val = 0x01, |
670 | .update_val_idle = 0x03, | |
671 | .update_val_normal = 0x01, | |
6909b452 BJ |
672 | .voltage_bank = 0x04, |
673 | .voltage_reg = 0x1f, | |
674 | .voltage_mask = 0x0f, | |
6909b452 BJ |
675 | }, |
676 | [AB8500_LDO_AUX2] = { | |
677 | .desc = { | |
678 | .name = "LDO-AUX2", | |
7ce4669c | 679 | .ops = &ab8500_regulator_volt_mode_ops, |
6909b452 BJ |
680 | .type = REGULATOR_VOLTAGE, |
681 | .id = AB8500_LDO_AUX2, | |
682 | .owner = THIS_MODULE, | |
683 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
ec1cc4d9 | 684 | .volt_table = ldo_vauxn_voltages, |
530158b6 | 685 | .enable_time = 200, |
ce6f5ea3 | 686 | .supply_name = "vin", |
6909b452 | 687 | }, |
7ce4669c | 688 | .load_lp_uA = 5000, |
6909b452 BJ |
689 | .update_bank = 0x04, |
690 | .update_reg = 0x09, | |
691 | .update_mask = 0x0c, | |
bd28a157 EV |
692 | .update_val = 0x04, |
693 | .update_val_idle = 0x0c, | |
694 | .update_val_normal = 0x04, | |
6909b452 BJ |
695 | .voltage_bank = 0x04, |
696 | .voltage_reg = 0x20, | |
697 | .voltage_mask = 0x0f, | |
6909b452 BJ |
698 | }, |
699 | [AB8500_LDO_AUX3] = { | |
700 | .desc = { | |
701 | .name = "LDO-AUX3", | |
7ce4669c | 702 | .ops = &ab8500_regulator_volt_mode_ops, |
6909b452 BJ |
703 | .type = REGULATOR_VOLTAGE, |
704 | .id = AB8500_LDO_AUX3, | |
705 | .owner = THIS_MODULE, | |
706 | .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages), | |
ec1cc4d9 | 707 | .volt_table = ldo_vaux3_voltages, |
530158b6 | 708 | .enable_time = 450, |
ce6f5ea3 | 709 | .supply_name = "vin", |
6909b452 | 710 | }, |
7ce4669c | 711 | .load_lp_uA = 5000, |
6909b452 BJ |
712 | .update_bank = 0x04, |
713 | .update_reg = 0x0a, | |
714 | .update_mask = 0x03, | |
bd28a157 EV |
715 | .update_val = 0x01, |
716 | .update_val_idle = 0x03, | |
717 | .update_val_normal = 0x01, | |
6909b452 BJ |
718 | .voltage_bank = 0x04, |
719 | .voltage_reg = 0x21, | |
720 | .voltage_mask = 0x07, | |
6909b452 BJ |
721 | }, |
722 | [AB8500_LDO_INTCORE] = { | |
723 | .desc = { | |
724 | .name = "LDO-INTCORE", | |
7ce4669c | 725 | .ops = &ab8500_regulator_volt_mode_ops, |
6909b452 BJ |
726 | .type = REGULATOR_VOLTAGE, |
727 | .id = AB8500_LDO_INTCORE, | |
728 | .owner = THIS_MODULE, | |
729 | .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), | |
ec1cc4d9 | 730 | .volt_table = ldo_vintcore_voltages, |
530158b6 | 731 | .enable_time = 750, |
6909b452 | 732 | }, |
7ce4669c | 733 | .load_lp_uA = 5000, |
6909b452 BJ |
734 | .update_bank = 0x03, |
735 | .update_reg = 0x80, | |
736 | .update_mask = 0x44, | |
cc40dc29 | 737 | .update_val = 0x44, |
bd28a157 EV |
738 | .update_val_idle = 0x44, |
739 | .update_val_normal = 0x04, | |
6909b452 BJ |
740 | .voltage_bank = 0x03, |
741 | .voltage_reg = 0x80, | |
742 | .voltage_mask = 0x38, | |
6909b452 | 743 | }, |
c789ca20 SI |
744 | |
745 | /* | |
e1159e6d BJ |
746 | * Fixed Voltage Regulators |
747 | * name, fixed mV, | |
748 | * update bank, reg, mask, enable val | |
c789ca20 | 749 | */ |
6909b452 BJ |
750 | [AB8500_LDO_TVOUT] = { |
751 | .desc = { | |
752 | .name = "LDO-TVOUT", | |
7ce4669c | 753 | .ops = &ab8500_regulator_mode_ops, |
6909b452 BJ |
754 | .type = REGULATOR_VOLTAGE, |
755 | .id = AB8500_LDO_TVOUT, | |
756 | .owner = THIS_MODULE, | |
757 | .n_voltages = 1, | |
b080c78a | 758 | .volt_table = fixed_2000000_voltage, |
ed3c138e | 759 | .enable_time = 500, |
6909b452 | 760 | }, |
7ce4669c | 761 | .load_lp_uA = 1000, |
6909b452 BJ |
762 | .update_bank = 0x03, |
763 | .update_reg = 0x80, | |
764 | .update_mask = 0x82, | |
bd28a157 | 765 | .update_val = 0x02, |
7ce4669c BJ |
766 | .update_val_idle = 0x82, |
767 | .update_val_normal = 0x02, | |
6909b452 BJ |
768 | }, |
769 | [AB8500_LDO_AUDIO] = { | |
770 | .desc = { | |
771 | .name = "LDO-AUDIO", | |
7ce4669c | 772 | .ops = &ab8500_regulator_ops, |
6909b452 BJ |
773 | .type = REGULATOR_VOLTAGE, |
774 | .id = AB8500_LDO_AUDIO, | |
775 | .owner = THIS_MODULE, | |
776 | .n_voltages = 1, | |
530158b6 | 777 | .enable_time = 140, |
b080c78a | 778 | .volt_table = fixed_2000000_voltage, |
6909b452 | 779 | }, |
6909b452 BJ |
780 | .update_bank = 0x03, |
781 | .update_reg = 0x83, | |
782 | .update_mask = 0x02, | |
bd28a157 | 783 | .update_val = 0x02, |
6909b452 BJ |
784 | }, |
785 | [AB8500_LDO_ANAMIC1] = { | |
786 | .desc = { | |
787 | .name = "LDO-ANAMIC1", | |
7ce4669c | 788 | .ops = &ab8500_regulator_ops, |
6909b452 BJ |
789 | .type = REGULATOR_VOLTAGE, |
790 | .id = AB8500_LDO_ANAMIC1, | |
791 | .owner = THIS_MODULE, | |
792 | .n_voltages = 1, | |
530158b6 | 793 | .enable_time = 500, |
b080c78a | 794 | .volt_table = fixed_2050000_voltage, |
6909b452 | 795 | }, |
6909b452 BJ |
796 | .update_bank = 0x03, |
797 | .update_reg = 0x83, | |
798 | .update_mask = 0x08, | |
bd28a157 | 799 | .update_val = 0x08, |
6909b452 BJ |
800 | }, |
801 | [AB8500_LDO_ANAMIC2] = { | |
802 | .desc = { | |
803 | .name = "LDO-ANAMIC2", | |
7ce4669c | 804 | .ops = &ab8500_regulator_ops, |
6909b452 BJ |
805 | .type = REGULATOR_VOLTAGE, |
806 | .id = AB8500_LDO_ANAMIC2, | |
807 | .owner = THIS_MODULE, | |
808 | .n_voltages = 1, | |
530158b6 | 809 | .enable_time = 500, |
b080c78a | 810 | .volt_table = fixed_2050000_voltage, |
6909b452 | 811 | }, |
6909b452 BJ |
812 | .update_bank = 0x03, |
813 | .update_reg = 0x83, | |
814 | .update_mask = 0x10, | |
bd28a157 | 815 | .update_val = 0x10, |
6909b452 BJ |
816 | }, |
817 | [AB8500_LDO_DMIC] = { | |
818 | .desc = { | |
819 | .name = "LDO-DMIC", | |
7ce4669c | 820 | .ops = &ab8500_regulator_ops, |
6909b452 BJ |
821 | .type = REGULATOR_VOLTAGE, |
822 | .id = AB8500_LDO_DMIC, | |
823 | .owner = THIS_MODULE, | |
824 | .n_voltages = 1, | |
530158b6 | 825 | .enable_time = 420, |
b080c78a | 826 | .volt_table = fixed_1800000_voltage, |
6909b452 | 827 | }, |
6909b452 BJ |
828 | .update_bank = 0x03, |
829 | .update_reg = 0x83, | |
830 | .update_mask = 0x04, | |
bd28a157 | 831 | .update_val = 0x04, |
6909b452 | 832 | }, |
7ce4669c BJ |
833 | |
834 | /* | |
835 | * Regulators with fixed voltage and normal/idle modes | |
836 | */ | |
6909b452 BJ |
837 | [AB8500_LDO_ANA] = { |
838 | .desc = { | |
839 | .name = "LDO-ANA", | |
7ce4669c | 840 | .ops = &ab8500_regulator_mode_ops, |
6909b452 BJ |
841 | .type = REGULATOR_VOLTAGE, |
842 | .id = AB8500_LDO_ANA, | |
843 | .owner = THIS_MODULE, | |
844 | .n_voltages = 1, | |
530158b6 | 845 | .enable_time = 140, |
b080c78a | 846 | .volt_table = fixed_1200000_voltage, |
6909b452 | 847 | }, |
7ce4669c | 848 | .load_lp_uA = 1000, |
6909b452 BJ |
849 | .update_bank = 0x04, |
850 | .update_reg = 0x06, | |
851 | .update_mask = 0x0c, | |
bd28a157 | 852 | .update_val = 0x04, |
7ce4669c BJ |
853 | .update_val_idle = 0x0c, |
854 | .update_val_normal = 0x04, | |
6909b452 | 855 | }, |
8e6a8d7d | 856 | }; |
6909b452 | 857 | |
547f384f LJ |
858 | /* AB8505 regulator information */ |
859 | static struct ab8500_regulator_info | |
860 | ab8505_regulator_info[AB8505_NUM_REGULATORS] = { | |
861 | /* | |
862 | * Variable Voltage Regulators | |
863 | * name, min mV, max mV, | |
864 | * update bank, reg, mask, enable val | |
d3193103 | 865 | * volt bank, reg, mask |
547f384f LJ |
866 | */ |
867 | [AB8505_LDO_AUX1] = { | |
868 | .desc = { | |
869 | .name = "LDO-AUX1", | |
870 | .ops = &ab8500_regulator_volt_mode_ops, | |
871 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 872 | .id = AB8505_LDO_AUX1, |
547f384f LJ |
873 | .owner = THIS_MODULE, |
874 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
62ab4111 | 875 | .volt_table = ldo_vauxn_voltages, |
547f384f | 876 | }, |
547f384f LJ |
877 | .load_lp_uA = 5000, |
878 | .update_bank = 0x04, | |
879 | .update_reg = 0x09, | |
880 | .update_mask = 0x03, | |
881 | .update_val = 0x01, | |
882 | .update_val_idle = 0x03, | |
883 | .update_val_normal = 0x01, | |
884 | .voltage_bank = 0x04, | |
885 | .voltage_reg = 0x1f, | |
886 | .voltage_mask = 0x0f, | |
547f384f LJ |
887 | }, |
888 | [AB8505_LDO_AUX2] = { | |
889 | .desc = { | |
890 | .name = "LDO-AUX2", | |
891 | .ops = &ab8500_regulator_volt_mode_ops, | |
892 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 893 | .id = AB8505_LDO_AUX2, |
547f384f LJ |
894 | .owner = THIS_MODULE, |
895 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
62ab4111 | 896 | .volt_table = ldo_vauxn_voltages, |
547f384f | 897 | }, |
547f384f LJ |
898 | .load_lp_uA = 5000, |
899 | .update_bank = 0x04, | |
900 | .update_reg = 0x09, | |
901 | .update_mask = 0x0c, | |
902 | .update_val = 0x04, | |
903 | .update_val_idle = 0x0c, | |
904 | .update_val_normal = 0x04, | |
905 | .voltage_bank = 0x04, | |
906 | .voltage_reg = 0x20, | |
907 | .voltage_mask = 0x0f, | |
547f384f LJ |
908 | }, |
909 | [AB8505_LDO_AUX3] = { | |
910 | .desc = { | |
911 | .name = "LDO-AUX3", | |
912 | .ops = &ab8500_regulator_volt_mode_ops, | |
913 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 914 | .id = AB8505_LDO_AUX3, |
547f384f LJ |
915 | .owner = THIS_MODULE, |
916 | .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages), | |
62ab4111 | 917 | .volt_table = ldo_vaux3_voltages, |
547f384f | 918 | }, |
547f384f LJ |
919 | .load_lp_uA = 5000, |
920 | .update_bank = 0x04, | |
921 | .update_reg = 0x0a, | |
922 | .update_mask = 0x03, | |
923 | .update_val = 0x01, | |
924 | .update_val_idle = 0x03, | |
925 | .update_val_normal = 0x01, | |
926 | .voltage_bank = 0x04, | |
927 | .voltage_reg = 0x21, | |
928 | .voltage_mask = 0x07, | |
547f384f LJ |
929 | }, |
930 | [AB8505_LDO_AUX4] = { | |
931 | .desc = { | |
932 | .name = "LDO-AUX4", | |
933 | .ops = &ab8500_regulator_volt_mode_ops, | |
934 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 935 | .id = AB8505_LDO_AUX4, |
547f384f LJ |
936 | .owner = THIS_MODULE, |
937 | .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages), | |
62ab4111 | 938 | .volt_table = ldo_vauxn_voltages, |
547f384f | 939 | }, |
547f384f LJ |
940 | .load_lp_uA = 5000, |
941 | /* values for Vaux4Regu register */ | |
942 | .update_bank = 0x04, | |
943 | .update_reg = 0x2e, | |
944 | .update_mask = 0x03, | |
945 | .update_val = 0x01, | |
946 | .update_val_idle = 0x03, | |
947 | .update_val_normal = 0x01, | |
948 | /* values for Vaux4SEL register */ | |
949 | .voltage_bank = 0x04, | |
950 | .voltage_reg = 0x2f, | |
951 | .voltage_mask = 0x0f, | |
547f384f LJ |
952 | }, |
953 | [AB8505_LDO_AUX5] = { | |
954 | .desc = { | |
955 | .name = "LDO-AUX5", | |
956 | .ops = &ab8500_regulator_volt_mode_ops, | |
957 | .type = REGULATOR_VOLTAGE, | |
958 | .id = AB8505_LDO_AUX5, | |
959 | .owner = THIS_MODULE, | |
960 | .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages), | |
62ab4111 | 961 | .volt_table = ldo_vaux56_voltages, |
547f384f | 962 | }, |
547f384f LJ |
963 | .load_lp_uA = 2000, |
964 | /* values for CtrlVaux5 register */ | |
965 | .update_bank = 0x01, | |
966 | .update_reg = 0x55, | |
ae0a9a3e LJ |
967 | .update_mask = 0x18, |
968 | .update_val = 0x10, | |
969 | .update_val_idle = 0x18, | |
970 | .update_val_normal = 0x10, | |
547f384f LJ |
971 | .voltage_bank = 0x01, |
972 | .voltage_reg = 0x55, | |
973 | .voltage_mask = 0x07, | |
547f384f LJ |
974 | }, |
975 | [AB8505_LDO_AUX6] = { | |
976 | .desc = { | |
977 | .name = "LDO-AUX6", | |
978 | .ops = &ab8500_regulator_volt_mode_ops, | |
979 | .type = REGULATOR_VOLTAGE, | |
980 | .id = AB8505_LDO_AUX6, | |
981 | .owner = THIS_MODULE, | |
982 | .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages), | |
62ab4111 | 983 | .volt_table = ldo_vaux56_voltages, |
547f384f | 984 | }, |
547f384f LJ |
985 | .load_lp_uA = 2000, |
986 | /* values for CtrlVaux6 register */ | |
987 | .update_bank = 0x01, | |
988 | .update_reg = 0x56, | |
ae0a9a3e LJ |
989 | .update_mask = 0x18, |
990 | .update_val = 0x10, | |
991 | .update_val_idle = 0x18, | |
992 | .update_val_normal = 0x10, | |
547f384f LJ |
993 | .voltage_bank = 0x01, |
994 | .voltage_reg = 0x56, | |
995 | .voltage_mask = 0x07, | |
547f384f LJ |
996 | }, |
997 | [AB8505_LDO_INTCORE] = { | |
998 | .desc = { | |
999 | .name = "LDO-INTCORE", | |
1000 | .ops = &ab8500_regulator_volt_mode_ops, | |
1001 | .type = REGULATOR_VOLTAGE, | |
0b946411 | 1002 | .id = AB8505_LDO_INTCORE, |
547f384f LJ |
1003 | .owner = THIS_MODULE, |
1004 | .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages), | |
62ab4111 | 1005 | .volt_table = ldo_vintcore_voltages, |
547f384f | 1006 | }, |
547f384f LJ |
1007 | .load_lp_uA = 5000, |
1008 | .update_bank = 0x03, | |
1009 | .update_reg = 0x80, | |
1010 | .update_mask = 0x44, | |
1011 | .update_val = 0x04, | |
1012 | .update_val_idle = 0x44, | |
1013 | .update_val_normal = 0x04, | |
1014 | .voltage_bank = 0x03, | |
1015 | .voltage_reg = 0x80, | |
1016 | .voltage_mask = 0x38, | |
547f384f LJ |
1017 | }, |
1018 | ||
1019 | /* | |
1020 | * Fixed Voltage Regulators | |
1021 | * name, fixed mV, | |
1022 | * update bank, reg, mask, enable val | |
1023 | */ | |
1024 | [AB8505_LDO_ADC] = { | |
1025 | .desc = { | |
1026 | .name = "LDO-ADC", | |
1027 | .ops = &ab8500_regulator_mode_ops, | |
1028 | .type = REGULATOR_VOLTAGE, | |
1029 | .id = AB8505_LDO_ADC, | |
1030 | .owner = THIS_MODULE, | |
1031 | .n_voltages = 1, | |
b080c78a | 1032 | .volt_table = fixed_2000000_voltage, |
a4d68468 | 1033 | .enable_time = 10000, |
547f384f | 1034 | }, |
547f384f LJ |
1035 | .load_lp_uA = 1000, |
1036 | .update_bank = 0x03, | |
1037 | .update_reg = 0x80, | |
1038 | .update_mask = 0x82, | |
1039 | .update_val = 0x02, | |
1040 | .update_val_idle = 0x82, | |
1041 | .update_val_normal = 0x02, | |
1042 | }, | |
547f384f LJ |
1043 | [AB8505_LDO_AUDIO] = { |
1044 | .desc = { | |
1045 | .name = "LDO-AUDIO", | |
8a3b1b87 | 1046 | .ops = &ab8500_regulator_volt_ops, |
547f384f | 1047 | .type = REGULATOR_VOLTAGE, |
0b946411 | 1048 | .id = AB8505_LDO_AUDIO, |
547f384f | 1049 | .owner = THIS_MODULE, |
8a3b1b87 LJ |
1050 | .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages), |
1051 | .volt_table = ldo_vaudio_voltages, | |
547f384f | 1052 | }, |
547f384f LJ |
1053 | .update_bank = 0x03, |
1054 | .update_reg = 0x83, | |
1055 | .update_mask = 0x02, | |
1056 | .update_val = 0x02, | |
8a3b1b87 LJ |
1057 | .voltage_bank = 0x01, |
1058 | .voltage_reg = 0x57, | |
e4fc9d6d | 1059 | .voltage_mask = 0x70, |
547f384f LJ |
1060 | }, |
1061 | [AB8505_LDO_ANAMIC1] = { | |
1062 | .desc = { | |
1063 | .name = "LDO-ANAMIC1", | |
3fe52289 | 1064 | .ops = &ab8500_regulator_anamic_mode_ops, |
547f384f | 1065 | .type = REGULATOR_VOLTAGE, |
0b946411 | 1066 | .id = AB8505_LDO_ANAMIC1, |
547f384f LJ |
1067 | .owner = THIS_MODULE, |
1068 | .n_voltages = 1, | |
b080c78a | 1069 | .volt_table = fixed_2050000_voltage, |
547f384f | 1070 | }, |
4c84b4dd | 1071 | .shared_mode = &ldo_anamic1_shared, |
547f384f LJ |
1072 | .update_bank = 0x03, |
1073 | .update_reg = 0x83, | |
1074 | .update_mask = 0x08, | |
1075 | .update_val = 0x08, | |
3fe52289 LJ |
1076 | .mode_bank = 0x01, |
1077 | .mode_reg = 0x54, | |
1078 | .mode_mask = 0x04, | |
1079 | .mode_val_idle = 0x04, | |
1080 | .mode_val_normal = 0x00, | |
547f384f LJ |
1081 | }, |
1082 | [AB8505_LDO_ANAMIC2] = { | |
1083 | .desc = { | |
1084 | .name = "LDO-ANAMIC2", | |
3fe52289 | 1085 | .ops = &ab8500_regulator_anamic_mode_ops, |
547f384f | 1086 | .type = REGULATOR_VOLTAGE, |
0b946411 | 1087 | .id = AB8505_LDO_ANAMIC2, |
547f384f LJ |
1088 | .owner = THIS_MODULE, |
1089 | .n_voltages = 1, | |
b080c78a | 1090 | .volt_table = fixed_2050000_voltage, |
547f384f | 1091 | }, |
3fe52289 | 1092 | .shared_mode = &ldo_anamic2_shared, |
547f384f LJ |
1093 | .update_bank = 0x03, |
1094 | .update_reg = 0x83, | |
1095 | .update_mask = 0x10, | |
1096 | .update_val = 0x10, | |
3fe52289 LJ |
1097 | .mode_bank = 0x01, |
1098 | .mode_reg = 0x54, | |
1099 | .mode_mask = 0x04, | |
1100 | .mode_val_idle = 0x04, | |
1101 | .mode_val_normal = 0x00, | |
547f384f LJ |
1102 | }, |
1103 | [AB8505_LDO_AUX8] = { | |
1104 | .desc = { | |
1105 | .name = "LDO-AUX8", | |
1106 | .ops = &ab8500_regulator_ops, | |
1107 | .type = REGULATOR_VOLTAGE, | |
1108 | .id = AB8505_LDO_AUX8, | |
1109 | .owner = THIS_MODULE, | |
1110 | .n_voltages = 1, | |
b080c78a | 1111 | .volt_table = fixed_1800000_voltage, |
547f384f | 1112 | }, |
547f384f LJ |
1113 | .update_bank = 0x03, |
1114 | .update_reg = 0x83, | |
1115 | .update_mask = 0x04, | |
1116 | .update_val = 0x04, | |
1117 | }, | |
1118 | /* | |
1119 | * Regulators with fixed voltage and normal/idle modes | |
1120 | */ | |
1121 | [AB8505_LDO_ANA] = { | |
1122 | .desc = { | |
1123 | .name = "LDO-ANA", | |
8a3b1b87 | 1124 | .ops = &ab8500_regulator_volt_mode_ops, |
547f384f | 1125 | .type = REGULATOR_VOLTAGE, |
0b946411 | 1126 | .id = AB8505_LDO_ANA, |
547f384f | 1127 | .owner = THIS_MODULE, |
8a3b1b87 LJ |
1128 | .n_voltages = ARRAY_SIZE(ldo_vana_voltages), |
1129 | .volt_table = ldo_vana_voltages, | |
547f384f | 1130 | }, |
547f384f LJ |
1131 | .load_lp_uA = 1000, |
1132 | .update_bank = 0x04, | |
1133 | .update_reg = 0x06, | |
1134 | .update_mask = 0x0c, | |
1135 | .update_val = 0x04, | |
1136 | .update_val_idle = 0x0c, | |
1137 | .update_val_normal = 0x04, | |
8a3b1b87 LJ |
1138 | .voltage_bank = 0x04, |
1139 | .voltage_reg = 0x29, | |
1140 | .voltage_mask = 0x7, | |
547f384f LJ |
1141 | }, |
1142 | }; | |
1143 | ||
ec1ba3e5 LW |
1144 | static struct ab8500_shared_mode ldo_anamic1_shared = { |
1145 | .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC2], | |
1146 | }; | |
1147 | ||
1148 | static struct ab8500_shared_mode ldo_anamic2_shared = { | |
1149 | .shared_regulator = &ab8505_regulator_info[AB8505_LDO_ANAMIC1], | |
1150 | }; | |
1151 | ||
1152 | struct ab8500_reg_init { | |
1153 | u8 bank; | |
1154 | u8 addr; | |
1155 | u8 mask; | |
1156 | }; | |
1157 | ||
1158 | #define REG_INIT(_id, _bank, _addr, _mask) \ | |
1159 | [_id] = { \ | |
1160 | .bank = _bank, \ | |
1161 | .addr = _addr, \ | |
1162 | .mask = _mask, \ | |
1163 | } | |
1164 | ||
1165 | /* AB8500 register init */ | |
1166 | static struct ab8500_reg_init ab8500_reg_init[] = { | |
8e6a8d7d | 1167 | /* |
ec1ba3e5 LW |
1168 | * 0x30, VanaRequestCtrl |
1169 | * 0xc0, VextSupply1RequestCtrl | |
8e6a8d7d | 1170 | */ |
ec1ba3e5 | 1171 | REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0), |
8e6a8d7d | 1172 | /* |
ec1ba3e5 LW |
1173 | * 0x03, VextSupply2RequestCtrl |
1174 | * 0x0c, VextSupply3RequestCtrl | |
1175 | * 0x30, Vaux1RequestCtrl | |
1176 | * 0xc0, Vaux2RequestCtrl | |
8e6a8d7d | 1177 | */ |
ec1ba3e5 | 1178 | REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff), |
8e6a8d7d LJ |
1179 | /* |
1180 | * 0x03, Vaux3RequestCtrl | |
1181 | * 0x04, SwHPReq | |
1182 | */ | |
ec1ba3e5 | 1183 | REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), |
8e6a8d7d | 1184 | /* |
8e6a8d7d | 1185 | * 0x08, VanaSysClkReq1HPValid |
8e6a8d7d LJ |
1186 | * 0x20, Vaux1SysClkReq1HPValid |
1187 | * 0x40, Vaux2SysClkReq1HPValid | |
1188 | * 0x80, Vaux3SysClkReq1HPValid | |
1189 | */ | |
ec1ba3e5 | 1190 | REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8), |
8e6a8d7d | 1191 | /* |
8e6a8d7d LJ |
1192 | * 0x10, VextSupply1SysClkReq1HPValid |
1193 | * 0x20, VextSupply2SysClkReq1HPValid | |
1194 | * 0x40, VextSupply3SysClkReq1HPValid | |
1195 | */ | |
ec1ba3e5 | 1196 | REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70), |
8e6a8d7d | 1197 | /* |
8e6a8d7d | 1198 | * 0x08, VanaHwHPReq1Valid |
8e6a8d7d LJ |
1199 | * 0x20, Vaux1HwHPReq1Valid |
1200 | * 0x40, Vaux2HwHPReq1Valid | |
1201 | * 0x80, Vaux3HwHPReq1Valid | |
1202 | */ | |
ec1ba3e5 | 1203 | REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8), |
8e6a8d7d LJ |
1204 | /* |
1205 | * 0x01, VextSupply1HwHPReq1Valid | |
1206 | * 0x02, VextSupply2HwHPReq1Valid | |
1207 | * 0x04, VextSupply3HwHPReq1Valid | |
8e6a8d7d | 1208 | */ |
ec1ba3e5 | 1209 | REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07), |
8e6a8d7d | 1210 | /* |
8e6a8d7d | 1211 | * 0x08, VanaHwHPReq2Valid |
8e6a8d7d LJ |
1212 | * 0x20, Vaux1HwHPReq2Valid |
1213 | * 0x40, Vaux2HwHPReq2Valid | |
1214 | * 0x80, Vaux3HwHPReq2Valid | |
1215 | */ | |
ec1ba3e5 | 1216 | REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8), |
8e6a8d7d LJ |
1217 | /* |
1218 | * 0x01, VextSupply1HwHPReq2Valid | |
1219 | * 0x02, VextSupply2HwHPReq2Valid | |
1220 | * 0x04, VextSupply3HwHPReq2Valid | |
8e6a8d7d | 1221 | */ |
ec1ba3e5 | 1222 | REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07), |
8e6a8d7d | 1223 | /* |
8e6a8d7d | 1224 | * 0x20, VanaSwHPReqValid |
8e6a8d7d LJ |
1225 | * 0x80, Vaux1SwHPReqValid |
1226 | */ | |
ec1ba3e5 | 1227 | REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0), |
8e6a8d7d LJ |
1228 | /* |
1229 | * 0x01, Vaux2SwHPReqValid | |
1230 | * 0x02, Vaux3SwHPReqValid | |
1231 | * 0x04, VextSupply1SwHPReqValid | |
1232 | * 0x08, VextSupply2SwHPReqValid | |
1233 | * 0x10, VextSupply3SwHPReqValid | |
8e6a8d7d | 1234 | */ |
ec1ba3e5 | 1235 | REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f), |
8e6a8d7d LJ |
1236 | /* |
1237 | * 0x02, SysClkReq2Valid1 | |
ec1ba3e5 LW |
1238 | * 0x04, SysClkReq3Valid1 |
1239 | * 0x08, SysClkReq4Valid1 | |
1240 | * 0x10, SysClkReq5Valid1 | |
1241 | * 0x20, SysClkReq6Valid1 | |
1242 | * 0x40, SysClkReq7Valid1 | |
8e6a8d7d LJ |
1243 | * 0x80, SysClkReq8Valid1 |
1244 | */ | |
ec1ba3e5 | 1245 | REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe), |
8e6a8d7d LJ |
1246 | /* |
1247 | * 0x02, SysClkReq2Valid2 | |
ec1ba3e5 LW |
1248 | * 0x04, SysClkReq3Valid2 |
1249 | * 0x08, SysClkReq4Valid2 | |
1250 | * 0x10, SysClkReq5Valid2 | |
1251 | * 0x20, SysClkReq6Valid2 | |
1252 | * 0x40, SysClkReq7Valid2 | |
8e6a8d7d LJ |
1253 | * 0x80, SysClkReq8Valid2 |
1254 | */ | |
ec1ba3e5 | 1255 | REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe), |
8e6a8d7d LJ |
1256 | /* |
1257 | * 0x02, VTVoutEna | |
1258 | * 0x04, Vintcore12Ena | |
1259 | * 0x38, Vintcore12Sel | |
1260 | * 0x40, Vintcore12LP | |
1261 | * 0x80, VTVoutLP | |
1262 | */ | |
ec1ba3e5 | 1263 | REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe), |
8e6a8d7d LJ |
1264 | /* |
1265 | * 0x02, VaudioEna | |
1266 | * 0x04, VdmicEna | |
1267 | * 0x08, Vamic1Ena | |
1268 | * 0x10, Vamic2Ena | |
1269 | */ | |
ec1ba3e5 | 1270 | REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e), |
8e6a8d7d LJ |
1271 | /* |
1272 | * 0x01, Vamic1_dzout | |
1273 | * 0x02, Vamic2_dzout | |
1274 | */ | |
ec1ba3e5 | 1275 | REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), |
8e6a8d7d | 1276 | /* |
ec1ba3e5 LW |
1277 | * 0x03, VpllRegu (NOTE! PRCMU register bits) |
1278 | * 0x0c, VanaRegu | |
8e6a8d7d | 1279 | */ |
ec1ba3e5 | 1280 | REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f), |
8e6a8d7d | 1281 | /* |
ec1ba3e5 LW |
1282 | * 0x01, VrefDDREna |
1283 | * 0x02, VrefDDRSleepMode | |
8e6a8d7d | 1284 | */ |
ec1ba3e5 | 1285 | REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03), |
8e6a8d7d LJ |
1286 | /* |
1287 | * 0x03, VextSupply1Regu | |
1288 | * 0x0c, VextSupply2Regu | |
1289 | * 0x30, VextSupply3Regu | |
1290 | * 0x40, ExtSupply2Bypass | |
1291 | * 0x80, ExtSupply3Bypass | |
1292 | */ | |
ec1ba3e5 | 1293 | REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff), |
8e6a8d7d LJ |
1294 | /* |
1295 | * 0x03, Vaux1Regu | |
1296 | * 0x0c, Vaux2Regu | |
1297 | */ | |
ec1ba3e5 | 1298 | REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f), |
8e6a8d7d | 1299 | /* |
8e6a8d7d LJ |
1300 | * 0x03, Vaux3Regu |
1301 | */ | |
ec1ba3e5 | 1302 | REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03), |
8e6a8d7d LJ |
1303 | /* |
1304 | * 0x0f, Vaux1Sel | |
1305 | */ | |
ec1ba3e5 | 1306 | REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f), |
8e6a8d7d LJ |
1307 | /* |
1308 | * 0x0f, Vaux2Sel | |
1309 | */ | |
ec1ba3e5 | 1310 | REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f), |
8e6a8d7d LJ |
1311 | /* |
1312 | * 0x07, Vaux3Sel | |
8e6a8d7d | 1313 | */ |
ec1ba3e5 | 1314 | REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07), |
8e6a8d7d LJ |
1315 | /* |
1316 | * 0x01, VextSupply12LP | |
1317 | */ | |
ec1ba3e5 | 1318 | REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01), |
8e6a8d7d | 1319 | /* |
8e6a8d7d LJ |
1320 | * 0x04, Vaux1Disch |
1321 | * 0x08, Vaux2Disch | |
1322 | * 0x10, Vaux3Disch | |
1323 | * 0x20, Vintcore12Disch | |
1324 | * 0x40, VTVoutDisch | |
1325 | * 0x80, VaudioDisch | |
1326 | */ | |
ec1ba3e5 | 1327 | REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc), |
8e6a8d7d | 1328 | /* |
8e6a8d7d LJ |
1329 | * 0x02, VanaDisch |
1330 | * 0x04, VdmicPullDownEna | |
8e6a8d7d LJ |
1331 | * 0x10, VdmicDisch |
1332 | */ | |
ec1ba3e5 | 1333 | REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16), |
8e6a8d7d LJ |
1334 | }; |
1335 | ||
ec1ba3e5 LW |
1336 | /* AB8505 register init */ |
1337 | static struct ab8500_reg_init ab8505_reg_init[] = { | |
ae0a9a3e LJ |
1338 | /* |
1339 | * 0x03, VarmRequestCtrl | |
ec1ba3e5 LW |
1340 | * 0x0c, VsmpsCRequestCtrl |
1341 | * 0x30, VsmpsARequestCtrl | |
1342 | * 0xc0, VsmpsBRequestCtrl | |
ae0a9a3e | 1343 | */ |
ec1ba3e5 | 1344 | REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff), |
ae0a9a3e | 1345 | /* |
ec1ba3e5 | 1346 | * 0x03, VsafeRequestCtrl |
ae0a9a3e LJ |
1347 | * 0x0c, VpllRequestCtrl |
1348 | * 0x30, VanaRequestCtrl | |
ae0a9a3e | 1349 | */ |
ec1ba3e5 | 1350 | REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f), |
ae0a9a3e | 1351 | /* |
ae0a9a3e LJ |
1352 | * 0x30, Vaux1RequestCtrl |
1353 | * 0xc0, Vaux2RequestCtrl | |
1354 | */ | |
ec1ba3e5 | 1355 | REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0), |
ae0a9a3e LJ |
1356 | /* |
1357 | * 0x03, Vaux3RequestCtrl | |
1358 | * 0x04, SwHPReq | |
1359 | */ | |
ec1ba3e5 | 1360 | REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07), |
ae0a9a3e | 1361 | /* |
ec1ba3e5 LW |
1362 | * 0x01, VsmpsASysClkReq1HPValid |
1363 | * 0x02, VsmpsBSysClkReq1HPValid | |
1364 | * 0x04, VsafeSysClkReq1HPValid | |
ae0a9a3e LJ |
1365 | * 0x08, VanaSysClkReq1HPValid |
1366 | * 0x10, VpllSysClkReq1HPValid | |
1367 | * 0x20, Vaux1SysClkReq1HPValid | |
1368 | * 0x40, Vaux2SysClkReq1HPValid | |
1369 | * 0x80, Vaux3SysClkReq1HPValid | |
1370 | */ | |
ec1ba3e5 | 1371 | REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff), |
ae0a9a3e | 1372 | /* |
ec1ba3e5 | 1373 | * 0x01, VsmpsCSysClkReq1HPValid |
ae0a9a3e LJ |
1374 | * 0x02, VarmSysClkReq1HPValid |
1375 | * 0x04, VbbSysClkReq1HPValid | |
ec1ba3e5 | 1376 | * 0x08, VsmpsMSysClkReq1HPValid |
ae0a9a3e | 1377 | */ |
ec1ba3e5 | 1378 | REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f), |
ae0a9a3e | 1379 | /* |
ec1ba3e5 LW |
1380 | * 0x01, VsmpsAHwHPReq1Valid |
1381 | * 0x02, VsmpsBHwHPReq1Valid | |
1382 | * 0x04, VsafeHwHPReq1Valid | |
ae0a9a3e LJ |
1383 | * 0x08, VanaHwHPReq1Valid |
1384 | * 0x10, VpllHwHPReq1Valid | |
1385 | * 0x20, Vaux1HwHPReq1Valid | |
1386 | * 0x40, Vaux2HwHPReq1Valid | |
1387 | * 0x80, Vaux3HwHPReq1Valid | |
1388 | */ | |
ec1ba3e5 | 1389 | REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff), |
ae0a9a3e | 1390 | /* |
ec1ba3e5 | 1391 | * 0x08, VsmpsMHwHPReq1Valid |
ae0a9a3e | 1392 | */ |
ec1ba3e5 | 1393 | REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08), |
ae0a9a3e | 1394 | /* |
ec1ba3e5 LW |
1395 | * 0x01, VsmpsAHwHPReq2Valid |
1396 | * 0x02, VsmpsBHwHPReq2Valid | |
1397 | * 0x04, VsafeHwHPReq2Valid | |
ae0a9a3e LJ |
1398 | * 0x08, VanaHwHPReq2Valid |
1399 | * 0x10, VpllHwHPReq2Valid | |
1400 | * 0x20, Vaux1HwHPReq2Valid | |
1401 | * 0x40, Vaux2HwHPReq2Valid | |
1402 | * 0x80, Vaux3HwHPReq2Valid | |
1403 | */ | |
ec1ba3e5 | 1404 | REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff), |
ae0a9a3e | 1405 | /* |
ec1ba3e5 | 1406 | * 0x08, VsmpsMHwHPReq2Valid |
ae0a9a3e | 1407 | */ |
ec1ba3e5 | 1408 | REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08), |
ae0a9a3e | 1409 | /* |
ec1ba3e5 | 1410 | * 0x01, VsmpsCSwHPReqValid |
ae0a9a3e | 1411 | * 0x02, VarmSwHPReqValid |
ec1ba3e5 LW |
1412 | * 0x04, VsmpsASwHPReqValid |
1413 | * 0x08, VsmpsBSwHPReqValid | |
1414 | * 0x10, VsafeSwHPReqValid | |
ae0a9a3e LJ |
1415 | * 0x20, VanaSwHPReqValid |
1416 | * 0x40, VpllSwHPReqValid | |
1417 | * 0x80, Vaux1SwHPReqValid | |
1418 | */ | |
ec1ba3e5 | 1419 | REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff), |
ae0a9a3e LJ |
1420 | /* |
1421 | * 0x01, Vaux2SwHPReqValid | |
1422 | * 0x02, Vaux3SwHPReqValid | |
ec1ba3e5 | 1423 | * 0x20, VsmpsMSwHPReqValid |
ae0a9a3e | 1424 | */ |
ec1ba3e5 | 1425 | REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23), |
ae0a9a3e LJ |
1426 | /* |
1427 | * 0x02, SysClkReq2Valid1 | |
ec1ba3e5 LW |
1428 | * 0x04, SysClkReq3Valid1 |
1429 | * 0x08, SysClkReq4Valid1 | |
ae0a9a3e | 1430 | */ |
ec1ba3e5 | 1431 | REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e), |
ae0a9a3e LJ |
1432 | /* |
1433 | * 0x02, SysClkReq2Valid2 | |
ec1ba3e5 LW |
1434 | * 0x04, SysClkReq3Valid2 |
1435 | * 0x08, SysClkReq4Valid2 | |
ae0a9a3e | 1436 | */ |
ec1ba3e5 | 1437 | REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e), |
ae0a9a3e LJ |
1438 | /* |
1439 | * 0x01, Vaux4SwHPReqValid | |
1440 | * 0x02, Vaux4HwHPReq2Valid | |
1441 | * 0x04, Vaux4HwHPReq1Valid | |
1442 | * 0x08, Vaux4SysClkReq1HPValid | |
1443 | */ | |
ec1ba3e5 | 1444 | REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f), |
ae0a9a3e | 1445 | /* |
ec1ba3e5 LW |
1446 | * 0x02, VadcEna |
1447 | * 0x04, VintCore12Ena | |
1448 | * 0x38, VintCore12Sel | |
1449 | * 0x40, VintCore12LP | |
1450 | * 0x80, VadcLP | |
ae0a9a3e | 1451 | */ |
ec1ba3e5 | 1452 | REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe), |
ae0a9a3e LJ |
1453 | /* |
1454 | * 0x02, VaudioEna | |
1455 | * 0x04, VdmicEna | |
1456 | * 0x08, Vamic1Ena | |
1457 | * 0x10, Vamic2Ena | |
ae0a9a3e | 1458 | */ |
ec1ba3e5 | 1459 | REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e), |
ae0a9a3e LJ |
1460 | /* |
1461 | * 0x01, Vamic1_dzout | |
1462 | * 0x02, Vamic2_dzout | |
1463 | */ | |
ec1ba3e5 | 1464 | REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03), |
ae0a9a3e | 1465 | /* |
ec1ba3e5 LW |
1466 | * 0x03, VsmpsARegu |
1467 | * 0x0c, VsmpsASelCtrl | |
1468 | * 0x10, VsmpsAAutoMode | |
1469 | * 0x20, VsmpsAPWMMode | |
ae0a9a3e | 1470 | */ |
ec1ba3e5 | 1471 | REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f), |
ae0a9a3e | 1472 | /* |
ec1ba3e5 LW |
1473 | * 0x03, VsmpsBRegu |
1474 | * 0x0c, VsmpsBSelCtrl | |
1475 | * 0x10, VsmpsBAutoMode | |
1476 | * 0x20, VsmpsBPWMMode | |
ae0a9a3e | 1477 | */ |
ec1ba3e5 | 1478 | REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f), |
ae0a9a3e | 1479 | /* |
ec1ba3e5 LW |
1480 | * 0x03, VsafeRegu |
1481 | * 0x0c, VsafeSelCtrl | |
1482 | * 0x10, VsafeAutoMode | |
1483 | * 0x20, VsafePWMMode | |
ae0a9a3e | 1484 | */ |
ec1ba3e5 | 1485 | REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f), |
ae0a9a3e | 1486 | /* |
ec1ba3e5 | 1487 | * 0x03, VpllRegu (NOTE! PRCMU register bits) |
ae0a9a3e LJ |
1488 | * 0x0c, VanaRegu |
1489 | */ | |
ec1ba3e5 | 1490 | REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f), |
ae0a9a3e LJ |
1491 | /* |
1492 | * 0x03, VextSupply1Regu | |
1493 | * 0x0c, VextSupply2Regu | |
1494 | * 0x30, VextSupply3Regu | |
1495 | * 0x40, ExtSupply2Bypass | |
1496 | * 0x80, ExtSupply3Bypass | |
1497 | */ | |
ec1ba3e5 | 1498 | REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff), |
ae0a9a3e LJ |
1499 | /* |
1500 | * 0x03, Vaux1Regu | |
1501 | * 0x0c, Vaux2Regu | |
1502 | */ | |
ec1ba3e5 | 1503 | REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f), |
ae0a9a3e | 1504 | /* |
ec1ba3e5 LW |
1505 | * 0x0f, Vaux3Regu |
1506 | */ | |
1507 | REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f), | |
1508 | /* | |
1509 | * 0x3f, VsmpsASel1 | |
ae0a9a3e | 1510 | */ |
ec1ba3e5 | 1511 | REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f), |
ae0a9a3e | 1512 | /* |
ec1ba3e5 | 1513 | * 0x3f, VsmpsASel2 |
ae0a9a3e | 1514 | */ |
ec1ba3e5 | 1515 | REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f), |
ae0a9a3e | 1516 | /* |
ec1ba3e5 | 1517 | * 0x3f, VsmpsASel3 |
ae0a9a3e | 1518 | */ |
ec1ba3e5 | 1519 | REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f), |
ae0a9a3e | 1520 | /* |
ec1ba3e5 | 1521 | * 0x3f, VsmpsBSel1 |
ae0a9a3e | 1522 | */ |
ec1ba3e5 | 1523 | REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f), |
ae0a9a3e | 1524 | /* |
ec1ba3e5 | 1525 | * 0x3f, VsmpsBSel2 |
ae0a9a3e | 1526 | */ |
ec1ba3e5 | 1527 | REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f), |
ae0a9a3e | 1528 | /* |
ec1ba3e5 | 1529 | * 0x3f, VsmpsBSel3 |
ae0a9a3e | 1530 | */ |
ec1ba3e5 | 1531 | REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f), |
ae0a9a3e | 1532 | /* |
ec1ba3e5 | 1533 | * 0x7f, VsafeSel1 |
ae0a9a3e | 1534 | */ |
ec1ba3e5 | 1535 | REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f), |
ae0a9a3e | 1536 | /* |
ec1ba3e5 | 1537 | * 0x3f, VsafeSel2 |
ae0a9a3e | 1538 | */ |
ec1ba3e5 | 1539 | REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f), |
ae0a9a3e | 1540 | /* |
ec1ba3e5 | 1541 | * 0x3f, VsafeSel3 |
ae0a9a3e | 1542 | */ |
ec1ba3e5 | 1543 | REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f), |
ae0a9a3e LJ |
1544 | /* |
1545 | * 0x0f, Vaux1Sel | |
1546 | */ | |
ec1ba3e5 | 1547 | REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f), |
ae0a9a3e LJ |
1548 | /* |
1549 | * 0x0f, Vaux2Sel | |
1550 | */ | |
ec1ba3e5 | 1551 | REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f), |
ae0a9a3e LJ |
1552 | /* |
1553 | * 0x07, Vaux3Sel | |
ec1ba3e5 | 1554 | * 0x30, VRF1Sel |
ae0a9a3e | 1555 | */ |
ec1ba3e5 | 1556 | REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37), |
ae0a9a3e LJ |
1557 | /* |
1558 | * 0x03, Vaux4RequestCtrl | |
1559 | */ | |
ec1ba3e5 | 1560 | REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03), |
ae0a9a3e LJ |
1561 | /* |
1562 | * 0x03, Vaux4Regu | |
1563 | */ | |
ec1ba3e5 | 1564 | REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03), |
ae0a9a3e LJ |
1565 | /* |
1566 | * 0x0f, Vaux4Sel | |
1567 | */ | |
ec1ba3e5 | 1568 | REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f), |
ae0a9a3e | 1569 | /* |
ae0a9a3e LJ |
1570 | * 0x04, Vaux1Disch |
1571 | * 0x08, Vaux2Disch | |
1572 | * 0x10, Vaux3Disch | |
1573 | * 0x20, Vintcore12Disch | |
1574 | * 0x40, VTVoutDisch | |
1575 | * 0x80, VaudioDisch | |
1576 | */ | |
ec1ba3e5 | 1577 | REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc), |
ae0a9a3e LJ |
1578 | /* |
1579 | * 0x02, VanaDisch | |
1580 | * 0x04, VdmicPullDownEna | |
ae0a9a3e LJ |
1581 | * 0x10, VdmicDisch |
1582 | */ | |
ec1ba3e5 | 1583 | REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16), |
ae0a9a3e LJ |
1584 | /* |
1585 | * 0x01, Vaux4Disch | |
1586 | */ | |
ec1ba3e5 LW |
1587 | REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01), |
1588 | /* | |
1589 | * 0x07, Vaux5Sel | |
1590 | * 0x08, Vaux5LP | |
1591 | * 0x10, Vaux5Ena | |
1592 | * 0x20, Vaux5Disch | |
1593 | * 0x40, Vaux5DisSfst | |
1594 | * 0x80, Vaux5DisPulld | |
1595 | */ | |
1596 | REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff), | |
ae0a9a3e | 1597 | /* |
ec1ba3e5 LW |
1598 | * 0x07, Vaux6Sel |
1599 | * 0x08, Vaux6LP | |
1600 | * 0x10, Vaux6Ena | |
1601 | * 0x80, Vaux6DisPulld | |
ae0a9a3e | 1602 | */ |
ec1ba3e5 | 1603 | REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f), |
ae0a9a3e LJ |
1604 | }; |
1605 | ||
b54969ac | 1606 | static struct of_regulator_match ab8500_regulator_match[] = { |
7e715b95 LJ |
1607 | { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, }, |
1608 | { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, }, | |
1609 | { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, }, | |
1610 | { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, }, | |
1611 | { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, }, | |
7e715b95 LJ |
1612 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, }, |
1613 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, }, | |
5510ed9f | 1614 | { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, }, |
7e715b95 LJ |
1615 | { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, }, |
1616 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, }, | |
3a8334b9 LJ |
1617 | }; |
1618 | ||
547f384f LJ |
1619 | static struct of_regulator_match ab8505_regulator_match[] = { |
1620 | { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, }, | |
1621 | { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, }, | |
1622 | { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, }, | |
1623 | { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, }, | |
1624 | { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, }, | |
1625 | { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, }, | |
1626 | { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, }, | |
1627 | { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, }, | |
1628 | { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, }, | |
1629 | { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, }, | |
5510ed9f | 1630 | { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, }, |
547f384f LJ |
1631 | { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, }, |
1632 | { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, }, | |
1633 | }; | |
1634 | ||
da45edc7 LJ |
1635 | static struct { |
1636 | struct ab8500_regulator_info *info; | |
1637 | int info_size; | |
1638 | struct ab8500_reg_init *init; | |
1639 | int init_size; | |
1640 | struct of_regulator_match *match; | |
1641 | int match_size; | |
1642 | } abx500_regulator; | |
1643 | ||
33aeb49e LJ |
1644 | static void abx500_get_regulator_info(struct ab8500 *ab8500) |
1645 | { | |
ec1ba3e5 | 1646 | if (is_ab8505(ab8500)) { |
33aeb49e LJ |
1647 | abx500_regulator.info = ab8505_regulator_info; |
1648 | abx500_regulator.info_size = ARRAY_SIZE(ab8505_regulator_info); | |
1649 | abx500_regulator.init = ab8505_reg_init; | |
1650 | abx500_regulator.init_size = AB8505_NUM_REGULATOR_REGISTERS; | |
1651 | abx500_regulator.match = ab8505_regulator_match; | |
1652 | abx500_regulator.match_size = ARRAY_SIZE(ab8505_regulator_match); | |
33aeb49e LJ |
1653 | } else { |
1654 | abx500_regulator.info = ab8500_regulator_info; | |
1655 | abx500_regulator.info_size = ARRAY_SIZE(ab8500_regulator_info); | |
1656 | abx500_regulator.init = ab8500_reg_init; | |
1657 | abx500_regulator.init_size = AB8500_NUM_REGULATOR_REGISTERS; | |
1658 | abx500_regulator.match = ab8500_regulator_match; | |
1659 | abx500_regulator.match_size = ARRAY_SIZE(ab8500_regulator_match); | |
1660 | } | |
1661 | } | |
1662 | ||
da45edc7 LJ |
1663 | static int ab8500_regulator_register(struct platform_device *pdev, |
1664 | struct regulator_init_data *init_data, | |
1665 | int id, struct device_node *np) | |
1666 | { | |
1667 | struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); | |
1668 | struct ab8500_regulator_info *info = NULL; | |
1669 | struct regulator_config config = { }; | |
7c6b8e3b | 1670 | struct regulator_dev *rdev; |
da45edc7 LJ |
1671 | |
1672 | /* assign per-regulator data */ | |
1673 | info = &abx500_regulator.info[id]; | |
1674 | info->dev = &pdev->dev; | |
1675 | ||
1676 | config.dev = &pdev->dev; | |
1677 | config.init_data = init_data; | |
1678 | config.driver_data = info; | |
1679 | config.of_node = np; | |
1680 | ||
1681 | /* fix for hardware before ab8500v2.0 */ | |
1682 | if (is_ab8500_1p1_or_earlier(ab8500)) { | |
1683 | if (info->desc.id == AB8500_LDO_AUX3) { | |
1684 | info->desc.n_voltages = | |
1685 | ARRAY_SIZE(ldo_vauxn_voltages); | |
1686 | info->desc.volt_table = ldo_vauxn_voltages; | |
1687 | info->voltage_mask = 0xf; | |
1688 | } | |
1689 | } | |
1690 | ||
1691 | /* register regulator with framework */ | |
7c6b8e3b AL |
1692 | rdev = devm_regulator_register(&pdev->dev, &info->desc, &config); |
1693 | if (IS_ERR(rdev)) { | |
da45edc7 LJ |
1694 | dev_err(&pdev->dev, "failed to register regulator %s\n", |
1695 | info->desc.name); | |
7c6b8e3b | 1696 | return PTR_ERR(rdev); |
da45edc7 LJ |
1697 | } |
1698 | ||
1699 | return 0; | |
1700 | } | |
1701 | ||
a5023574 | 1702 | static int ab8500_regulator_probe(struct platform_device *pdev) |
c789ca20 SI |
1703 | { |
1704 | struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent); | |
3a8334b9 | 1705 | struct device_node *np = pdev->dev.of_node; |
a5c1a416 AL |
1706 | struct of_regulator_match *match; |
1707 | int err, i; | |
b54969ac | 1708 | |
33aeb49e LJ |
1709 | if (!ab8500) { |
1710 | dev_err(&pdev->dev, "null mfd parent\n"); | |
1711 | return -EINVAL; | |
8e6a8d7d | 1712 | } |
c789ca20 | 1713 | |
33aeb49e LJ |
1714 | abx500_get_regulator_info(ab8500); |
1715 | ||
34c040ce LW |
1716 | err = of_regulator_match(&pdev->dev, np, |
1717 | abx500_regulator.match, | |
1718 | abx500_regulator.match_size); | |
1719 | if (err < 0) { | |
1720 | dev_err(&pdev->dev, | |
1721 | "Error parsing regulator init data: %d\n", err); | |
da0b0c47 | 1722 | return err; |
c789ca20 | 1723 | } |
a5c1a416 AL |
1724 | |
1725 | match = abx500_regulator.match; | |
1726 | for (i = 0; i < abx500_regulator.info_size; i++) { | |
1727 | err = ab8500_regulator_register(pdev, match[i].init_data, i, | |
1728 | match[i].of_node); | |
1729 | if (err) | |
1730 | return err; | |
1731 | } | |
1732 | ||
1733 | return 0; | |
c789ca20 SI |
1734 | } |
1735 | ||
c789ca20 SI |
1736 | static struct platform_driver ab8500_regulator_driver = { |
1737 | .probe = ab8500_regulator_probe, | |
c789ca20 SI |
1738 | .driver = { |
1739 | .name = "ab8500-regulator", | |
c789ca20 SI |
1740 | }, |
1741 | }; | |
1742 | ||
1743 | static int __init ab8500_regulator_init(void) | |
1744 | { | |
1745 | int ret; | |
1746 | ||
1747 | ret = platform_driver_register(&ab8500_regulator_driver); | |
1748 | if (ret != 0) | |
1749 | pr_err("Failed to register ab8500 regulator: %d\n", ret); | |
1750 | ||
1751 | return ret; | |
1752 | } | |
1753 | subsys_initcall(ab8500_regulator_init); | |
1754 | ||
1755 | static void __exit ab8500_regulator_exit(void) | |
1756 | { | |
1757 | platform_driver_unregister(&ab8500_regulator_driver); | |
1758 | } | |
1759 | module_exit(ab8500_regulator_exit); | |
1760 | ||
1761 | MODULE_LICENSE("GPL v2"); | |
1762 | MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>"); | |
732805a5 | 1763 | MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>"); |
547f384f | 1764 | MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>"); |
c789ca20 SI |
1765 | MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC"); |
1766 | MODULE_ALIAS("platform:ab8500-regulator"); |