Merge tag 'thermal-v5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/therma...
[linux-block.git] / drivers / pwm / pwm-vt8500.c
CommitLineData
9c92ab61 1// SPDX-License-Identifier: GPL-2.0-only
21f47fbc 2/*
261995dd 3 * drivers/pwm/pwm-vt8500.c
21f47fbc 4 *
63e1ed23
TP
5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
21f47fbc
AC
7 */
8
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/platform_device.h>
12#include <linux/slab.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/pwm.h>
16#include <linux/delay.h>
63e1ed23 17#include <linux/clk.h>
21f47fbc
AC
18
19#include <asm/div64.h>
20
63e1ed23
TP
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/of_address.h>
24
25/*
26 * SoC architecture allocates register space for 4 PWMs but only
27 * 2 are currently implemented.
28 */
29#define VT8500_NR_PWMS 2
21f47fbc 30
8ab432ca
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31#define REG_CTRL(pwm) (((pwm) << 4) + 0x00)
32#define REG_SCALAR(pwm) (((pwm) << 4) + 0x04)
33#define REG_PERIOD(pwm) (((pwm) << 4) + 0x08)
34#define REG_DUTY(pwm) (((pwm) << 4) + 0x0C)
35#define REG_STATUS 0x40
36
37#define CTRL_ENABLE BIT(0)
38#define CTRL_INVERT BIT(1)
39#define CTRL_AUTOLOAD BIT(2)
40#define CTRL_STOP_IMM BIT(3)
41#define CTRL_LOAD_PRESCALE BIT(4)
42#define CTRL_LOAD_PERIOD BIT(5)
43
44#define STATUS_CTRL_UPDATE BIT(0)
45#define STATUS_SCALAR_UPDATE BIT(1)
46#define STATUS_PERIOD_UPDATE BIT(2)
47#define STATUS_DUTY_UPDATE BIT(3)
48#define STATUS_ALL_UPDATE 0x0F
49
a245cceb
SH
50struct vt8500_chip {
51 struct pwm_chip chip;
52 void __iomem *base;
63e1ed23 53 struct clk *clk;
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AC
54};
55
a245cceb
SH
56#define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip)
57
21f47fbc 58#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
8ab432ca 59static inline void pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask)
21f47fbc
AC
60{
61 int loops = msecs_to_loops(10);
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TP
62 u32 mask = bitmask << (nr << 8);
63
64 while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
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65 cpu_relax();
66
67 if (unlikely(!loops))
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TP
68 dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n",
69 mask);
21f47fbc
AC
70}
71
a245cceb
SH
72static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
73 int duty_ns, int period_ns)
21f47fbc 74{
a245cceb 75 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
21f47fbc
AC
76 unsigned long long c;
77 unsigned long period_cycles, prescale, pv, dc;
422470a8 78 int err;
8ab432ca 79 u32 val;
422470a8
TP
80
81 err = clk_enable(vt8500->clk);
82 if (err < 0) {
83 dev_err(chip->dev, "failed to enable clock\n");
84 return err;
85 }
21f47fbc 86
63e1ed23 87 c = clk_get_rate(vt8500->clk);
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AC
88 c = c * period_ns;
89 do_div(c, 1000000000);
90 period_cycles = c;
91
92 if (period_cycles < 1)
93 period_cycles = 1;
94 prescale = (period_cycles - 1) / 4096;
95 pv = period_cycles / (prescale + 1) - 1;
96 if (pv > 4095)
97 pv = 4095;
98
422470a8
TP
99 if (prescale > 1023) {
100 clk_disable(vt8500->clk);
21f47fbc 101 return -EINVAL;
422470a8 102 }
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AC
103
104 c = (unsigned long long)pv * duty_ns;
105 do_div(c, period_ns);
106 dc = c;
107
8ab432ca
TP
108 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm));
109 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE);
21f47fbc 110
8ab432ca
TP
111 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm));
112 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE);
21f47fbc 113
8ab432ca
TP
114 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
115 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE);
21f47fbc 116
8ab432ca
TP
117 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
118 val |= CTRL_AUTOLOAD;
119 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
120 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
21f47fbc 121
422470a8 122 clk_disable(vt8500->clk);
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AC
123 return 0;
124}
21f47fbc 125
a245cceb 126static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
21f47fbc 127{
a245cceb 128 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
8ab432ca
TP
129 int err;
130 u32 val;
21f47fbc 131
63e1ed23 132 err = clk_enable(vt8500->clk);
2f9569f7 133 if (err < 0) {
63e1ed23
TP
134 dev_err(chip->dev, "failed to enable clock\n");
135 return err;
422470a8 136 }
63e1ed23 137
8ab432ca
TP
138 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
139 val |= CTRL_ENABLE;
140 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
141 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
142
a245cceb 143 return 0;
21f47fbc 144}
21f47fbc 145
a245cceb 146static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
21f47fbc 147{
a245cceb 148 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
8ab432ca 149 u32 val;
21f47fbc 150
8ab432ca
TP
151 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
152 val &= ~CTRL_ENABLE;
153 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
154 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
63e1ed23
TP
155
156 clk_disable(vt8500->clk);
21f47fbc 157}
21f47fbc 158
3ccb1c17
TP
159static int vt8500_pwm_set_polarity(struct pwm_chip *chip,
160 struct pwm_device *pwm,
161 enum pwm_polarity polarity)
162{
163 struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
164 u32 val;
165
166 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
167
168 if (polarity == PWM_POLARITY_INVERSED)
169 val |= CTRL_INVERT;
170 else
171 val &= ~CTRL_INVERT;
172
173 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
174 pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
175
176 return 0;
177}
178
b2ec9efc 179static const struct pwm_ops vt8500_pwm_ops = {
a245cceb
SH
180 .enable = vt8500_pwm_enable,
181 .disable = vt8500_pwm_disable,
182 .config = vt8500_pwm_config,
3ccb1c17 183 .set_polarity = vt8500_pwm_set_polarity,
a245cceb
SH
184 .owner = THIS_MODULE,
185};
21f47fbc 186
63e1ed23
TP
187static const struct of_device_id vt8500_pwm_dt_ids[] = {
188 { .compatible = "via,vt8500-pwm", },
189 { /* Sentinel */ }
190};
191MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids);
192
193static int vt8500_pwm_probe(struct platform_device *pdev)
21f47fbc 194{
a245cceb 195 struct vt8500_chip *chip;
63e1ed23 196 struct device_node *np = pdev->dev.of_node;
a245cceb 197 int ret;
21f47fbc 198
63e1ed23
TP
199 if (!np) {
200 dev_err(&pdev->dev, "invalid devicetree node\n");
201 return -EINVAL;
202 }
203
261995dd 204 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
b9f87404 205 if (chip == NULL)
21f47fbc 206 return -ENOMEM;
21f47fbc 207
a245cceb
SH
208 chip->chip.dev = &pdev->dev;
209 chip->chip.ops = &vt8500_pwm_ops;
a245cceb 210 chip->chip.npwm = VT8500_NR_PWMS;
21f47fbc 211
63e1ed23
TP
212 chip->clk = devm_clk_get(&pdev->dev, NULL);
213 if (IS_ERR(chip->clk)) {
214 dev_err(&pdev->dev, "clock source not specified\n");
215 return PTR_ERR(chip->clk);
216 }
217
4906bf54 218 chip->base = devm_platform_ioremap_resource(pdev, 0);
6d4294d1
TR
219 if (IS_ERR(chip->base))
220 return PTR_ERR(chip->base);
21f47fbc 221
63e1ed23
TP
222 ret = clk_prepare(chip->clk);
223 if (ret < 0) {
224 dev_err(&pdev->dev, "failed to prepare clock\n");
225 return ret;
226 }
227
a245cceb 228 ret = pwmchip_add(&chip->chip);
63e1ed23
TP
229 if (ret < 0) {
230 dev_err(&pdev->dev, "failed to add PWM chip\n");
0bd24f9b 231 clk_unprepare(chip->clk);
261995dd 232 return ret;
63e1ed23 233 }
21f47fbc 234
a245cceb
SH
235 platform_set_drvdata(pdev, chip);
236 return ret;
21f47fbc
AC
237}
238
63e1ed23 239static int vt8500_pwm_remove(struct platform_device *pdev)
21f47fbc 240{
fb2cb3bf 241 struct vt8500_chip *chip = platform_get_drvdata(pdev);
21f47fbc 242
868f13bd 243 pwmchip_remove(&chip->chip);
21f47fbc 244
63e1ed23
TP
245 clk_unprepare(chip->clk);
246
868f13bd 247 return 0;
21f47fbc
AC
248}
249
63e1ed23
TP
250static struct platform_driver vt8500_pwm_driver = {
251 .probe = vt8500_pwm_probe,
252 .remove = vt8500_pwm_remove,
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AC
253 .driver = {
254 .name = "vt8500-pwm",
63e1ed23 255 .of_match_table = vt8500_pwm_dt_ids,
21f47fbc 256 },
21f47fbc 257};
63e1ed23 258module_platform_driver(vt8500_pwm_driver);
21f47fbc 259
63e1ed23
TP
260MODULE_DESCRIPTION("VT8500 PWM Driver");
261MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
262MODULE_LICENSE("GPL v2");