[linux-2.6-block.git] / drivers / pwm / pwm-vt8500.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * drivers/pwm/pwm-vt8500.c
 *
 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
 */

#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/pwm.h>
#include <linux/delay.h>
#include <linux/clk.h>

#include <asm/div64.h>

/*
 * SoC architecture allocates register space for 4 PWMs but only
 * 2 are currently implemented.
 */
#define VT8500_NR_PWMS	2

#define REG_CTRL(pwm)		(((pwm) << 4) + 0x00)
#define REG_SCALAR(pwm)		(((pwm) << 4) + 0x04)
#define REG_PERIOD(pwm)		(((pwm) << 4) + 0x08)
#define REG_DUTY(pwm)		(((pwm) << 4) + 0x0C)
#define REG_STATUS		0x40

#define CTRL_ENABLE		BIT(0)
#define CTRL_INVERT		BIT(1)
#define CTRL_AUTOLOAD		BIT(2)
#define CTRL_STOP_IMM		BIT(3)
#define CTRL_LOAD_PRESCALE	BIT(4)
#define CTRL_LOAD_PERIOD	BIT(5)

#define STATUS_CTRL_UPDATE	BIT(0)
#define STATUS_SCALAR_UPDATE	BIT(1)
#define STATUS_PERIOD_UPDATE	BIT(2)
#define STATUS_DUTY_UPDATE	BIT(3)
#define STATUS_ALL_UPDATE	0x0F

struct vt8500_chip {
	struct pwm_chip chip;
	void __iomem *base;
	struct clk *clk;
};

#define to_vt8500_chip(chip)	container_of(chip, struct vt8500_chip, chip)

#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
static inline void vt8500_pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask)
{
	int loops = msecs_to_loops(10);
	u32 mask = bitmask << (nr << 8);

	while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
		cpu_relax();

	if (unlikely(!loops))
		dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n",
			 mask);
}

static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
		u64 duty_ns, u64 period_ns)
{
	struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
	unsigned long long c;
	unsigned long period_cycles, prescale, pv, dc;
	int err;
	u32 val;

	err = clk_enable(vt8500->clk);
	if (err < 0) {
		dev_err(chip->dev, "failed to enable clock\n");
		return err;
	}

	c = clk_get_rate(vt8500->clk);
	c = c * period_ns;
	do_div(c, 1000000000);
	period_cycles = c;

	if (period_cycles < 1)
		period_cycles = 1;
	prescale = (period_cycles - 1) / 4096;
	pv = period_cycles / (prescale + 1) - 1;
	if (pv > 4095)
		pv = 4095;

	if (prescale > 1023) {
		clk_disable(vt8500->clk);
		return -EINVAL;
	}

	c = (unsigned long long)pv * duty_ns;

	dc = div64_u64(c, period_ns);

	writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm));
	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE);

	writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm));
	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE);

	writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE);

	val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
	val |= CTRL_AUTOLOAD;
	writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);

	clk_disable(vt8500->clk);
	return 0;
}

static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
	int err;
	u32 val;

	err = clk_enable(vt8500->clk);
	if (err < 0) {
		dev_err(chip->dev, "failed to enable clock\n");
		return err;
	}

	val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
	val |= CTRL_ENABLE;
	writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);

	return 0;
}

static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
	u32 val;

	val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
	val &= ~CTRL_ENABLE;
	writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);

	clk_disable(vt8500->clk);
}

static int vt8500_pwm_set_polarity(struct pwm_chip *chip,
				   struct pwm_device *pwm,
				   enum pwm_polarity polarity)
{
	struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
	u32 val;

	val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));

	if (polarity == PWM_POLARITY_INVERSED)
		val |= CTRL_INVERT;
	else
		val &= ~CTRL_INVERT;

	writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);

	return 0;
}

static int vt8500_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			    const struct pwm_state *state)
{
	int err;
	bool enabled = pwm->state.enabled;

	if (state->polarity != pwm->state.polarity) {
		/*
		 * Changing the polarity of a running PWM is only allowed when
		 * the PWM driver implements ->apply().
		 */
		if (enabled) {
			vt8500_pwm_disable(chip, pwm);

			enabled = false;
		}

		err = vt8500_pwm_set_polarity(chip, pwm, state->polarity);
		if (err)
			return err;
	}

	if (!state->enabled) {
		if (enabled)
			vt8500_pwm_disable(chip, pwm);

		return 0;
	}

	/*
	 * We cannot skip calling ->config even if state->period ==
	 * pwm->state.period && state->duty_cycle == pwm->state.duty_cycle
	 * because we might have exited early in the last call to
	 * pwm_apply_might_sleep because of !state->enabled and so the two values in
	 * pwm->state might not be configured in hardware.
	 */
	err = vt8500_pwm_config(chip, pwm, state->duty_cycle, state->period);
	if (err)
		return err;

	if (!enabled)
		err = vt8500_pwm_enable(chip, pwm);

	return err;
}

static const struct pwm_ops vt8500_pwm_ops = {
	.apply = vt8500_pwm_apply,
};

static const struct of_device_id vt8500_pwm_dt_ids[] = {
	{ .compatible = "via,vt8500-pwm", },
	{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids);

static int vt8500_pwm_probe(struct platform_device *pdev)
{
	struct vt8500_chip *vt8500;
	struct device_node *np = pdev->dev.of_node;
	int ret;

	if (!np)
		return dev_err_probe(&pdev->dev, -EINVAL, "invalid devicetree node\n");

	vt8500 = devm_kzalloc(&pdev->dev, sizeof(*vt8500), GFP_KERNEL);
	if (vt8500 == NULL)
		return -ENOMEM;

	vt8500->chip.dev = &pdev->dev;
	vt8500->chip.ops = &vt8500_pwm_ops;
	vt8500->chip.npwm = VT8500_NR_PWMS;

	vt8500->clk = devm_clk_get_prepared(&pdev->dev, NULL);
	if (IS_ERR(vt8500->clk))
		return dev_err_probe(&pdev->dev, PTR_ERR(vt8500->clk), "clock source not specified\n");

	vt8500->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(vt8500->base))
		return PTR_ERR(vt8500->base);

	ret = devm_pwmchip_add(&pdev->dev, &vt8500->chip);
	if (ret < 0)
		return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");

	return 0;
}

static struct platform_driver vt8500_pwm_driver = {
	.probe		= vt8500_pwm_probe,
	.driver		= {
		.name	= "vt8500-pwm",
		.of_match_table = vt8500_pwm_dt_ids,
	},
};
module_platform_driver(vt8500_pwm_driver);

MODULE_DESCRIPTION("VT8500 PWM Driver");
MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9c92ab61	1	// SPDX-License-Identifier: GPL-2.0-only
21f47fbc	2	/*
261995dd	3	* drivers/pwm/pwm-vt8500.c
21f47fbc	4	*
63e1ed23 TP	5	* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
63e1ed23 TP	6	* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
21f47fbc AC	7	*/
21f47fbc AC	8
0a41b0c5	9	#include <linux/mod_devicetable.h>
21f47fbc AC	10	#include <linux/module.h>
	11	#include <linux/kernel.h>
	12	#include <linux/platform_device.h>
	13	#include <linux/slab.h>
	14	#include <linux/err.h>
	15	#include <linux/io.h>
	16	#include <linux/pwm.h>
	17	#include <linux/delay.h>
63e1ed23	18	#include <linux/clk.h>
21f47fbc AC	19
	20	#include <asm/div64.h>
	21
63e1ed23 TP	22	/*
	23	* SoC architecture allocates register space for 4 PWMs but only
	24	* 2 are currently implemented.
	25	*/
	26	#define VT8500_NR_PWMS 2
21f47fbc	27
8ab432ca TP	28	#define REG_CTRL(pwm) (((pwm) << 4) + 0x00)
	29	#define REG_SCALAR(pwm) (((pwm) << 4) + 0x04)
	30	#define REG_PERIOD(pwm) (((pwm) << 4) + 0x08)
	31	#define REG_DUTY(pwm) (((pwm) << 4) + 0x0C)
	32	#define REG_STATUS 0x40
	33
	34	#define CTRL_ENABLE BIT(0)
	35	#define CTRL_INVERT BIT(1)
	36	#define CTRL_AUTOLOAD BIT(2)
	37	#define CTRL_STOP_IMM BIT(3)
	38	#define CTRL_LOAD_PRESCALE BIT(4)
	39	#define CTRL_LOAD_PERIOD BIT(5)
	40
	41	#define STATUS_CTRL_UPDATE BIT(0)
	42	#define STATUS_SCALAR_UPDATE BIT(1)
	43	#define STATUS_PERIOD_UPDATE BIT(2)
	44	#define STATUS_DUTY_UPDATE BIT(3)
	45	#define STATUS_ALL_UPDATE 0x0F
	46
a245cceb SH	47	struct vt8500_chip {
	48	struct pwm_chip chip;
	49	void __iomem *base;
63e1ed23	50	struct clk *clk;
21f47fbc AC	51	};
21f47fbc AC	52
a245cceb SH	53	#define to_vt8500_chip(chip) container_of(chip, struct vt8500_chip, chip)
a245cceb SH	54
21f47fbc	55	#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
e9d866d5	56	static inline void vt8500_pwm_busy_wait(struct vt8500_chip *vt8500, int nr, u8 bitmask)
21f47fbc AC	57	{
21f47fbc AC	58	int loops = msecs_to_loops(10);
8ab432ca TP	59	u32 mask = bitmask << (nr << 8);
	60
	61	while ((readl(vt8500->base + REG_STATUS) & mask) && --loops)
21f47fbc AC	62	cpu_relax();
	63
	64	if (unlikely(!loops))
8ab432ca TP	65	dev_warn(vt8500->chip.dev, "Waiting for status bits 0x%x to clear timed out\n",
8ab432ca TP	66	mask);
21f47fbc AC	67	}
21f47fbc AC	68
a245cceb	69	static int vt8500_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
14d89565	70	u64 duty_ns, u64 period_ns)
21f47fbc	71	{
a245cceb	72	struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
21f47fbc AC	73	unsigned long long c;
21f47fbc AC	74	unsigned long period_cycles, prescale, pv, dc;
422470a8	75	int err;
8ab432ca	76	u32 val;
422470a8 TP	77
	78	err = clk_enable(vt8500->clk);
	79	if (err < 0) {
	80	dev_err(chip->dev, "failed to enable clock\n");
	81	return err;
	82	}
21f47fbc	83
63e1ed23	84	c = clk_get_rate(vt8500->clk);
21f47fbc AC	85	c = c * period_ns;
	86	do_div(c, 1000000000);
	87	period_cycles = c;
	88
	89	if (period_cycles < 1)
	90	period_cycles = 1;
	91	prescale = (period_cycles - 1) / 4096;
	92	pv = period_cycles / (prescale + 1) - 1;
	93	if (pv > 4095)
	94	pv = 4095;
	95
422470a8 TP	96	if (prescale > 1023) {
422470a8 TP	97	clk_disable(vt8500->clk);
21f47fbc	98	return -EINVAL;
422470a8	99	}
21f47fbc AC	100
21f47fbc AC	101	c = (unsigned long long)pv * duty_ns;
14d89565 UKK	102
14d89565 UKK	103	dc = div64_u64(c, period_ns);
21f47fbc	104
8ab432ca	105	writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm));
e9d866d5	106	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_SCALAR_UPDATE);
21f47fbc	107
8ab432ca	108	writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm));
e9d866d5	109	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_PERIOD_UPDATE);
21f47fbc	110
8ab432ca	111	writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm));
e9d866d5	112	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_DUTY_UPDATE);
21f47fbc	113
8ab432ca TP	114	val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
	115	val \|= CTRL_AUTOLOAD;
	116	writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
e9d866d5	117	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
21f47fbc	118
422470a8	119	clk_disable(vt8500->clk);
21f47fbc AC	120	return 0;
21f47fbc AC	121	}
21f47fbc	122
a245cceb	123	static int vt8500_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
21f47fbc	124	{
a245cceb	125	struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
8ab432ca TP	126	int err;
8ab432ca TP	127	u32 val;
21f47fbc	128
63e1ed23	129	err = clk_enable(vt8500->clk);
2f9569f7	130	if (err < 0) {
63e1ed23 TP	131	dev_err(chip->dev, "failed to enable clock\n");
63e1ed23 TP	132	return err;
422470a8	133	}
63e1ed23	134
8ab432ca TP	135	val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
	136	val \|= CTRL_ENABLE;
	137	writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
e9d866d5	138	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
8ab432ca	139
a245cceb	140	return 0;
21f47fbc	141	}
21f47fbc	142
a245cceb	143	static void vt8500_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
21f47fbc	144	{
a245cceb	145	struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
8ab432ca	146	u32 val;
21f47fbc	147
8ab432ca TP	148	val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
	149	val &= ~CTRL_ENABLE;
	150	writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
e9d866d5	151	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
63e1ed23 TP	152
63e1ed23 TP	153	clk_disable(vt8500->clk);
21f47fbc	154	}
21f47fbc	155
3ccb1c17 TP	156	static int vt8500_pwm_set_polarity(struct pwm_chip *chip,
	157	struct pwm_device *pwm,
	158	enum pwm_polarity polarity)
	159	{
	160	struct vt8500_chip *vt8500 = to_vt8500_chip(chip);
	161	u32 val;
	162
	163	val = readl(vt8500->base + REG_CTRL(pwm->hwpwm));
	164
	165	if (polarity == PWM_POLARITY_INVERSED)
	166	val \|= CTRL_INVERT;
	167	else
	168	val &= ~CTRL_INVERT;
	169
	170	writel(val, vt8500->base + REG_CTRL(pwm->hwpwm));
e9d866d5	171	vt8500_pwm_busy_wait(vt8500, pwm->hwpwm, STATUS_CTRL_UPDATE);
3ccb1c17 TP	172
	173	return 0;
	174	}
	175
14d89565 UKK	176	static int vt8500_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	177	const struct pwm_state *state)
	178	{
	179	int err;
	180	bool enabled = pwm->state.enabled;
	181
	182	if (state->polarity != pwm->state.polarity) {
	183	/*
	184	* Changing the polarity of a running PWM is only allowed when
	185	* the PWM driver implements ->apply().
	186	*/
	187	if (enabled) {
	188	vt8500_pwm_disable(chip, pwm);
	189
	190	enabled = false;
	191	}
	192
	193	err = vt8500_pwm_set_polarity(chip, pwm, state->polarity);
	194	if (err)
	195	return err;
	196	}
	197
	198	if (!state->enabled) {
	199	if (enabled)
	200	vt8500_pwm_disable(chip, pwm);
	201
	202	return 0;
	203	}
	204
	205	/*
	206	* We cannot skip calling ->config even if state->period ==
	207	* pwm->state.period && state->duty_cycle == pwm->state.duty_cycle
	208	* because we might have exited early in the last call to
c748a6d7	209	* pwm_apply_might_sleep because of !state->enabled and so the two values in
14d89565 UKK	210	* pwm->state might not be configured in hardware.
14d89565 UKK	211	*/
80943bbd	212	err = vt8500_pwm_config(chip, pwm, state->duty_cycle, state->period);
14d89565 UKK	213	if (err)
	214	return err;
	215
	216	if (!enabled)
	217	err = vt8500_pwm_enable(chip, pwm);
	218
	219	return err;
	220	}
	221
b2ec9efc	222	static const struct pwm_ops vt8500_pwm_ops = {
14d89565	223	.apply = vt8500_pwm_apply,
a245cceb	224	};
21f47fbc	225
63e1ed23 TP	226	static const struct of_device_id vt8500_pwm_dt_ids[] = {
	227	{ .compatible = "via,vt8500-pwm", },
	228	{ /* Sentinel */ }
	229	};
	230	MODULE_DEVICE_TABLE(of, vt8500_pwm_dt_ids);
	231
	232	static int vt8500_pwm_probe(struct platform_device *pdev)
21f47fbc	233	{
635d324e	234	struct vt8500_chip *vt8500;
63e1ed23	235	struct device_node *np = pdev->dev.of_node;
a245cceb	236	int ret;
21f47fbc	237
dfbf9379 UKK	238	if (!np)
dfbf9379 UKK	239	return dev_err_probe(&pdev->dev, -EINVAL, "invalid devicetree node\n");
63e1ed23	240
635d324e	241	vt8500 = devm_kzalloc(&pdev->dev, sizeof(*vt8500), GFP_KERNEL);
635d324e	242	if (vt8500 == NULL)
21f47fbc	243	return -ENOMEM;
21f47fbc	244
635d324e	245	vt8500->chip.dev = &pdev->dev;
	246	vt8500->chip.ops = &vt8500_pwm_ops;
	247	vt8500->chip.npwm = VT8500_NR_PWMS;
21f47fbc	248
dfbf9379 UKK	249	vt8500->clk = devm_clk_get_prepared(&pdev->dev, NULL);
	250	if (IS_ERR(vt8500->clk))
	251	return dev_err_probe(&pdev->dev, PTR_ERR(vt8500->clk), "clock source not specified\n");
63e1ed23	252
635d324e	253	vt8500->base = devm_platform_ioremap_resource(pdev, 0);
	254	if (IS_ERR(vt8500->base))
	255	return PTR_ERR(vt8500->base);
21f47fbc	256
dfbf9379 UKK	257	ret = devm_pwmchip_add(&pdev->dev, &vt8500->chip);
	258	if (ret < 0)
	259	return dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
21f47fbc	260
dfbf9379	261	return 0;
21f47fbc AC	262	}
21f47fbc AC	263
63e1ed23 TP	264	static struct platform_driver vt8500_pwm_driver = {
63e1ed23 TP	265	.probe = vt8500_pwm_probe,
21f47fbc AC	266	.driver = {
21f47fbc AC	267	.name = "vt8500-pwm",
63e1ed23	268	.of_match_table = vt8500_pwm_dt_ids,
21f47fbc	269	},
21f47fbc	270	};
63e1ed23	271	module_platform_driver(vt8500_pwm_driver);
21f47fbc	272
63e1ed23 TP	273	MODULE_DESCRIPTION("VT8500 PWM Driver");
	274	MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
	275	MODULE_LICENSE("GPL v2");