[linux-block.git] / drivers / pwm / pwm-visconti.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Toshiba Visconti pulse-width-modulation controller driver
 *
 * Copyright (c) 2020 - 2021 TOSHIBA CORPORATION
 * Copyright (c) 2020 - 2021 Toshiba Electronic Devices & Storage Corporation
 *
 * Authors: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
 *
 * Limitations:
 * - The fixed input clock is running at 1 MHz and is divided by either 1,
 *   2, 4 or 8.
 * - When the settings of the PWM are modified, the new values are shadowed
 *   in hardware until the PIPGM_PCSR register is written and the currently
 *   running period is completed. This way the hardware switches atomically
 *   from the old setting to the new.
 * - Disabling the hardware completes the currently running period and keeps
 *   the output at low level at all times.
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>

#define PIPGM_PCSR(ch) (0x400 + 4 * (ch))
#define PIPGM_PDUT(ch) (0x420 + 4 * (ch))
#define PIPGM_PWMC(ch) (0x440 + 4 * (ch))

#define PIPGM_PWMC_PWMACT		BIT(5)
#define PIPGM_PWMC_CLK_MASK		GENMASK(1, 0)
#define PIPGM_PWMC_POLARITY_MASK	GENMASK(5, 5)

struct visconti_pwm_chip {
	struct pwm_chip chip;
	void __iomem *base;
};

static inline struct visconti_pwm_chip *visconti_pwm_from_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct visconti_pwm_chip, chip);
}

static int visconti_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			      const struct pwm_state *state)
{
	struct visconti_pwm_chip *priv = visconti_pwm_from_chip(chip);
	u32 period, duty_cycle, pwmc0;

	if (!state->enabled) {
		writel(0, priv->base + PIPGM_PCSR(pwm->hwpwm));
		return 0;
	}

	/*
	 * The biggest period the hardware can provide is
	 *	(0xffff << 3) * 1000 ns
	 * This value fits easily in an u32, so simplify the maths by
	 * capping the values to 32 bit integers.
	 */
	if (state->period > (0xffff << 3) * 1000)
		period = (0xffff << 3) * 1000;
	else
		period = state->period;

	if (state->duty_cycle > period)
		duty_cycle = period;
	else
		duty_cycle = state->duty_cycle;

	/*
	 * The input clock runs fixed at 1 MHz, so we have only
	 * microsecond resolution and so can divide by
	 * NSEC_PER_SEC / CLKFREQ = 1000 without losing precision.
	 */
	period /= 1000;
	duty_cycle /= 1000;

	if (!period)
		return -ERANGE;

	/*
	 * PWMC controls a divider that divides the input clk by a power of two
	 * between 1 and 8. As a smaller divider yields higher precision, pick
	 * the smallest possible one. As period is at most 0xffff << 3, pwmc0 is
	 * in the intended range [0..3].
	 */
	pwmc0 = fls(period >> 16);
	if (WARN_ON(pwmc0 > 3))
		return -EINVAL;

	period >>= pwmc0;
	duty_cycle >>= pwmc0;

	if (state->polarity == PWM_POLARITY_INVERSED)
		pwmc0 |= PIPGM_PWMC_PWMACT;
	writel(pwmc0, priv->base + PIPGM_PWMC(pwm->hwpwm));
	writel(duty_cycle, priv->base + PIPGM_PDUT(pwm->hwpwm));
	writel(period, priv->base + PIPGM_PCSR(pwm->hwpwm));

	return 0;
}

static int visconti_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
				  struct pwm_state *state)
{
	struct visconti_pwm_chip *priv = visconti_pwm_from_chip(chip);
	u32 period, duty, pwmc0, pwmc0_clk;

	period = readl(priv->base + PIPGM_PCSR(pwm->hwpwm));
	duty = readl(priv->base + PIPGM_PDUT(pwm->hwpwm));
	pwmc0 = readl(priv->base + PIPGM_PWMC(pwm->hwpwm));
	pwmc0_clk = pwmc0 & PIPGM_PWMC_CLK_MASK;

	state->period = (period << pwmc0_clk) * NSEC_PER_USEC;
	state->duty_cycle = (duty << pwmc0_clk) * NSEC_PER_USEC;
	if (pwmc0 & PIPGM_PWMC_POLARITY_MASK)
		state->polarity = PWM_POLARITY_INVERSED;
	else
		state->polarity = PWM_POLARITY_NORMAL;

	state->enabled = true;

	return 0;
}

static const struct pwm_ops visconti_pwm_ops = {
	.apply = visconti_pwm_apply,
	.get_state = visconti_pwm_get_state,
	.owner = THIS_MODULE,
};

static int visconti_pwm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct visconti_pwm_chip *priv;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(priv->base))
		return PTR_ERR(priv->base);

	priv->chip.dev = dev;
	priv->chip.ops = &visconti_pwm_ops;
	priv->chip.npwm = 4;

	ret = devm_pwmchip_add(&pdev->dev, &priv->chip);
	if (ret < 0)
		return dev_err_probe(&pdev->dev, ret, "Cannot register visconti PWM\n");

	return 0;
}

static const struct of_device_id visconti_pwm_of_match[] = {
	{ .compatible = "toshiba,visconti-pwm", },
	{ }
};
MODULE_DEVICE_TABLE(of, visconti_pwm_of_match);

static struct platform_driver visconti_pwm_driver = {
	.driver = {
		.name = "pwm-visconti",
		.of_match_table = visconti_pwm_of_match,
	},
	.probe = visconti_pwm_probe,
};
module_platform_driver(visconti_pwm_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>");
MODULE_ALIAS("platform:pwm-visconti");
Commit	Line	Data
721b5957 NI	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* Toshiba Visconti pulse-width-modulation controller driver
	4	*
	5	* Copyright (c) 2020 - 2021 TOSHIBA CORPORATION
	6	* Copyright (c) 2020 - 2021 Toshiba Electronic Devices & Storage Corporation
	7	*
	8	* Authors: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
	9	*
	10	* Limitations:
	11	* - The fixed input clock is running at 1 MHz and is divided by either 1,
	12	* 2, 4 or 8.
	13	* - When the settings of the PWM are modified, the new values are shadowed
	14	* in hardware until the PIPGM_PCSR register is written and the currently
	15	* running period is completed. This way the hardware switches atomically
	16	* from the old setting to the new.
	17	* - Disabling the hardware completes the currently running period and keeps
	18	* the output at low level at all times.
	19	*/
	20
	21	#include <linux/err.h>
	22	#include <linux/io.h>
	23	#include <linux/module.h>
	24	#include <linux/of_device.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/pwm.h>
	27
	28	#define PIPGM_PCSR(ch) (0x400 + 4 * (ch))
	29	#define PIPGM_PDUT(ch) (0x420 + 4 * (ch))
	30	#define PIPGM_PWMC(ch) (0x440 + 4 * (ch))
	31
	32	#define PIPGM_PWMC_PWMACT BIT(5)
	33	#define PIPGM_PWMC_CLK_MASK GENMASK(1, 0)
	34	#define PIPGM_PWMC_POLARITY_MASK GENMASK(5, 5)
	35
	36	struct visconti_pwm_chip {
	37	struct pwm_chip chip;
	38	void __iomem *base;
	39	};
	40
	41	static inline struct visconti_pwm_chip visconti_pwm_from_chip(struct pwm_chip chip)
	42	{
	43	return container_of(chip, struct visconti_pwm_chip, chip);
	44	}
	45
	46	static int visconti_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	47	const struct pwm_state *state)
	48	{
	49	struct visconti_pwm_chip *priv = visconti_pwm_from_chip(chip);
	50	u32 period, duty_cycle, pwmc0;
	51
	52	if (!state->enabled) {
	53	writel(0, priv->base + PIPGM_PCSR(pwm->hwpwm));
	54	return 0;
	55	}
	56
	57	/*
	58	* The biggest period the hardware can provide is
	59	* (0xffff << 3) * 1000 ns
	60	* This value fits easily in an u32, so simplify the maths by
	61	* capping the values to 32 bit integers.
	62	*/
	63	if (state->period > (0xffff << 3) * 1000)
	64	period = (0xffff << 3) * 1000;
65	else
66	period = state->period;
67
68	if (state->duty_cycle > period)
69	duty_cycle = period;
70	else
71	duty_cycle = state->duty_cycle;
72
73	/*
74	* The input clock runs fixed at 1 MHz, so we have only
75	* microsecond resolution and so can divide by
76	* NSEC_PER_SEC / CLKFREQ = 1000 without losing precision.
77	*/
78	period /= 1000;
79	duty_cycle /= 1000;
80
81	if (!period)
82	return -ERANGE;
83
84	/*
937efa29 UKK	85	* PWMC controls a divider that divides the input clk by a power of two
	86	* between 1 and 8. As a smaller divider yields higher precision, pick
	87	* the smallest possible one. As period is at most 0xffff << 3, pwmc0 is
	88	* in the intended range [0..3].
721b5957	89	*/
937efa29 UKK	90	pwmc0 = fls(period >> 16);
	91	if (WARN_ON(pwmc0 > 3))
	92	return -EINVAL;
721b5957 NI	93
	94	period >>= pwmc0;
	95	duty_cycle >>= pwmc0;
	96
	97	if (state->polarity == PWM_POLARITY_INVERSED)
	98	pwmc0 \|= PIPGM_PWMC_PWMACT;
	99	writel(pwmc0, priv->base + PIPGM_PWMC(pwm->hwpwm));
	100	writel(duty_cycle, priv->base + PIPGM_PDUT(pwm->hwpwm));
	101	writel(period, priv->base + PIPGM_PCSR(pwm->hwpwm));
	102
	103	return 0;
	104	}
	105
6c452cff UKK	106	static int visconti_pwm_get_state(struct pwm_chip chip, struct pwm_device pwm,
6c452cff UKK	107	struct pwm_state *state)
721b5957 NI	108	{
	109	struct visconti_pwm_chip *priv = visconti_pwm_from_chip(chip);
	110	u32 period, duty, pwmc0, pwmc0_clk;
	111
	112	period = readl(priv->base + PIPGM_PCSR(pwm->hwpwm));
	113	duty = readl(priv->base + PIPGM_PDUT(pwm->hwpwm));
	114	pwmc0 = readl(priv->base + PIPGM_PWMC(pwm->hwpwm));
	115	pwmc0_clk = pwmc0 & PIPGM_PWMC_CLK_MASK;
	116
	117	state->period = (period << pwmc0_clk) * NSEC_PER_USEC;
	118	state->duty_cycle = (duty << pwmc0_clk) * NSEC_PER_USEC;
	119	if (pwmc0 & PIPGM_PWMC_POLARITY_MASK)
	120	state->polarity = PWM_POLARITY_INVERSED;
	121	else
	122	state->polarity = PWM_POLARITY_NORMAL;
	123
	124	state->enabled = true;
6c452cff UKK	125
6c452cff UKK	126	return 0;
721b5957 NI	127	}
	128
	129	static const struct pwm_ops visconti_pwm_ops = {
	130	.apply = visconti_pwm_apply,
	131	.get_state = visconti_pwm_get_state,
	132	.owner = THIS_MODULE,
	133	};
	134
	135	static int visconti_pwm_probe(struct platform_device *pdev)
	136	{
	137	struct device *dev = &pdev->dev;
	138	struct visconti_pwm_chip *priv;
	139	int ret;
	140
	141	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	142	if (!priv)
	143	return -ENOMEM;
	144
	145	priv->base = devm_platform_ioremap_resource(pdev, 0);
	146	if (IS_ERR(priv->base))
	147	return PTR_ERR(priv->base);
	148
721b5957 NI	149	priv->chip.dev = dev;
	150	priv->chip.ops = &visconti_pwm_ops;
	151	priv->chip.npwm = 4;
	152
6facd840	153	ret = devm_pwmchip_add(&pdev->dev, &priv->chip);
721b5957 NI	154	if (ret < 0)
	155	return dev_err_probe(&pdev->dev, ret, "Cannot register visconti PWM\n");
	156
	157	return 0;
	158	}
	159
721b5957 NI	160	static const struct of_device_id visconti_pwm_of_match[] = {
	161	{ .compatible = "toshiba,visconti-pwm", },
	162	{ }
	163	};
	164	MODULE_DEVICE_TABLE(of, visconti_pwm_of_match);
	165
	166	static struct platform_driver visconti_pwm_driver = {
	167	.driver = {
	168	.name = "pwm-visconti",
	169	.of_match_table = visconti_pwm_of_match,
	170	},
	171	.probe = visconti_pwm_probe,
721b5957 NI	172	};
	173	module_platform_driver(visconti_pwm_driver);
	174
	175	MODULE_LICENSE("GPL v2");
	176	MODULE_AUTHOR("Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>");
	177	MODULE_ALIAS("platform:pwm-visconti");