[linux-block.git] / drivers / pwm / pwm-tiecap.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * ECAP PWM driver
 *
 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/pm_runtime.h>
#include <linux/pwm.h>
#include <linux/of_device.h>

/* ECAP registers and bits definitions */
#define CAP1			0x08
#define CAP2			0x0C
#define CAP3			0x10
#define CAP4			0x14
#define ECCTL2			0x2A
#define ECCTL2_APWM_POL_LOW	BIT(10)
#define ECCTL2_APWM_MODE	BIT(9)
#define ECCTL2_SYNC_SEL_DISA	(BIT(7) | BIT(6))
#define ECCTL2_TSCTR_FREERUN	BIT(4)

struct ecap_context {
	u32 cap3;
	u32 cap4;
	u16 ecctl2;
};

struct ecap_pwm_chip {
	struct pwm_chip chip;
	unsigned int clk_rate;
	void __iomem *mmio_base;
	struct ecap_context ctx;
};

static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct ecap_pwm_chip, chip);
}

/*
 * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
 * duty_ns   = 10^9 * duty_cycles / PWM_CLK_RATE
 */
static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
		int duty_ns, int period_ns)
{
	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
	u32 period_cycles, duty_cycles;
	unsigned long long c;
	u16 value;

	if (period_ns > NSEC_PER_SEC)
		return -ERANGE;

	c = pc->clk_rate;
	c = c * period_ns;
	do_div(c, NSEC_PER_SEC);
	period_cycles = (u32)c;

	if (period_cycles < 1) {
		period_cycles = 1;
		duty_cycles = 1;
	} else {
		c = pc->clk_rate;
		c = c * duty_ns;
		do_div(c, NSEC_PER_SEC);
		duty_cycles = (u32)c;
	}

	pm_runtime_get_sync(pc->chip.dev);

	value = readw(pc->mmio_base + ECCTL2);

	/* Configure APWM mode & disable sync option */
	value |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;

	writew(value, pc->mmio_base + ECCTL2);

	if (!pwm_is_enabled(pwm)) {
		/* Update active registers if not running */
		writel(duty_cycles, pc->mmio_base + CAP2);
		writel(period_cycles, pc->mmio_base + CAP1);
	} else {
		/*
		 * Update shadow registers to configure period and
		 * compare values. This helps current PWM period to
		 * complete on reconfiguring
		 */
		writel(duty_cycles, pc->mmio_base + CAP4);
		writel(period_cycles, pc->mmio_base + CAP3);
	}

	if (!pwm_is_enabled(pwm)) {
		value = readw(pc->mmio_base + ECCTL2);
		/* Disable APWM mode to put APWM output Low */
		value &= ~ECCTL2_APWM_MODE;
		writew(value, pc->mmio_base + ECCTL2);
	}

	pm_runtime_put_sync(pc->chip.dev);

	return 0;
}

static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
				 enum pwm_polarity polarity)
{
	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
	u16 value;

	pm_runtime_get_sync(pc->chip.dev);

	value = readw(pc->mmio_base + ECCTL2);

	if (polarity == PWM_POLARITY_INVERSED)
		/* Duty cycle defines LOW period of PWM */
		value |= ECCTL2_APWM_POL_LOW;
	else
		/* Duty cycle defines HIGH period of PWM */
		value &= ~ECCTL2_APWM_POL_LOW;

	writew(value, pc->mmio_base + ECCTL2);

	pm_runtime_put_sync(pc->chip.dev);

	return 0;
}

static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
	u16 value;

	/* Leave clock enabled on enabling PWM */
	pm_runtime_get_sync(pc->chip.dev);

	/*
	 * Enable 'Free run Time stamp counter mode' to start counter
	 * and  'APWM mode' to enable APWM output
	 */
	value = readw(pc->mmio_base + ECCTL2);
	value |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
	writew(value, pc->mmio_base + ECCTL2);

	return 0;
}

static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
	u16 value;

	/*
	 * Disable 'Free run Time stamp counter mode' to stop counter
	 * and 'APWM mode' to put APWM output to low
	 */
	value = readw(pc->mmio_base + ECCTL2);
	value &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
	writew(value, pc->mmio_base + ECCTL2);

	/* Disable clock on PWM disable */
	pm_runtime_put_sync(pc->chip.dev);
}

static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	if (pwm_is_enabled(pwm)) {
		dev_warn(chip->dev, "Removing PWM device without disabling\n");
		pm_runtime_put_sync(chip->dev);
	}
}

static const struct pwm_ops ecap_pwm_ops = {
	.free = ecap_pwm_free,
	.config = ecap_pwm_config,
	.set_polarity = ecap_pwm_set_polarity,
	.enable = ecap_pwm_enable,
	.disable = ecap_pwm_disable,
	.owner = THIS_MODULE,
};

static const struct of_device_id ecap_of_match[] = {
	{ .compatible	= "ti,am3352-ecap" },
	{ .compatible	= "ti,am33xx-ecap" },
	{},
};
MODULE_DEVICE_TABLE(of, ecap_of_match);

static int ecap_pwm_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct ecap_pwm_chip *pc;
	struct clk *clk;
	int ret;

	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	clk = devm_clk_get(&pdev->dev, "fck");
	if (IS_ERR(clk)) {
		if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
			dev_warn(&pdev->dev, "Binding is obsolete.\n");
			clk = devm_clk_get(pdev->dev.parent, "fck");
		}
	}

	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get clock\n");
		return PTR_ERR(clk);
	}

	pc->clk_rate = clk_get_rate(clk);
	if (!pc->clk_rate) {
		dev_err(&pdev->dev, "failed to get clock rate\n");
		return -EINVAL;
	}

	pc->chip.dev = &pdev->dev;
	pc->chip.ops = &ecap_pwm_ops;
	pc->chip.of_xlate = of_pwm_xlate_with_flags;
	pc->chip.of_pwm_n_cells = 3;
	pc->chip.npwm = 1;

	pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pc->mmio_base))
		return PTR_ERR(pc->mmio_base);

	ret = pwmchip_add(&pc->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, pc);
	pm_runtime_enable(&pdev->dev);

	return 0;
}

static int ecap_pwm_remove(struct platform_device *pdev)
{
	struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);

	pm_runtime_disable(&pdev->dev);

	return pwmchip_remove(&pc->chip);
}

#ifdef CONFIG_PM_SLEEP
static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
{
	pm_runtime_get_sync(pc->chip.dev);
	pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
	pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
	pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
	pm_runtime_put_sync(pc->chip.dev);
}

static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
{
	writel(pc->ctx.cap3, pc->mmio_base + CAP3);
	writel(pc->ctx.cap4, pc->mmio_base + CAP4);
	writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
}

static int ecap_pwm_suspend(struct device *dev)
{
	struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
	struct pwm_device *pwm = pc->chip.pwms;

	ecap_pwm_save_context(pc);

	/* Disable explicitly if PWM is running */
	if (pwm_is_enabled(pwm))
		pm_runtime_put_sync(dev);

	return 0;
}

static int ecap_pwm_resume(struct device *dev)
{
	struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
	struct pwm_device *pwm = pc->chip.pwms;

	/* Enable explicitly if PWM was running */
	if (pwm_is_enabled(pwm))
		pm_runtime_get_sync(dev);

	ecap_pwm_restore_context(pc);
	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);

static struct platform_driver ecap_pwm_driver = {
	.driver = {
		.name = "ecap",
		.of_match_table = ecap_of_match,
		.pm = &ecap_pwm_pm_ops,
	},
	.probe = ecap_pwm_probe,
	.remove = ecap_pwm_remove,
};
module_platform_driver(ecap_pwm_driver);

MODULE_DESCRIPTION("ECAP PWM driver");
MODULE_AUTHOR("Texas Instruments");
MODULE_LICENSE("GPL");
Commit	Line	Data
74ba9207	1	// SPDX-License-Identifier: GPL-2.0-or-later
8e0cb05b PA	2	/*
	3	* ECAP PWM driver
	4	*
216a094d	5	* Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
8e0cb05b PA	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/platform_device.h>
	10	#include <linux/io.h>
	11	#include <linux/err.h>
	12	#include <linux/clk.h>
	13	#include <linux/pm_runtime.h>
	14	#include <linux/pwm.h>
333b08ee PA	15	#include <linux/of_device.h>
333b08ee PA	16
8e0cb05b PA	17	/* ECAP registers and bits definitions */
	18	#define CAP1 0x08
	19	#define CAP2 0x0C
	20	#define CAP3 0x10
	21	#define CAP4 0x14
	22	#define ECCTL2 0x2A
454870a4	23	#define ECCTL2_APWM_POL_LOW BIT(10)
8e0cb05b PA	24	#define ECCTL2_APWM_MODE BIT(9)
	25	#define ECCTL2_SYNC_SEL_DISA (BIT(7) \| BIT(6))
	26	#define ECCTL2_TSCTR_FREERUN BIT(4)
	27
0d75c203	28	struct ecap_context {
53c7972d TR	29	u32 cap3;
	30	u32 cap4;
	31	u16 ecctl2;
0d75c203 PA	32	};
0d75c203 PA	33
8e0cb05b	34	struct ecap_pwm_chip {
53c7972d TR	35	struct pwm_chip chip;
	36	unsigned int clk_rate;
	37	void __iomem *mmio_base;
0d75c203	38	struct ecap_context ctx;
8e0cb05b PA	39	};
	40
	41	static inline struct ecap_pwm_chip to_ecap_pwm_chip(struct pwm_chip chip)
	42	{
	43	return container_of(chip, struct ecap_pwm_chip, chip);
	44	}
	45
	46	/*
	47	* period_ns = 10^9 * period_cycles / PWM_CLK_RATE
	48	* duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
	49	*/
	50	static int ecap_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	51	int duty_ns, int period_ns)
	52	{
	53	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
53c7972d	54	u32 period_cycles, duty_cycles;
8e0cb05b	55	unsigned long long c;
53c7972d	56	u16 value;
8e0cb05b	57
c2d476a9	58	if (period_ns > NSEC_PER_SEC)
8e0cb05b PA	59	return -ERANGE;
	60
	61	c = pc->clk_rate;
	62	c = c * period_ns;
	63	do_div(c, NSEC_PER_SEC);
53c7972d	64	period_cycles = (u32)c;
8e0cb05b PA	65
	66	if (period_cycles < 1) {
	67	period_cycles = 1;
	68	duty_cycles = 1;
	69	} else {
	70	c = pc->clk_rate;
	71	c = c * duty_ns;
	72	do_div(c, NSEC_PER_SEC);
53c7972d	73	duty_cycles = (u32)c;
8e0cb05b PA	74	}
	75
	76	pm_runtime_get_sync(pc->chip.dev);
	77
53c7972d	78	value = readw(pc->mmio_base + ECCTL2);
8e0cb05b PA	79
8e0cb05b PA	80	/* Configure APWM mode & disable sync option */
53c7972d	81	value \|= ECCTL2_APWM_MODE \| ECCTL2_SYNC_SEL_DISA;
8e0cb05b	82
53c7972d	83	writew(value, pc->mmio_base + ECCTL2);
8e0cb05b	84
5c31252c	85	if (!pwm_is_enabled(pwm)) {
8e0cb05b PA	86	/* Update active registers if not running */
	87	writel(duty_cycles, pc->mmio_base + CAP2);
	88	writel(period_cycles, pc->mmio_base + CAP1);
	89	} else {
	90	/*
	91	* Update shadow registers to configure period and
	92	* compare values. This helps current PWM period to
	93	* complete on reconfiguring
	94	*/
	95	writel(duty_cycles, pc->mmio_base + CAP4);
	96	writel(period_cycles, pc->mmio_base + CAP3);
	97	}
	98
5c31252c	99	if (!pwm_is_enabled(pwm)) {
53c7972d	100	value = readw(pc->mmio_base + ECCTL2);
c06fad9d	101	/* Disable APWM mode to put APWM output Low */
53c7972d TR	102	value &= ~ECCTL2_APWM_MODE;
53c7972d TR	103	writew(value, pc->mmio_base + ECCTL2);
c06fad9d PA	104	}
c06fad9d PA	105
8e0cb05b	106	pm_runtime_put_sync(pc->chip.dev);
53c7972d	107
8e0cb05b PA	108	return 0;
	109	}
	110
454870a4	111	static int ecap_pwm_set_polarity(struct pwm_chip chip, struct pwm_device pwm,
53c7972d	112	enum pwm_polarity polarity)
454870a4 PA	113	{
454870a4 PA	114	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
53c7972d	115	u16 value;
454870a4 PA	116
454870a4 PA	117	pm_runtime_get_sync(pc->chip.dev);
53c7972d TR	118
	119	value = readw(pc->mmio_base + ECCTL2);
	120
454870a4 PA	121	if (polarity == PWM_POLARITY_INVERSED)
454870a4 PA	122	/* Duty cycle defines LOW period of PWM */
53c7972d	123	value \|= ECCTL2_APWM_POL_LOW;
454870a4 PA	124	else
454870a4 PA	125	/* Duty cycle defines HIGH period of PWM */
53c7972d TR	126	value &= ~ECCTL2_APWM_POL_LOW;
	127
	128	writew(value, pc->mmio_base + ECCTL2);
454870a4	129
454870a4	130	pm_runtime_put_sync(pc->chip.dev);
53c7972d	131
454870a4 PA	132	return 0;
	133	}
	134
8e0cb05b PA	135	static int ecap_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	136	{
	137	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
53c7972d	138	u16 value;
8e0cb05b PA	139
	140	/* Leave clock enabled on enabling PWM */
	141	pm_runtime_get_sync(pc->chip.dev);
	142
	143	/*
	144	* Enable 'Free run Time stamp counter mode' to start counter
	145	* and 'APWM mode' to enable APWM output
	146	*/
53c7972d TR	147	value = readw(pc->mmio_base + ECCTL2);
	148	value \|= ECCTL2_TSCTR_FREERUN \| ECCTL2_APWM_MODE;
	149	writew(value, pc->mmio_base + ECCTL2);
	150
8e0cb05b PA	151	return 0;
	152	}
	153
	154	static void ecap_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	155	{
	156	struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
53c7972d	157	u16 value;
8e0cb05b PA	158
	159	/*
	160	* Disable 'Free run Time stamp counter mode' to stop counter
	161	* and 'APWM mode' to put APWM output to low
	162	*/
53c7972d TR	163	value = readw(pc->mmio_base + ECCTL2);
	164	value &= ~(ECCTL2_TSCTR_FREERUN \| ECCTL2_APWM_MODE);
	165	writew(value, pc->mmio_base + ECCTL2);
8e0cb05b PA	166
	167	/* Disable clock on PWM disable */
	168	pm_runtime_put_sync(pc->chip.dev);
	169	}
	170
	171	static void ecap_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	172	{
5c31252c	173	if (pwm_is_enabled(pwm)) {
8e0cb05b PA	174	dev_warn(chip->dev, "Removing PWM device without disabling\n");
	175	pm_runtime_put_sync(chip->dev);
	176	}
	177	}
	178
	179	static const struct pwm_ops ecap_pwm_ops = {
53c7972d TR	180	.free = ecap_pwm_free,
	181	.config = ecap_pwm_config,
	182	.set_polarity = ecap_pwm_set_polarity,
	183	.enable = ecap_pwm_enable,
	184	.disable = ecap_pwm_disable,
	185	.owner = THIS_MODULE,
8e0cb05b PA	186	};
8e0cb05b PA	187
333b08ee	188	static const struct of_device_id ecap_of_match[] = {
ae5200d2	189	{ .compatible = "ti,am3352-ecap" },
333b08ee PA	190	{ .compatible = "ti,am33xx-ecap" },
	191	{},
	192	};
	193	MODULE_DEVICE_TABLE(of, ecap_of_match);
	194
3e9fe83d	195	static int ecap_pwm_probe(struct platform_device *pdev)
8e0cb05b	196	{
ae5200d2	197	struct device_node *np = pdev->dev.of_node;
53c7972d	198	struct ecap_pwm_chip *pc;
8e0cb05b	199	struct clk *clk;
53c7972d	200	int ret;
8e0cb05b PA	201
8e0cb05b PA	202	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
c10d5063	203	if (!pc)
8e0cb05b	204	return -ENOMEM;
8e0cb05b PA	205
8e0cb05b PA	206	clk = devm_clk_get(&pdev->dev, "fck");
ae5200d2 CJF	207	if (IS_ERR(clk)) {
	208	if (of_device_is_compatible(np, "ti,am33xx-ecap")) {
	209	dev_warn(&pdev->dev, "Binding is obsolete.\n");
	210	clk = devm_clk_get(pdev->dev.parent, "fck");
	211	}
	212	}
	213
8e0cb05b PA	214	if (IS_ERR(clk)) {
	215	dev_err(&pdev->dev, "failed to get clock\n");
	216	return PTR_ERR(clk);
	217	}
	218
	219	pc->clk_rate = clk_get_rate(clk);
	220	if (!pc->clk_rate) {
	221	dev_err(&pdev->dev, "failed to get clock rate\n");
	222	return -EINVAL;
	223	}
	224
	225	pc->chip.dev = &pdev->dev;
	226	pc->chip.ops = &ecap_pwm_ops;
333b08ee PA	227	pc->chip.of_xlate = of_pwm_xlate_with_flags;
333b08ee PA	228	pc->chip.of_pwm_n_cells = 3;
8e0cb05b PA	229	pc->chip.npwm = 1;
8e0cb05b PA	230
1dcf0523	231	pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);
6d4294d1 TR	232	if (IS_ERR(pc->mmio_base))
6d4294d1 TR	233	return PTR_ERR(pc->mmio_base);
8e0cb05b PA	234
	235	ret = pwmchip_add(&pc->chip);
	236	if (ret < 0) {
	237	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
	238	return ret;
	239	}
	240
23f373e6	241	platform_set_drvdata(pdev, pc);
8e0cb05b	242	pm_runtime_enable(&pdev->dev);
333b08ee	243
8e0cb05b PA	244	return 0;
	245	}
	246
77f37917	247	static int ecap_pwm_remove(struct platform_device *pdev)
8e0cb05b PA	248	{
	249	struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
	250
8e0cb05b	251	pm_runtime_disable(&pdev->dev);
53c7972d	252
8e0cb05b PA	253	return pwmchip_remove(&pc->chip);
	254	}
	255
3943a650	256	#ifdef CONFIG_PM_SLEEP
a38c9898	257	static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
0d75c203 PA	258	{
	259	pm_runtime_get_sync(pc->chip.dev);
	260	pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
	261	pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
	262	pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
	263	pm_runtime_put_sync(pc->chip.dev);
	264	}
	265
a38c9898	266	static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
0d75c203 PA	267	{
	268	writel(pc->ctx.cap3, pc->mmio_base + CAP3);
	269	writel(pc->ctx.cap4, pc->mmio_base + CAP4);
	270	writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
	271	}
	272
	273	static int ecap_pwm_suspend(struct device *dev)
	274	{
	275	struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
	276	struct pwm_device *pwm = pc->chip.pwms;
	277
	278	ecap_pwm_save_context(pc);
	279
	280	/* Disable explicitly if PWM is running */
5c31252c	281	if (pwm_is_enabled(pwm))
0d75c203 PA	282	pm_runtime_put_sync(dev);
	283
	284	return 0;
	285	}
	286
	287	static int ecap_pwm_resume(struct device *dev)
	288	{
	289	struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
	290	struct pwm_device *pwm = pc->chip.pwms;
	291
	292	/* Enable explicitly if PWM was running */
5c31252c	293	if (pwm_is_enabled(pwm))
0d75c203 PA	294	pm_runtime_get_sync(dev);
	295
	296	ecap_pwm_restore_context(pc);
	297	return 0;
	298	}
b78f5fc9	299	#endif
0d75c203 PA	300
	301	static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
	302
8e0cb05b PA	303	static struct platform_driver ecap_pwm_driver = {
8e0cb05b PA	304	.driver = {
53c7972d	305	.name = "ecap",
333b08ee	306	.of_match_table = ecap_of_match,
53c7972d	307	.pm = &ecap_pwm_pm_ops,
8e0cb05b PA	308	},
8e0cb05b PA	309	.probe = ecap_pwm_probe,
fd109112	310	.remove = ecap_pwm_remove,
8e0cb05b	311	};
8e0cb05b PA	312	module_platform_driver(ecap_pwm_driver);
	313
	314	MODULE_DESCRIPTION("ECAP PWM driver");
	315	MODULE_AUTHOR("Texas Instruments");
	316	MODULE_LICENSE("GPL");