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8e0cb05b PA |
1 | /* |
2 | * ECAP PWM driver | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/ | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/err.h> | |
25 | #include <linux/clk.h> | |
26 | #include <linux/pm_runtime.h> | |
27 | #include <linux/pwm.h> | |
333b08ee PA |
28 | #include <linux/of_device.h> |
29 | ||
8e0cb05b PA |
30 | /* ECAP registers and bits definitions */ |
31 | #define CAP1 0x08 | |
32 | #define CAP2 0x0C | |
33 | #define CAP3 0x10 | |
34 | #define CAP4 0x14 | |
35 | #define ECCTL2 0x2A | |
454870a4 | 36 | #define ECCTL2_APWM_POL_LOW BIT(10) |
8e0cb05b PA |
37 | #define ECCTL2_APWM_MODE BIT(9) |
38 | #define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6)) | |
39 | #define ECCTL2_TSCTR_FREERUN BIT(4) | |
40 | ||
0d75c203 | 41 | struct ecap_context { |
53c7972d TR |
42 | u32 cap3; |
43 | u32 cap4; | |
44 | u16 ecctl2; | |
0d75c203 PA |
45 | }; |
46 | ||
8e0cb05b | 47 | struct ecap_pwm_chip { |
53c7972d TR |
48 | struct pwm_chip chip; |
49 | unsigned int clk_rate; | |
50 | void __iomem *mmio_base; | |
0d75c203 | 51 | struct ecap_context ctx; |
8e0cb05b PA |
52 | }; |
53 | ||
54 | static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip) | |
55 | { | |
56 | return container_of(chip, struct ecap_pwm_chip, chip); | |
57 | } | |
58 | ||
59 | /* | |
60 | * period_ns = 10^9 * period_cycles / PWM_CLK_RATE | |
61 | * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE | |
62 | */ | |
63 | static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |
64 | int duty_ns, int period_ns) | |
65 | { | |
66 | struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); | |
53c7972d | 67 | u32 period_cycles, duty_cycles; |
8e0cb05b | 68 | unsigned long long c; |
53c7972d | 69 | u16 value; |
8e0cb05b | 70 | |
c2d476a9 | 71 | if (period_ns > NSEC_PER_SEC) |
8e0cb05b PA |
72 | return -ERANGE; |
73 | ||
74 | c = pc->clk_rate; | |
75 | c = c * period_ns; | |
76 | do_div(c, NSEC_PER_SEC); | |
53c7972d | 77 | period_cycles = (u32)c; |
8e0cb05b PA |
78 | |
79 | if (period_cycles < 1) { | |
80 | period_cycles = 1; | |
81 | duty_cycles = 1; | |
82 | } else { | |
83 | c = pc->clk_rate; | |
84 | c = c * duty_ns; | |
85 | do_div(c, NSEC_PER_SEC); | |
53c7972d | 86 | duty_cycles = (u32)c; |
8e0cb05b PA |
87 | } |
88 | ||
89 | pm_runtime_get_sync(pc->chip.dev); | |
90 | ||
53c7972d | 91 | value = readw(pc->mmio_base + ECCTL2); |
8e0cb05b PA |
92 | |
93 | /* Configure APWM mode & disable sync option */ | |
53c7972d | 94 | value |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA; |
8e0cb05b | 95 | |
53c7972d | 96 | writew(value, pc->mmio_base + ECCTL2); |
8e0cb05b | 97 | |
5c31252c | 98 | if (!pwm_is_enabled(pwm)) { |
8e0cb05b PA |
99 | /* Update active registers if not running */ |
100 | writel(duty_cycles, pc->mmio_base + CAP2); | |
101 | writel(period_cycles, pc->mmio_base + CAP1); | |
102 | } else { | |
103 | /* | |
104 | * Update shadow registers to configure period and | |
105 | * compare values. This helps current PWM period to | |
106 | * complete on reconfiguring | |
107 | */ | |
108 | writel(duty_cycles, pc->mmio_base + CAP4); | |
109 | writel(period_cycles, pc->mmio_base + CAP3); | |
110 | } | |
111 | ||
5c31252c | 112 | if (!pwm_is_enabled(pwm)) { |
53c7972d | 113 | value = readw(pc->mmio_base + ECCTL2); |
c06fad9d | 114 | /* Disable APWM mode to put APWM output Low */ |
53c7972d TR |
115 | value &= ~ECCTL2_APWM_MODE; |
116 | writew(value, pc->mmio_base + ECCTL2); | |
c06fad9d PA |
117 | } |
118 | ||
8e0cb05b | 119 | pm_runtime_put_sync(pc->chip.dev); |
53c7972d | 120 | |
8e0cb05b PA |
121 | return 0; |
122 | } | |
123 | ||
454870a4 | 124 | static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, |
53c7972d | 125 | enum pwm_polarity polarity) |
454870a4 PA |
126 | { |
127 | struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); | |
53c7972d | 128 | u16 value; |
454870a4 PA |
129 | |
130 | pm_runtime_get_sync(pc->chip.dev); | |
53c7972d TR |
131 | |
132 | value = readw(pc->mmio_base + ECCTL2); | |
133 | ||
454870a4 PA |
134 | if (polarity == PWM_POLARITY_INVERSED) |
135 | /* Duty cycle defines LOW period of PWM */ | |
53c7972d | 136 | value |= ECCTL2_APWM_POL_LOW; |
454870a4 PA |
137 | else |
138 | /* Duty cycle defines HIGH period of PWM */ | |
53c7972d TR |
139 | value &= ~ECCTL2_APWM_POL_LOW; |
140 | ||
141 | writew(value, pc->mmio_base + ECCTL2); | |
454870a4 | 142 | |
454870a4 | 143 | pm_runtime_put_sync(pc->chip.dev); |
53c7972d | 144 | |
454870a4 PA |
145 | return 0; |
146 | } | |
147 | ||
8e0cb05b PA |
148 | static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
149 | { | |
150 | struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); | |
53c7972d | 151 | u16 value; |
8e0cb05b PA |
152 | |
153 | /* Leave clock enabled on enabling PWM */ | |
154 | pm_runtime_get_sync(pc->chip.dev); | |
155 | ||
156 | /* | |
157 | * Enable 'Free run Time stamp counter mode' to start counter | |
158 | * and 'APWM mode' to enable APWM output | |
159 | */ | |
53c7972d TR |
160 | value = readw(pc->mmio_base + ECCTL2); |
161 | value |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE; | |
162 | writew(value, pc->mmio_base + ECCTL2); | |
163 | ||
8e0cb05b PA |
164 | return 0; |
165 | } | |
166 | ||
167 | static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
168 | { | |
169 | struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip); | |
53c7972d | 170 | u16 value; |
8e0cb05b PA |
171 | |
172 | /* | |
173 | * Disable 'Free run Time stamp counter mode' to stop counter | |
174 | * and 'APWM mode' to put APWM output to low | |
175 | */ | |
53c7972d TR |
176 | value = readw(pc->mmio_base + ECCTL2); |
177 | value &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE); | |
178 | writew(value, pc->mmio_base + ECCTL2); | |
8e0cb05b PA |
179 | |
180 | /* Disable clock on PWM disable */ | |
181 | pm_runtime_put_sync(pc->chip.dev); | |
182 | } | |
183 | ||
184 | static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) | |
185 | { | |
5c31252c | 186 | if (pwm_is_enabled(pwm)) { |
8e0cb05b PA |
187 | dev_warn(chip->dev, "Removing PWM device without disabling\n"); |
188 | pm_runtime_put_sync(chip->dev); | |
189 | } | |
190 | } | |
191 | ||
192 | static const struct pwm_ops ecap_pwm_ops = { | |
53c7972d TR |
193 | .free = ecap_pwm_free, |
194 | .config = ecap_pwm_config, | |
195 | .set_polarity = ecap_pwm_set_polarity, | |
196 | .enable = ecap_pwm_enable, | |
197 | .disable = ecap_pwm_disable, | |
198 | .owner = THIS_MODULE, | |
8e0cb05b PA |
199 | }; |
200 | ||
333b08ee | 201 | static const struct of_device_id ecap_of_match[] = { |
ae5200d2 | 202 | { .compatible = "ti,am3352-ecap" }, |
333b08ee PA |
203 | { .compatible = "ti,am33xx-ecap" }, |
204 | {}, | |
205 | }; | |
206 | MODULE_DEVICE_TABLE(of, ecap_of_match); | |
207 | ||
3e9fe83d | 208 | static int ecap_pwm_probe(struct platform_device *pdev) |
8e0cb05b | 209 | { |
ae5200d2 | 210 | struct device_node *np = pdev->dev.of_node; |
53c7972d | 211 | struct ecap_pwm_chip *pc; |
8e0cb05b PA |
212 | struct resource *r; |
213 | struct clk *clk; | |
53c7972d | 214 | int ret; |
8e0cb05b PA |
215 | |
216 | pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); | |
c10d5063 | 217 | if (!pc) |
8e0cb05b | 218 | return -ENOMEM; |
8e0cb05b PA |
219 | |
220 | clk = devm_clk_get(&pdev->dev, "fck"); | |
ae5200d2 CJF |
221 | if (IS_ERR(clk)) { |
222 | if (of_device_is_compatible(np, "ti,am33xx-ecap")) { | |
223 | dev_warn(&pdev->dev, "Binding is obsolete.\n"); | |
224 | clk = devm_clk_get(pdev->dev.parent, "fck"); | |
225 | } | |
226 | } | |
227 | ||
8e0cb05b PA |
228 | if (IS_ERR(clk)) { |
229 | dev_err(&pdev->dev, "failed to get clock\n"); | |
230 | return PTR_ERR(clk); | |
231 | } | |
232 | ||
233 | pc->clk_rate = clk_get_rate(clk); | |
234 | if (!pc->clk_rate) { | |
235 | dev_err(&pdev->dev, "failed to get clock rate\n"); | |
236 | return -EINVAL; | |
237 | } | |
238 | ||
239 | pc->chip.dev = &pdev->dev; | |
240 | pc->chip.ops = &ecap_pwm_ops; | |
333b08ee PA |
241 | pc->chip.of_xlate = of_pwm_xlate_with_flags; |
242 | pc->chip.of_pwm_n_cells = 3; | |
8e0cb05b PA |
243 | pc->chip.base = -1; |
244 | pc->chip.npwm = 1; | |
245 | ||
246 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
6d4294d1 TR |
247 | pc->mmio_base = devm_ioremap_resource(&pdev->dev, r); |
248 | if (IS_ERR(pc->mmio_base)) | |
249 | return PTR_ERR(pc->mmio_base); | |
8e0cb05b PA |
250 | |
251 | ret = pwmchip_add(&pc->chip); | |
252 | if (ret < 0) { | |
253 | dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); | |
254 | return ret; | |
255 | } | |
256 | ||
23f373e6 | 257 | platform_set_drvdata(pdev, pc); |
8e0cb05b | 258 | pm_runtime_enable(&pdev->dev); |
333b08ee | 259 | |
8e0cb05b PA |
260 | return 0; |
261 | } | |
262 | ||
77f37917 | 263 | static int ecap_pwm_remove(struct platform_device *pdev) |
8e0cb05b PA |
264 | { |
265 | struct ecap_pwm_chip *pc = platform_get_drvdata(pdev); | |
266 | ||
8e0cb05b | 267 | pm_runtime_disable(&pdev->dev); |
53c7972d | 268 | |
8e0cb05b PA |
269 | return pwmchip_remove(&pc->chip); |
270 | } | |
271 | ||
3943a650 | 272 | #ifdef CONFIG_PM_SLEEP |
a38c9898 | 273 | static void ecap_pwm_save_context(struct ecap_pwm_chip *pc) |
0d75c203 PA |
274 | { |
275 | pm_runtime_get_sync(pc->chip.dev); | |
276 | pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2); | |
277 | pc->ctx.cap4 = readl(pc->mmio_base + CAP4); | |
278 | pc->ctx.cap3 = readl(pc->mmio_base + CAP3); | |
279 | pm_runtime_put_sync(pc->chip.dev); | |
280 | } | |
281 | ||
a38c9898 | 282 | static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc) |
0d75c203 PA |
283 | { |
284 | writel(pc->ctx.cap3, pc->mmio_base + CAP3); | |
285 | writel(pc->ctx.cap4, pc->mmio_base + CAP4); | |
286 | writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2); | |
287 | } | |
288 | ||
289 | static int ecap_pwm_suspend(struct device *dev) | |
290 | { | |
291 | struct ecap_pwm_chip *pc = dev_get_drvdata(dev); | |
292 | struct pwm_device *pwm = pc->chip.pwms; | |
293 | ||
294 | ecap_pwm_save_context(pc); | |
295 | ||
296 | /* Disable explicitly if PWM is running */ | |
5c31252c | 297 | if (pwm_is_enabled(pwm)) |
0d75c203 PA |
298 | pm_runtime_put_sync(dev); |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | static int ecap_pwm_resume(struct device *dev) | |
304 | { | |
305 | struct ecap_pwm_chip *pc = dev_get_drvdata(dev); | |
306 | struct pwm_device *pwm = pc->chip.pwms; | |
307 | ||
308 | /* Enable explicitly if PWM was running */ | |
5c31252c | 309 | if (pwm_is_enabled(pwm)) |
0d75c203 PA |
310 | pm_runtime_get_sync(dev); |
311 | ||
312 | ecap_pwm_restore_context(pc); | |
313 | return 0; | |
314 | } | |
b78f5fc9 | 315 | #endif |
0d75c203 PA |
316 | |
317 | static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume); | |
318 | ||
8e0cb05b PA |
319 | static struct platform_driver ecap_pwm_driver = { |
320 | .driver = { | |
53c7972d | 321 | .name = "ecap", |
333b08ee | 322 | .of_match_table = ecap_of_match, |
53c7972d | 323 | .pm = &ecap_pwm_pm_ops, |
8e0cb05b PA |
324 | }, |
325 | .probe = ecap_pwm_probe, | |
fd109112 | 326 | .remove = ecap_pwm_remove, |
8e0cb05b | 327 | }; |
8e0cb05b PA |
328 | module_platform_driver(ecap_pwm_driver); |
329 | ||
330 | MODULE_DESCRIPTION("ECAP PWM driver"); | |
331 | MODULE_AUTHOR("Texas Instruments"); | |
332 | MODULE_LICENSE("GPL"); |