[linux-block.git] / drivers / pwm / pwm-tegra.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * drivers/pwm/pwm-tegra.c
 *
 * Tegra pulse-width-modulation controller driver
 *
 * Copyright (c) 2010-2020, NVIDIA Corporation.
 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
 *
 * Overview of Tegra Pulse Width Modulator Register:
 * 1. 13-bit: Frequency division (SCALE)
 * 2. 8-bit : Pulse division (DUTY)
 * 3. 1-bit : Enable bit
 *
 * The PWM clock frequency is divided by 256 before subdividing it based
 * on the programmable frequency division value to generate the required
 * frequency for PWM output. The maximum output frequency that can be
 * achieved is (max rate of source clock) / 256.
 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
 * 408 MHz/256 = 1.6 MHz.
 * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
 *
 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
 * To achieve 100% duty cycle, program Bit [24] of this register to
 * 1’b1. In which case the other bits [23:16] are set to don't care.
 *
 * Limitations:
 * -	When PWM is disabled, the output is driven to inactive.
 * -	It does not allow the current PWM period to complete and
 *	stops abruptly.
 *
 * -	If the register is reconfigured while PWM is running,
 *	it does not complete the currently running period.
 *
 * -	If the user input duty is beyond acceptible limits,
 *	-EINVAL is returned.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pwm.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/slab.h>
#include <linux/reset.h>

#define PWM_ENABLE	(1 << 31)
#define PWM_DUTY_WIDTH	8
#define PWM_DUTY_SHIFT	16
#define PWM_SCALE_WIDTH	13
#define PWM_SCALE_SHIFT	0

struct tegra_pwm_soc {
	unsigned int num_channels;

	/* Maximum IP frequency for given SoCs */
	unsigned long max_frequency;
};

struct tegra_pwm_chip {
	struct pwm_chip chip;
	struct device *dev;

	struct clk *clk;
	struct reset_control*rst;

	unsigned long clk_rate;
	unsigned long min_period_ns;

	void __iomem *regs;

	const struct tegra_pwm_soc *soc;
};

static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct tegra_pwm_chip, chip);
}

static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
{
	return readl(chip->regs + (num << 4));
}

static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
			     unsigned long val)
{
	writel(val, chip->regs + (num << 4));
}

static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			    int duty_ns, int period_ns)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	unsigned long long c = duty_ns, hz;
	unsigned long rate, required_clk_rate;
	u32 val = 0;
	int err;

	/*
	 * Convert from duty_ns / period_ns to a fixed number of duty ticks
	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
	 * nearest integer during division.
	 */
	c *= (1 << PWM_DUTY_WIDTH);
	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);

	val = (u32)c << PWM_DUTY_SHIFT;

	/*
	 *  min period = max clock limit >> PWM_DUTY_WIDTH
	 */
	if (period_ns < pc->min_period_ns)
		return -EINVAL;

	/*
	 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
	 * cycles at the PWM clock rate will take period_ns nanoseconds.
	 *
	 * num_channels: If single instance of PWM controller has multiple
	 * channels (e.g. Tegra210 or older) then it is not possible to
	 * configure separate clock rates to each of the channels, in such
	 * case the value stored during probe will be referred.
	 *
	 * If every PWM controller instance has one channel respectively, i.e.
	 * nums_channels == 1 then only the clock rate can be modified
	 * dynamically (e.g. Tegra186 or Tegra194).
	 */
	if (pc->soc->num_channels == 1) {
		/*
		 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
		 * with the maximum possible rate that the controller can
		 * provide. Any further lower value can be derived by setting
		 * PFM bits[0:12].
		 *
		 * required_clk_rate is a reference rate for source clock and
		 * it is derived based on user requested period. By setting the
		 * source clock rate as required_clk_rate, PWM controller will
		 * be able to configure the requested period.
		 */
		required_clk_rate =
			(NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;

		err = clk_set_rate(pc->clk, required_clk_rate);
		if (err < 0)
			return -EINVAL;

		/* Store the new rate for further references */
		pc->clk_rate = clk_get_rate(pc->clk);
	}

	rate = pc->clk_rate >> PWM_DUTY_WIDTH;

	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
	hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns);
	rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);

	/*
	 * Since the actual PWM divider is the register's frequency divider
	 * field plus 1, we need to decrement to get the correct value to
	 * write to the register.
	 */
	if (rate > 0)
		rate--;

	/*
	 * Make sure that the rate will fit in the register's frequency
	 * divider field.
	 */
	if (rate >> PWM_SCALE_WIDTH)
		return -EINVAL;

	val |= rate << PWM_SCALE_SHIFT;

	/*
	 * If the PWM channel is disabled, make sure to turn on the clock
	 * before writing the register. Otherwise, keep it enabled.
	 */
	if (!pwm_is_enabled(pwm)) {
		err = clk_prepare_enable(pc->clk);
		if (err < 0)
			return err;
	} else
		val |= PWM_ENABLE;

	pwm_writel(pc, pwm->hwpwm, val);

	/*
	 * If the PWM is not enabled, turn the clock off again to save power.
	 */
	if (!pwm_is_enabled(pwm))
		clk_disable_unprepare(pc->clk);

	return 0;
}

static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	int rc = 0;
	u32 val;

	rc = clk_prepare_enable(pc->clk);
	if (rc < 0)
		return rc;

	val = pwm_readl(pc, pwm->hwpwm);
	val |= PWM_ENABLE;
	pwm_writel(pc, pwm->hwpwm, val);

	return 0;
}

static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	u32 val;

	val = pwm_readl(pc, pwm->hwpwm);
	val &= ~PWM_ENABLE;
	pwm_writel(pc, pwm->hwpwm, val);

	clk_disable_unprepare(pc->clk);
}

static const struct pwm_ops tegra_pwm_ops = {
	.config = tegra_pwm_config,
	.enable = tegra_pwm_enable,
	.disable = tegra_pwm_disable,
	.owner = THIS_MODULE,
};

static int tegra_pwm_probe(struct platform_device *pdev)
{
	struct tegra_pwm_chip *pwm;
	int ret;

	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
	if (!pwm)
		return -ENOMEM;

	pwm->soc = of_device_get_match_data(&pdev->dev);
	pwm->dev = &pdev->dev;

	pwm->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pwm->regs))
		return PTR_ERR(pwm->regs);

	platform_set_drvdata(pdev, pwm);

	pwm->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pwm->clk))
		return PTR_ERR(pwm->clk);

	/* Set maximum frequency of the IP */
	ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
	if (ret < 0) {
		dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
		return ret;
	}

	/*
	 * The requested and configured frequency may differ due to
	 * clock register resolutions. Get the configured frequency
	 * so that PWM period can be calculated more accurately.
	 */
	pwm->clk_rate = clk_get_rate(pwm->clk);

	/* Set minimum limit of PWM period for the IP */
	pwm->min_period_ns =
	    (NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;

	pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
	if (IS_ERR(pwm->rst)) {
		ret = PTR_ERR(pwm->rst);
		dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
		return ret;
	}

	reset_control_deassert(pwm->rst);

	pwm->chip.dev = &pdev->dev;
	pwm->chip.ops = &tegra_pwm_ops;
	pwm->chip.npwm = pwm->soc->num_channels;

	ret = pwmchip_add(&pwm->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		reset_control_assert(pwm->rst);
		return ret;
	}

	return 0;
}

static int tegra_pwm_remove(struct platform_device *pdev)
{
	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);

	pwmchip_remove(&pc->chip);

	reset_control_assert(pc->rst);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int tegra_pwm_suspend(struct device *dev)
{
	return pinctrl_pm_select_sleep_state(dev);
}

static int tegra_pwm_resume(struct device *dev)
{
	return pinctrl_pm_select_default_state(dev);
}
#endif

static const struct tegra_pwm_soc tegra20_pwm_soc = {
	.num_channels = 4,
	.max_frequency = 48000000UL,
};

static const struct tegra_pwm_soc tegra186_pwm_soc = {
	.num_channels = 1,
	.max_frequency = 102000000UL,
};

static const struct tegra_pwm_soc tegra194_pwm_soc = {
	.num_channels = 1,
	.max_frequency = 408000000UL,
};

static const struct of_device_id tegra_pwm_of_match[] = {
	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
	{ }
};
MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);

static const struct dev_pm_ops tegra_pwm_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
};

static struct platform_driver tegra_pwm_driver = {
	.driver = {
		.name = "tegra-pwm",
		.of_match_table = tegra_pwm_of_match,
		.pm = &tegra_pwm_pm_ops,
	},
	.probe = tegra_pwm_probe,
	.remove = tegra_pwm_remove,
};

module_platform_driver(tegra_pwm_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
MODULE_DESCRIPTION("Tegra PWM controller driver");
MODULE_ALIAS("platform:tegra-pwm");
Commit	Line	Data
16216333	1	// SPDX-License-Identifier: GPL-2.0-or-later
0134b932 TR	2	/*
	3	* drivers/pwm/pwm-tegra.c
	4	*
	5	* Tegra pulse-width-modulation controller driver
	6	*
1d7796bd	7	* Copyright (c) 2010-2020, NVIDIA Corporation.
0134b932	8	* Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
1d7796bd SP	9	*
	10	* Overview of Tegra Pulse Width Modulator Register:
	11	* 1. 13-bit: Frequency division (SCALE)
	12	* 2. 8-bit : Pulse division (DUTY)
	13	* 3. 1-bit : Enable bit
	14	*
	15	* The PWM clock frequency is divided by 256 before subdividing it based
	16	* on the programmable frequency division value to generate the required
	17	* frequency for PWM output. The maximum output frequency that can be
	18	* achieved is (max rate of source clock) / 256.
	19	* e.g. if source clock rate is 408 MHz, maximum output frequency can be:
	20	* 408 MHz/256 = 1.6 MHz.
	21	* This 1.6 MHz frequency can further be divided using SCALE value in PWM.
	22	*
	23	* PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
	24	* To achieve 100% duty cycle, program Bit [24] of this register to
	25	* 1’b1. In which case the other bits [23:16] are set to don't care.
	26	*
	27	* Limitations:
	28	* - When PWM is disabled, the output is driven to inactive.
	29	* - It does not allow the current PWM period to complete and
	30	* stops abruptly.
	31	*
	32	* - If the register is reconfigured while PWM is running,
	33	* it does not complete the currently running period.
	34	*
	35	* - If the user input duty is beyond acceptible limits,
	36	* -EINVAL is returned.
0134b932 TR	37	*/
	38
	39	#include <linux/clk.h>
	40	#include <linux/err.h>
	41	#include <linux/io.h>
	42	#include <linux/module.h>
	43	#include <linux/of.h>
e9be88a2	44	#include <linux/of_device.h>
0134b932 TR	45	#include <linux/pwm.h>
0134b932 TR	46	#include <linux/platform_device.h>
4a813b26	47	#include <linux/pinctrl/consumer.h>
0134b932	48	#include <linux/slab.h>
5dfbd2bd	49	#include <linux/reset.h>
0134b932 TR	50
	51	#define PWM_ENABLE (1 << 31)
	52	#define PWM_DUTY_WIDTH 8
	53	#define PWM_DUTY_SHIFT 16
	54	#define PWM_SCALE_WIDTH 13
	55	#define PWM_SCALE_SHIFT 0
	56
e9be88a2 LD	57	struct tegra_pwm_soc {
e9be88a2 LD	58	unsigned int num_channels;
0527eb37 LD	59
	60	/* Maximum IP frequency for given SoCs */
	61	unsigned long max_frequency;
e9be88a2 LD	62	};
e9be88a2 LD	63
0134b932	64	struct tegra_pwm_chip {
e17c0b22 TR	65	struct pwm_chip chip;
e17c0b22 TR	66	struct device *dev;
0134b932	67
e17c0b22	68	struct clk *clk;
5dfbd2bd	69	struct reset_control*rst;
0134b932	70
46fa8bc0	71	unsigned long clk_rate;
1d7796bd	72	unsigned long min_period_ns;
46fa8bc0	73
4f57f5a0	74	void __iomem *regs;
e9be88a2 LD	75
e9be88a2 LD	76	const struct tegra_pwm_soc *soc;
0134b932 TR	77	};
	78
	79	static inline struct tegra_pwm_chip to_tegra_pwm_chip(struct pwm_chip chip)
	80	{
	81	return container_of(chip, struct tegra_pwm_chip, chip);
	82	}
	83
	84	static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
	85	{
4f57f5a0	86	return readl(chip->regs + (num << 4));
0134b932 TR	87	}
	88
	89	static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
	90	unsigned long val)
	91	{
4f57f5a0	92	writel(val, chip->regs + (num << 4));
0134b932 TR	93	}
	94
	95	static int tegra_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	96	int duty_ns, int period_ns)
	97	{
	98	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
6db78b20	99	unsigned long long c = duty_ns, hz;
1d7796bd	100	unsigned long rate, required_clk_rate;
0134b932 TR	101	u32 val = 0;
	102	int err;
	103
	104	/*
	105	* Convert from duty_ns / period_ns to a fixed number of duty ticks
	106	* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
	107	* nearest integer during division.
	108	*/
b979ed53	109	c *= (1 << PWM_DUTY_WIDTH);
90241fb9	110	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
0134b932 TR	111
	112	val = (u32)c << PWM_DUTY_SHIFT;
	113
1d7796bd SP	114	/*
	115	* min period = max clock limit >> PWM_DUTY_WIDTH
	116	*/
	117	if (period_ns < pc->min_period_ns)
	118	return -EINVAL;
	119
0134b932 TR	120	/*
	121	* Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
	122	* cycles at the PWM clock rate will take period_ns nanoseconds.
1d7796bd SP	123	*
	124	* num_channels: If single instance of PWM controller has multiple
	125	* channels (e.g. Tegra210 or older) then it is not possible to
	126	* configure separate clock rates to each of the channels, in such
	127	* case the value stored during probe will be referred.
	128	*
	129	* If every PWM controller instance has one channel respectively, i.e.
	130	* nums_channels == 1 then only the clock rate can be modified
	131	* dynamically (e.g. Tegra186 or Tegra194).
0134b932	132	*/
1d7796bd SP	133	if (pc->soc->num_channels == 1) {
	134	/*
	135	* Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
	136	* with the maximum possible rate that the controller can
	137	* provide. Any further lower value can be derived by setting
	138	* PFM bits[0:12].
	139	*
	140	* required_clk_rate is a reference rate for source clock and
	141	* it is derived based on user requested period. By setting the
	142	* source clock rate as required_clk_rate, PWM controller will
	143	* be able to configure the requested period.
	144	*/
	145	required_clk_rate =
	146	(NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
	147
	148	err = clk_set_rate(pc->clk, required_clk_rate);
	149	if (err < 0)
	150	return -EINVAL;
	151
	152	/* Store the new rate for further references */
	153	pc->clk_rate = clk_get_rate(pc->clk);
	154	}
	155
46fa8bc0	156	rate = pc->clk_rate >> PWM_DUTY_WIDTH;
0134b932	157
250b76f4	158	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
6db78b20 TR	159	hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns);
6db78b20 TR	160	rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);
0134b932 TR	161
	162	/*
	163	* Since the actual PWM divider is the register's frequency divider
1d7796bd	164	* field plus 1, we need to decrement to get the correct value to
0134b932 TR	165	* write to the register.
	166	*/
	167	if (rate > 0)
	168	rate--;
	169
	170	/*
	171	* Make sure that the rate will fit in the register's frequency
	172	* divider field.
	173	*/
	174	if (rate >> PWM_SCALE_WIDTH)
	175	return -EINVAL;
	176
	177	val \|= rate << PWM_SCALE_SHIFT;
	178
	179	/*
	180	* If the PWM channel is disabled, make sure to turn on the clock
	181	* before writing the register. Otherwise, keep it enabled.
	182	*/
5c31252c	183	if (!pwm_is_enabled(pwm)) {
0134b932 TR	184	err = clk_prepare_enable(pc->clk);
	185	if (err < 0)
	186	return err;
	187	} else
	188	val \|= PWM_ENABLE;
	189
	190	pwm_writel(pc, pwm->hwpwm, val);
	191
	192	/*
	193	* If the PWM is not enabled, turn the clock off again to save power.
	194	*/
5c31252c	195	if (!pwm_is_enabled(pwm))
0134b932 TR	196	clk_disable_unprepare(pc->clk);
	197
	198	return 0;
	199	}
	200
	201	static int tegra_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	202	{
	203	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	204	int rc = 0;
	205	u32 val;
	206
	207	rc = clk_prepare_enable(pc->clk);
	208	if (rc < 0)
	209	return rc;
	210
	211	val = pwm_readl(pc, pwm->hwpwm);
	212	val \|= PWM_ENABLE;
	213	pwm_writel(pc, pwm->hwpwm, val);
	214
	215	return 0;
	216	}
	217
	218	static void tegra_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	219	{
	220	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	221	u32 val;
	222
	223	val = pwm_readl(pc, pwm->hwpwm);
	224	val &= ~PWM_ENABLE;
	225	pwm_writel(pc, pwm->hwpwm, val);
	226
	227	clk_disable_unprepare(pc->clk);
	228	}
	229
	230	static const struct pwm_ops tegra_pwm_ops = {
	231	.config = tegra_pwm_config,
	232	.enable = tegra_pwm_enable,
	233	.disable = tegra_pwm_disable,
	234	.owner = THIS_MODULE,
	235	};
	236
	237	static int tegra_pwm_probe(struct platform_device *pdev)
	238	{
	239	struct tegra_pwm_chip *pwm;
0134b932 TR	240	int ret;
	241
	242	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
474b6902	243	if (!pwm)
0134b932	244	return -ENOMEM;
0134b932	245
e9be88a2	246	pwm->soc = of_device_get_match_data(&pdev->dev);
0134b932 TR	247	pwm->dev = &pdev->dev;
0134b932 TR	248
fa44fe41	249	pwm->regs = devm_platform_ioremap_resource(pdev, 0);
4f57f5a0 TR	250	if (IS_ERR(pwm->regs))
4f57f5a0 TR	251	return PTR_ERR(pwm->regs);
0134b932 TR	252
	253	platform_set_drvdata(pdev, pwm);
	254
0c8f527d	255	pwm->clk = devm_clk_get(&pdev->dev, NULL);
0134b932 TR	256	if (IS_ERR(pwm->clk))
	257	return PTR_ERR(pwm->clk);
	258
0527eb37 LD	259	/* Set maximum frequency of the IP */
	260	ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
	261	if (ret < 0) {
	262	dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
	263	return ret;
	264	}
	265
	266	/*
	267	* The requested and configured frequency may differ due to
	268	* clock register resolutions. Get the configured frequency
	269	* so that PWM period can be calculated more accurately.
	270	*/
46fa8bc0 LD	271	pwm->clk_rate = clk_get_rate(pwm->clk);
46fa8bc0 LD	272
1d7796bd SP	273	/* Set minimum limit of PWM period for the IP */
	274	pwm->min_period_ns =
	275	(NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
	276
6b03ef24	277	pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
5dfbd2bd RS	278	if (IS_ERR(pwm->rst)) {
	279	ret = PTR_ERR(pwm->rst);
	280	dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
	281	return ret;
	282	}
	283
	284	reset_control_deassert(pwm->rst);
	285
0134b932 TR	286	pwm->chip.dev = &pdev->dev;
0134b932 TR	287	pwm->chip.ops = &tegra_pwm_ops;
e9be88a2	288	pwm->chip.npwm = pwm->soc->num_channels;
0134b932 TR	289
	290	ret = pwmchip_add(&pwm->chip);
	291	if (ret < 0) {
	292	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
5dfbd2bd	293	reset_control_assert(pwm->rst);
0134b932 TR	294	return ret;
	295	}
	296
	297	return 0;
	298	}
	299
77f37917	300	static int tegra_pwm_remove(struct platform_device *pdev)
0134b932 TR	301	{
0134b932 TR	302	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
5dfbd2bd	303
2f1a3bd4 UKK	304	pwmchip_remove(&pc->chip);
2f1a3bd4 UKK	305
5dfbd2bd	306	reset_control_assert(pc->rst);
5dfbd2bd	307
2f1a3bd4	308	return 0;
0134b932 TR	309	}
0134b932 TR	310
4a813b26 LD	311	#ifdef CONFIG_PM_SLEEP
	312	static int tegra_pwm_suspend(struct device *dev)
	313	{
	314	return pinctrl_pm_select_sleep_state(dev);
	315	}
	316
	317	static int tegra_pwm_resume(struct device *dev)
	318	{
	319	return pinctrl_pm_select_default_state(dev);
	320	}
	321	#endif
	322
e9be88a2 LD	323	static const struct tegra_pwm_soc tegra20_pwm_soc = {
e9be88a2 LD	324	.num_channels = 4,
0527eb37	325	.max_frequency = 48000000UL,
e9be88a2 LD	326	};
	327
	328	static const struct tegra_pwm_soc tegra186_pwm_soc = {
	329	.num_channels = 1,
0527eb37	330	.max_frequency = 102000000UL,
e9be88a2 LD	331	};
e9be88a2 LD	332
2d0c08fc SP	333	static const struct tegra_pwm_soc tegra194_pwm_soc = {
	334	.num_channels = 1,
	335	.max_frequency = 408000000UL,
	336	};
	337
f1a8870a	338	static const struct of_device_id tegra_pwm_of_match[] = {
e9be88a2 LD	339	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
e9be88a2 LD	340	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
2d0c08fc	341	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
140fd977 TR	342	{ }
140fd977 TR	343	};
140fd977	344	MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
140fd977	345
4a813b26 LD	346	static const struct dev_pm_ops tegra_pwm_pm_ops = {
	347	SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
	348	};
	349
0134b932 TR	350	static struct platform_driver tegra_pwm_driver = {
	351	.driver = {
	352	.name = "tegra-pwm",
838bf09d	353	.of_match_table = tegra_pwm_of_match,
4a813b26	354	.pm = &tegra_pwm_pm_ops,
0134b932 TR	355	},
0134b932 TR	356	.probe = tegra_pwm_probe,
fd109112	357	.remove = tegra_pwm_remove,
0134b932 TR	358	};
	359
	360	module_platform_driver(tegra_pwm_driver);
	361
	362	MODULE_LICENSE("GPL");
1d7796bd SP	363	MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
1d7796bd SP	364	MODULE_DESCRIPTION("Tegra PWM controller driver");
0134b932	365	MODULE_ALIAS("platform:tegra-pwm");