[linux-2.6-block.git] / drivers / pwm / pwm-tegra.c

/*
 * drivers/pwm/pwm-tegra.c
 *
 * Tegra pulse-width-modulation controller driver
 *
 * Copyright (c) 2010, NVIDIA Corporation.
 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pwm.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/slab.h>
#include <linux/reset.h>

#define PWM_ENABLE	(1 << 31)
#define PWM_DUTY_WIDTH	8
#define PWM_DUTY_SHIFT	16
#define PWM_SCALE_WIDTH	13
#define PWM_SCALE_SHIFT	0

struct tegra_pwm_soc {
	unsigned int num_channels;

	/* Maximum IP frequency for given SoCs */
	unsigned long max_frequency;
};

struct tegra_pwm_chip {
	struct pwm_chip chip;
	struct device *dev;

	struct clk *clk;
	struct reset_control*rst;

	unsigned long clk_rate;

	void __iomem *regs;

	const struct tegra_pwm_soc *soc;
};

static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct tegra_pwm_chip, chip);
}

static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
{
	return readl(chip->regs + (num << 4));
}

static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
			     unsigned long val)
{
	writel(val, chip->regs + (num << 4));
}

static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			    int duty_ns, int period_ns)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	unsigned long long c = duty_ns, hz;
	unsigned long rate;
	u32 val = 0;
	int err;

	/*
	 * Convert from duty_ns / period_ns to a fixed number of duty ticks
	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
	 * nearest integer during division.
	 */
	c *= (1 << PWM_DUTY_WIDTH);
	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);

	val = (u32)c << PWM_DUTY_SHIFT;

	/*
	 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
	 * cycles at the PWM clock rate will take period_ns nanoseconds.
	 */
	rate = pc->clk_rate >> PWM_DUTY_WIDTH;

	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
	hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns);
	rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);

	/*
	 * Since the actual PWM divider is the register's frequency divider
	 * field minus 1, we need to decrement to get the correct value to
	 * write to the register.
	 */
	if (rate > 0)
		rate--;

	/*
	 * Make sure that the rate will fit in the register's frequency
	 * divider field.
	 */
	if (rate >> PWM_SCALE_WIDTH)
		return -EINVAL;

	val |= rate << PWM_SCALE_SHIFT;

	/*
	 * If the PWM channel is disabled, make sure to turn on the clock
	 * before writing the register. Otherwise, keep it enabled.
	 */
	if (!pwm_is_enabled(pwm)) {
		err = clk_prepare_enable(pc->clk);
		if (err < 0)
			return err;
	} else
		val |= PWM_ENABLE;

	pwm_writel(pc, pwm->hwpwm, val);

	/*
	 * If the PWM is not enabled, turn the clock off again to save power.
	 */
	if (!pwm_is_enabled(pwm))
		clk_disable_unprepare(pc->clk);

	return 0;
}

static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	int rc = 0;
	u32 val;

	rc = clk_prepare_enable(pc->clk);
	if (rc < 0)
		return rc;

	val = pwm_readl(pc, pwm->hwpwm);
	val |= PWM_ENABLE;
	pwm_writel(pc, pwm->hwpwm, val);

	return 0;
}

static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	u32 val;

	val = pwm_readl(pc, pwm->hwpwm);
	val &= ~PWM_ENABLE;
	pwm_writel(pc, pwm->hwpwm, val);

	clk_disable_unprepare(pc->clk);
}

static const struct pwm_ops tegra_pwm_ops = {
	.config = tegra_pwm_config,
	.enable = tegra_pwm_enable,
	.disable = tegra_pwm_disable,
	.owner = THIS_MODULE,
};

static int tegra_pwm_probe(struct platform_device *pdev)
{
	struct tegra_pwm_chip *pwm;
	struct resource *r;
	int ret;

	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
	if (!pwm)
		return -ENOMEM;

	pwm->soc = of_device_get_match_data(&pdev->dev);
	pwm->dev = &pdev->dev;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pwm->regs = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(pwm->regs))
		return PTR_ERR(pwm->regs);

	platform_set_drvdata(pdev, pwm);

	pwm->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pwm->clk))
		return PTR_ERR(pwm->clk);

	/* Set maximum frequency of the IP */
	ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
	if (ret < 0) {
		dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
		return ret;
	}

	/*
	 * The requested and configured frequency may differ due to
	 * clock register resolutions. Get the configured frequency
	 * so that PWM period can be calculated more accurately.
	 */
	pwm->clk_rate = clk_get_rate(pwm->clk);

	pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
	if (IS_ERR(pwm->rst)) {
		ret = PTR_ERR(pwm->rst);
		dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
		return ret;
	}

	reset_control_deassert(pwm->rst);

	pwm->chip.dev = &pdev->dev;
	pwm->chip.ops = &tegra_pwm_ops;
	pwm->chip.base = -1;
	pwm->chip.npwm = pwm->soc->num_channels;

	ret = pwmchip_add(&pwm->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		reset_control_assert(pwm->rst);
		return ret;
	}

	return 0;
}

static int tegra_pwm_remove(struct platform_device *pdev)
{
	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
	unsigned int i;
	int err;

	if (WARN_ON(!pc))
		return -ENODEV;

	err = clk_prepare_enable(pc->clk);
	if (err < 0)
		return err;

	for (i = 0; i < pc->chip.npwm; i++) {
		struct pwm_device *pwm = &pc->chip.pwms[i];

		if (!pwm_is_enabled(pwm))
			if (clk_prepare_enable(pc->clk) < 0)
				continue;

		pwm_writel(pc, i, 0);

		clk_disable_unprepare(pc->clk);
	}

	reset_control_assert(pc->rst);
	clk_disable_unprepare(pc->clk);

	return pwmchip_remove(&pc->chip);
}

#ifdef CONFIG_PM_SLEEP
static int tegra_pwm_suspend(struct device *dev)
{
	return pinctrl_pm_select_sleep_state(dev);
}

static int tegra_pwm_resume(struct device *dev)
{
	return pinctrl_pm_select_default_state(dev);
}
#endif

static const struct tegra_pwm_soc tegra20_pwm_soc = {
	.num_channels = 4,
	.max_frequency = 48000000UL,
};

static const struct tegra_pwm_soc tegra186_pwm_soc = {
	.num_channels = 1,
	.max_frequency = 102000000UL,
};

static const struct of_device_id tegra_pwm_of_match[] = {
	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
	{ }
};

MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);

static const struct dev_pm_ops tegra_pwm_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
};

static struct platform_driver tegra_pwm_driver = {
	.driver = {
		.name = "tegra-pwm",
		.of_match_table = tegra_pwm_of_match,
		.pm = &tegra_pwm_pm_ops,
	},
	.probe = tegra_pwm_probe,
	.remove = tegra_pwm_remove,
};

module_platform_driver(tegra_pwm_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("NVIDIA Corporation");
MODULE_ALIAS("platform:tegra-pwm");
Commit	Line	Data
0134b932 TR	1	/*
	2	* drivers/pwm/pwm-tegra.c
	3	*
	4	* Tegra pulse-width-modulation controller driver
	5	*
	6	* Copyright (c) 2010, NVIDIA Corporation.
	7	* Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful, but WITHOUT
	15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	17	* more details.
	18	*
	19	* You should have received a copy of the GNU General Public License along
	20	* with this program; if not, write to the Free Software Foundation, Inc.,
	21	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	22	*/
	23
	24	#include <linux/clk.h>
	25	#include <linux/err.h>
	26	#include <linux/io.h>
	27	#include <linux/module.h>
	28	#include <linux/of.h>
e9be88a2	29	#include <linux/of_device.h>
0134b932 TR	30	#include <linux/pwm.h>
0134b932 TR	31	#include <linux/platform_device.h>
4a813b26	32	#include <linux/pinctrl/consumer.h>
0134b932	33	#include <linux/slab.h>
5dfbd2bd	34	#include <linux/reset.h>
0134b932 TR	35
	36	#define PWM_ENABLE (1 << 31)
	37	#define PWM_DUTY_WIDTH 8
	38	#define PWM_DUTY_SHIFT 16
	39	#define PWM_SCALE_WIDTH 13
	40	#define PWM_SCALE_SHIFT 0
	41
e9be88a2 LD	42	struct tegra_pwm_soc {
e9be88a2 LD	43	unsigned int num_channels;
0527eb37 LD	44
	45	/* Maximum IP frequency for given SoCs */
	46	unsigned long max_frequency;
e9be88a2 LD	47	};
e9be88a2 LD	48
0134b932	49	struct tegra_pwm_chip {
e17c0b22 TR	50	struct pwm_chip chip;
e17c0b22 TR	51	struct device *dev;
0134b932	52
e17c0b22	53	struct clk *clk;
5dfbd2bd	54	struct reset_control*rst;
0134b932	55
46fa8bc0 LD	56	unsigned long clk_rate;
46fa8bc0 LD	57
4f57f5a0	58	void __iomem *regs;
e9be88a2 LD	59
e9be88a2 LD	60	const struct tegra_pwm_soc *soc;
0134b932 TR	61	};
	62
	63	static inline struct tegra_pwm_chip to_tegra_pwm_chip(struct pwm_chip chip)
	64	{
	65	return container_of(chip, struct tegra_pwm_chip, chip);
	66	}
	67
	68	static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
	69	{
4f57f5a0	70	return readl(chip->regs + (num << 4));
0134b932 TR	71	}
	72
	73	static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
	74	unsigned long val)
	75	{
4f57f5a0	76	writel(val, chip->regs + (num << 4));
0134b932 TR	77	}
	78
	79	static int tegra_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	80	int duty_ns, int period_ns)
	81	{
	82	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
6db78b20 TR	83	unsigned long long c = duty_ns, hz;
6db78b20 TR	84	unsigned long rate;
0134b932 TR	85	u32 val = 0;
	86	int err;
	87
	88	/*
	89	* Convert from duty_ns / period_ns to a fixed number of duty ticks
	90	* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
	91	* nearest integer during division.
	92	*/
b979ed53	93	c *= (1 << PWM_DUTY_WIDTH);
90241fb9	94	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
0134b932 TR	95
	96	val = (u32)c << PWM_DUTY_SHIFT;
	97
	98	/*
	99	* Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
	100	* cycles at the PWM clock rate will take period_ns nanoseconds.
	101	*/
46fa8bc0	102	rate = pc->clk_rate >> PWM_DUTY_WIDTH;
0134b932	103
250b76f4	104	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
6db78b20 TR	105	hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns);
6db78b20 TR	106	rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);
0134b932 TR	107
	108	/*
	109	* Since the actual PWM divider is the register's frequency divider
	110	* field minus 1, we need to decrement to get the correct value to
	111	* write to the register.
	112	*/
	113	if (rate > 0)
	114	rate--;
	115
	116	/*
	117	* Make sure that the rate will fit in the register's frequency
	118	* divider field.
	119	*/
	120	if (rate >> PWM_SCALE_WIDTH)
	121	return -EINVAL;
	122
	123	val \|= rate << PWM_SCALE_SHIFT;
	124
	125	/*
	126	* If the PWM channel is disabled, make sure to turn on the clock
	127	* before writing the register. Otherwise, keep it enabled.
	128	*/
5c31252c	129	if (!pwm_is_enabled(pwm)) {
0134b932 TR	130	err = clk_prepare_enable(pc->clk);
	131	if (err < 0)
	132	return err;
	133	} else
	134	val \|= PWM_ENABLE;
	135
	136	pwm_writel(pc, pwm->hwpwm, val);
	137
	138	/*
	139	* If the PWM is not enabled, turn the clock off again to save power.
	140	*/
5c31252c	141	if (!pwm_is_enabled(pwm))
0134b932 TR	142	clk_disable_unprepare(pc->clk);
	143
	144	return 0;
	145	}
	146
	147	static int tegra_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	148	{
	149	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	150	int rc = 0;
	151	u32 val;
	152
	153	rc = clk_prepare_enable(pc->clk);
	154	if (rc < 0)
	155	return rc;
	156
	157	val = pwm_readl(pc, pwm->hwpwm);
	158	val \|= PWM_ENABLE;
	159	pwm_writel(pc, pwm->hwpwm, val);
	160
	161	return 0;
	162	}
	163
	164	static void tegra_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	165	{
	166	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	167	u32 val;
	168
	169	val = pwm_readl(pc, pwm->hwpwm);
	170	val &= ~PWM_ENABLE;
	171	pwm_writel(pc, pwm->hwpwm, val);
	172
	173	clk_disable_unprepare(pc->clk);
	174	}
	175
	176	static const struct pwm_ops tegra_pwm_ops = {
	177	.config = tegra_pwm_config,
	178	.enable = tegra_pwm_enable,
	179	.disable = tegra_pwm_disable,
	180	.owner = THIS_MODULE,
	181	};
	182
	183	static int tegra_pwm_probe(struct platform_device *pdev)
	184	{
	185	struct tegra_pwm_chip *pwm;
	186	struct resource *r;
	187	int ret;
	188
	189	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
474b6902	190	if (!pwm)
0134b932	191	return -ENOMEM;
0134b932	192
e9be88a2	193	pwm->soc = of_device_get_match_data(&pdev->dev);
0134b932 TR	194	pwm->dev = &pdev->dev;
	195
	196	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4f57f5a0 TR	197	pwm->regs = devm_ioremap_resource(&pdev->dev, r);
	198	if (IS_ERR(pwm->regs))
	199	return PTR_ERR(pwm->regs);
0134b932 TR	200
	201	platform_set_drvdata(pdev, pwm);
	202
0c8f527d	203	pwm->clk = devm_clk_get(&pdev->dev, NULL);
0134b932 TR	204	if (IS_ERR(pwm->clk))
	205	return PTR_ERR(pwm->clk);
	206
0527eb37 LD	207	/* Set maximum frequency of the IP */
	208	ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
	209	if (ret < 0) {
	210	dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
	211	return ret;
	212	}
	213
	214	/*
	215	* The requested and configured frequency may differ due to
	216	* clock register resolutions. Get the configured frequency
	217	* so that PWM period can be calculated more accurately.
	218	*/
46fa8bc0 LD	219	pwm->clk_rate = clk_get_rate(pwm->clk);
46fa8bc0 LD	220
6b03ef24	221	pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
5dfbd2bd RS	222	if (IS_ERR(pwm->rst)) {
	223	ret = PTR_ERR(pwm->rst);
	224	dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
	225	return ret;
	226	}
	227
	228	reset_control_deassert(pwm->rst);
	229
0134b932 TR	230	pwm->chip.dev = &pdev->dev;
	231	pwm->chip.ops = &tegra_pwm_ops;
	232	pwm->chip.base = -1;
e9be88a2	233	pwm->chip.npwm = pwm->soc->num_channels;
0134b932 TR	234
	235	ret = pwmchip_add(&pwm->chip);
	236	if (ret < 0) {
	237	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
5dfbd2bd	238	reset_control_assert(pwm->rst);
0134b932 TR	239	return ret;
	240	}
	241
	242	return 0;
	243	}
	244
77f37917	245	static int tegra_pwm_remove(struct platform_device *pdev)
0134b932 TR	246	{
0134b932 TR	247	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
c009c564	248	unsigned int i;
5dfbd2bd	249	int err;
0134b932 TR	250
	251	if (WARN_ON(!pc))
	252	return -ENODEV;
	253
5dfbd2bd RS	254	err = clk_prepare_enable(pc->clk);
	255	if (err < 0)
	256	return err;
	257
c009c564	258	for (i = 0; i < pc->chip.npwm; i++) {
0134b932 TR	259	struct pwm_device *pwm = &pc->chip.pwms[i];
0134b932 TR	260
5c31252c	261	if (!pwm_is_enabled(pwm))
0134b932 TR	262	if (clk_prepare_enable(pc->clk) < 0)
	263	continue;
	264
	265	pwm_writel(pc, i, 0);
	266
	267	clk_disable_unprepare(pc->clk);
	268	}
	269
5dfbd2bd RS	270	reset_control_assert(pc->rst);
	271	clk_disable_unprepare(pc->clk);
	272
0c8f527d	273	return pwmchip_remove(&pc->chip);
0134b932 TR	274	}
0134b932 TR	275
4a813b26 LD	276	#ifdef CONFIG_PM_SLEEP
	277	static int tegra_pwm_suspend(struct device *dev)
	278	{
	279	return pinctrl_pm_select_sleep_state(dev);
	280	}
	281
	282	static int tegra_pwm_resume(struct device *dev)
	283	{
	284	return pinctrl_pm_select_default_state(dev);
	285	}
	286	#endif
	287
e9be88a2 LD	288	static const struct tegra_pwm_soc tegra20_pwm_soc = {
e9be88a2 LD	289	.num_channels = 4,
0527eb37	290	.max_frequency = 48000000UL,
e9be88a2 LD	291	};
	292
	293	static const struct tegra_pwm_soc tegra186_pwm_soc = {
	294	.num_channels = 1,
0527eb37	295	.max_frequency = 102000000UL,
e9be88a2 LD	296	};
e9be88a2 LD	297
f1a8870a	298	static const struct of_device_id tegra_pwm_of_match[] = {
e9be88a2 LD	299	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
e9be88a2 LD	300	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
140fd977 TR	301	{ }
	302	};
	303
	304	MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
140fd977	305
4a813b26 LD	306	static const struct dev_pm_ops tegra_pwm_pm_ops = {
	307	SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
	308	};
	309
0134b932 TR	310	static struct platform_driver tegra_pwm_driver = {
	311	.driver = {
	312	.name = "tegra-pwm",
838bf09d	313	.of_match_table = tegra_pwm_of_match,
4a813b26	314	.pm = &tegra_pwm_pm_ops,
0134b932 TR	315	},
0134b932 TR	316	.probe = tegra_pwm_probe,
fd109112	317	.remove = tegra_pwm_remove,
0134b932 TR	318	};
	319
	320	module_platform_driver(tegra_pwm_driver);
	321
	322	MODULE_LICENSE("GPL");
	323	MODULE_AUTHOR("NVIDIA Corporation");
	324	MODULE_ALIAS("platform:tegra-pwm");