[linux-block.git] / drivers / pwm / pwm-tegra.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * drivers/pwm/pwm-tegra.c
 *
 * Tegra pulse-width-modulation controller driver
 *
 * Copyright (c) 2010-2020, NVIDIA Corporation.
 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
 *
 * Overview of Tegra Pulse Width Modulator Register:
 * 1. 13-bit: Frequency division (SCALE)
 * 2. 8-bit : Pulse division (DUTY)
 * 3. 1-bit : Enable bit
 *
 * The PWM clock frequency is divided by 256 before subdividing it based
 * on the programmable frequency division value to generate the required
 * frequency for PWM output. The maximum output frequency that can be
 * achieved is (max rate of source clock) / 256.
 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
 * 408 MHz/256 = 1.6 MHz.
 * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
 *
 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
 * To achieve 100% duty cycle, program Bit [24] of this register to
 * 1’b1. In which case the other bits [23:16] are set to don't care.
 *
 * Limitations:
 * -	When PWM is disabled, the output is driven to inactive.
 * -	It does not allow the current PWM period to complete and
 *	stops abruptly.
 *
 * -	If the register is reconfigured while PWM is running,
 *	it does not complete the currently running period.
 *
 * -	If the user input duty is beyond acceptible limits,
 *	-EINVAL is returned.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/pwm.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/reset.h>

#include <soc/tegra/common.h>

#define PWM_ENABLE	(1 << 31)
#define PWM_DUTY_WIDTH	8
#define PWM_DUTY_SHIFT	16
#define PWM_SCALE_WIDTH	13
#define PWM_SCALE_SHIFT	0

struct tegra_pwm_soc {
	unsigned int num_channels;

	/* Maximum IP frequency for given SoCs */
	unsigned long max_frequency;
};

struct tegra_pwm_chip {
	struct clk *clk;
	struct reset_control*rst;

	unsigned long clk_rate;
	unsigned long min_period_ns;

	void __iomem *regs;

	const struct tegra_pwm_soc *soc;
};

static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset)
{
	return readl(pc->regs + (offset << 4));
}

static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value)
{
	writel(value, pc->regs + (offset << 4));
}

static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			    int duty_ns, int period_ns)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	unsigned long long c = duty_ns;
	unsigned long rate, required_clk_rate;
	u32 val = 0;
	int err;

	/*
	 * Convert from duty_ns / period_ns to a fixed number of duty ticks
	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
	 * nearest integer during division.
	 */
	c *= (1 << PWM_DUTY_WIDTH);
	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);

	val = (u32)c << PWM_DUTY_SHIFT;

	/*
	 *  min period = max clock limit >> PWM_DUTY_WIDTH
	 */
	if (period_ns < pc->min_period_ns)
		return -EINVAL;

	/*
	 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
	 * cycles at the PWM clock rate will take period_ns nanoseconds.
	 *
	 * num_channels: If single instance of PWM controller has multiple
	 * channels (e.g. Tegra210 or older) then it is not possible to
	 * configure separate clock rates to each of the channels, in such
	 * case the value stored during probe will be referred.
	 *
	 * If every PWM controller instance has one channel respectively, i.e.
	 * nums_channels == 1 then only the clock rate can be modified
	 * dynamically (e.g. Tegra186 or Tegra194).
	 */
	if (pc->soc->num_channels == 1) {
		/*
		 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
		 * with the maximum possible rate that the controller can
		 * provide. Any further lower value can be derived by setting
		 * PFM bits[0:12].
		 *
		 * required_clk_rate is a reference rate for source clock and
		 * it is derived based on user requested period. By setting the
		 * source clock rate as required_clk_rate, PWM controller will
		 * be able to configure the requested period.
		 */
		required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
						     period_ns);

		if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
			/*
			 * required_clk_rate is a lower bound for the input
			 * rate; for lower rates there is no value for PWM_SCALE
			 * that yields a period less than or equal to the
			 * requested period. Hence, for lower rates, double the
			 * required_clk_rate to get a clock rate that can meet
			 * the requested period.
			 */
			required_clk_rate *= 2;

		err = dev_pm_opp_set_rate(pwmchip_parent(chip), required_clk_rate);
		if (err < 0)
			return -EINVAL;

		/* Store the new rate for further references */
		pc->clk_rate = clk_get_rate(pc->clk);
	}

	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
	rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,
				   (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH);

	/*
	 * Since the actual PWM divider is the register's frequency divider
	 * field plus 1, we need to decrement to get the correct value to
	 * write to the register.
	 */
	if (rate > 0)
		rate--;
	else
		return -EINVAL;

	/*
	 * Make sure that the rate will fit in the register's frequency
	 * divider field.
	 */
	if (rate >> PWM_SCALE_WIDTH)
		return -EINVAL;

	val |= rate << PWM_SCALE_SHIFT;

	/*
	 * If the PWM channel is disabled, make sure to turn on the clock
	 * before writing the register. Otherwise, keep it enabled.
	 */
	if (!pwm_is_enabled(pwm)) {
		err = pm_runtime_resume_and_get(pwmchip_parent(chip));
		if (err)
			return err;
	} else
		val |= PWM_ENABLE;

	pwm_writel(pc, pwm->hwpwm, val);

	/*
	 * If the PWM is not enabled, turn the clock off again to save power.
	 */
	if (!pwm_is_enabled(pwm))
		pm_runtime_put(pwmchip_parent(chip));

	return 0;
}

static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	int rc = 0;
	u32 val;

	rc = pm_runtime_resume_and_get(pwmchip_parent(chip));
	if (rc)
		return rc;

	val = pwm_readl(pc, pwm->hwpwm);
	val |= PWM_ENABLE;
	pwm_writel(pc, pwm->hwpwm, val);

	return 0;
}

static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	u32 val;

	val = pwm_readl(pc, pwm->hwpwm);
	val &= ~PWM_ENABLE;
	pwm_writel(pc, pwm->hwpwm, val);

	pm_runtime_put_sync(pwmchip_parent(chip));
}

static int tegra_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{
	int err;
	bool enabled = pwm->state.enabled;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (!state->enabled) {
		if (enabled)
			tegra_pwm_disable(chip, pwm);

		return 0;
	}

	err = tegra_pwm_config(chip, pwm, state->duty_cycle, state->period);
	if (err)
		return err;

	if (!enabled)
		err = tegra_pwm_enable(chip, pwm);

	return err;
}

static const struct pwm_ops tegra_pwm_ops = {
	.apply = tegra_pwm_apply,
};

static int tegra_pwm_probe(struct platform_device *pdev)
{
	struct pwm_chip *chip;
	struct tegra_pwm_chip *pc;
	const struct tegra_pwm_soc *soc;
	int ret;

	soc = of_device_get_match_data(&pdev->dev);

	chip = devm_pwmchip_alloc(&pdev->dev, soc->num_channels, sizeof(*pc));
	if (IS_ERR(chip))
		return PTR_ERR(chip);
	pc = to_tegra_pwm_chip(chip);

	pc->soc = soc;

	pc->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pc->regs))
		return PTR_ERR(pc->regs);

	platform_set_drvdata(pdev, chip);

	pc->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pc->clk))
		return PTR_ERR(pc->clk);

	ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
	if (ret)
		return ret;

	pm_runtime_enable(&pdev->dev);
	ret = pm_runtime_resume_and_get(&pdev->dev);
	if (ret)
		return ret;

	/* Set maximum frequency of the IP */
	ret = dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency);
	if (ret < 0) {
		dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
		goto put_pm;
	}

	/*
	 * The requested and configured frequency may differ due to
	 * clock register resolutions. Get the configured frequency
	 * so that PWM period can be calculated more accurately.
	 */
	pc->clk_rate = clk_get_rate(pc->clk);

	/* Set minimum limit of PWM period for the IP */
	pc->min_period_ns =
	    (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;

	pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
	if (IS_ERR(pc->rst)) {
		ret = PTR_ERR(pc->rst);
		dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
		goto put_pm;
	}

	reset_control_deassert(pc->rst);

	chip->ops = &tegra_pwm_ops;

	ret = pwmchip_add(chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		reset_control_assert(pc->rst);
		goto put_pm;
	}

	pm_runtime_put(&pdev->dev);

	return 0;
put_pm:
	pm_runtime_put_sync_suspend(&pdev->dev);
	pm_runtime_force_suspend(&pdev->dev);
	return ret;
}

static void tegra_pwm_remove(struct platform_device *pdev)
{
	struct pwm_chip *chip = platform_get_drvdata(pdev);
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);

	pwmchip_remove(chip);

	reset_control_assert(pc->rst);

	pm_runtime_force_suspend(&pdev->dev);
}

static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev)
{
	struct pwm_chip *chip = dev_get_drvdata(dev);
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	int err;

	clk_disable_unprepare(pc->clk);

	err = pinctrl_pm_select_sleep_state(dev);
	if (err) {
		clk_prepare_enable(pc->clk);
		return err;
	}

	return 0;
}

static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)
{
	struct pwm_chip *chip = dev_get_drvdata(dev);
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	int err;

	err = pinctrl_pm_select_default_state(dev);
	if (err)
		return err;

	err = clk_prepare_enable(pc->clk);
	if (err) {
		pinctrl_pm_select_sleep_state(dev);
		return err;
	}

	return 0;
}

static const struct tegra_pwm_soc tegra20_pwm_soc = {
	.num_channels = 4,
	.max_frequency = 48000000UL,
};

static const struct tegra_pwm_soc tegra186_pwm_soc = {
	.num_channels = 1,
	.max_frequency = 102000000UL,
};

static const struct tegra_pwm_soc tegra194_pwm_soc = {
	.num_channels = 1,
	.max_frequency = 408000000UL,
};

static const struct of_device_id tegra_pwm_of_match[] = {
	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
	{ }
};
MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);

static const struct dev_pm_ops tegra_pwm_pm_ops = {
	SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume,
			   NULL)
	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				pm_runtime_force_resume)
};

static struct platform_driver tegra_pwm_driver = {
	.driver = {
		.name = "tegra-pwm",
		.of_match_table = tegra_pwm_of_match,
		.pm = &tegra_pwm_pm_ops,
	},
	.probe = tegra_pwm_probe,
	.remove_new = tegra_pwm_remove,
};

module_platform_driver(tegra_pwm_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
MODULE_DESCRIPTION("Tegra PWM controller driver");
MODULE_ALIAS("platform:tegra-pwm");
Commit	Line	Data
16216333	1	// SPDX-License-Identifier: GPL-2.0-or-later
0134b932 TR	2	/*
	3	* drivers/pwm/pwm-tegra.c
	4	*
	5	* Tegra pulse-width-modulation controller driver
	6	*
1d7796bd	7	* Copyright (c) 2010-2020, NVIDIA Corporation.
0134b932	8	* Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
1d7796bd SP	9	*
	10	* Overview of Tegra Pulse Width Modulator Register:
	11	* 1. 13-bit: Frequency division (SCALE)
	12	* 2. 8-bit : Pulse division (DUTY)
	13	* 3. 1-bit : Enable bit
	14	*
	15	* The PWM clock frequency is divided by 256 before subdividing it based
	16	* on the programmable frequency division value to generate the required
	17	* frequency for PWM output. The maximum output frequency that can be
	18	* achieved is (max rate of source clock) / 256.
	19	* e.g. if source clock rate is 408 MHz, maximum output frequency can be:
	20	* 408 MHz/256 = 1.6 MHz.
	21	* This 1.6 MHz frequency can further be divided using SCALE value in PWM.
	22	*
	23	* PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
	24	* To achieve 100% duty cycle, program Bit [24] of this register to
	25	* 1’b1. In which case the other bits [23:16] are set to don't care.
	26	*
	27	* Limitations:
	28	* - When PWM is disabled, the output is driven to inactive.
	29	* - It does not allow the current PWM period to complete and
	30	* stops abruptly.
	31	*
	32	* - If the register is reconfigured while PWM is running,
	33	* it does not complete the currently running period.
	34	*
	35	* - If the user input duty is beyond acceptible limits,
	36	* -EINVAL is returned.
0134b932 TR	37	*/
	38
	39	#include <linux/clk.h>
	40	#include <linux/err.h>
	41	#include <linux/io.h>
	42	#include <linux/module.h>
	43	#include <linux/of.h>
3da9b0fe	44	#include <linux/pm_opp.h>
0134b932 TR	45	#include <linux/pwm.h>
0134b932 TR	46	#include <linux/platform_device.h>
4a813b26	47	#include <linux/pinctrl/consumer.h>
3da9b0fe	48	#include <linux/pm_runtime.h>
0134b932	49	#include <linux/slab.h>
5dfbd2bd	50	#include <linux/reset.h>
0134b932	51
3da9b0fe DO	52	#include <soc/tegra/common.h>
3da9b0fe DO	53
0134b932 TR	54	#define PWM_ENABLE (1 << 31)
	55	#define PWM_DUTY_WIDTH 8
	56	#define PWM_DUTY_SHIFT 16
	57	#define PWM_SCALE_WIDTH 13
	58	#define PWM_SCALE_SHIFT 0
	59
e9be88a2 LD	60	struct tegra_pwm_soc {
e9be88a2 LD	61	unsigned int num_channels;
0527eb37 LD	62
	63	/* Maximum IP frequency for given SoCs */
	64	unsigned long max_frequency;
e9be88a2 LD	65	};
e9be88a2 LD	66
0134b932	67	struct tegra_pwm_chip {
e17c0b22	68	struct clk *clk;
5dfbd2bd	69	struct reset_control*rst;
0134b932	70
46fa8bc0	71	unsigned long clk_rate;
1d7796bd	72	unsigned long min_period_ns;
46fa8bc0	73
4f57f5a0	74	void __iomem *regs;
e9be88a2 LD	75
e9be88a2 LD	76	const struct tegra_pwm_soc *soc;
0134b932 TR	77	};
	78
	79	static inline struct tegra_pwm_chip to_tegra_pwm_chip(struct pwm_chip chip)
	80	{
7550ebf0	81	return pwmchip_get_drvdata(chip);
0134b932 TR	82	}
0134b932 TR	83
f19460c1	84	static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset)
0134b932	85	{
f19460c1	86	return readl(pc->regs + (offset << 4));
0134b932 TR	87	}
0134b932 TR	88
f19460c1	89	static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value)
0134b932	90	{
f19460c1	91	writel(value, pc->regs + (offset << 4));
0134b932 TR	92	}
	93
	94	static int tegra_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	95	int duty_ns, int period_ns)
	96	{
	97	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
8c193f47	98	unsigned long long c = duty_ns;
1d7796bd	99	unsigned long rate, required_clk_rate;
0134b932 TR	100	u32 val = 0;
	101	int err;
	102
	103	/*
	104	* Convert from duty_ns / period_ns to a fixed number of duty ticks
	105	* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
	106	* nearest integer during division.
	107	*/
b979ed53	108	c *= (1 << PWM_DUTY_WIDTH);
90241fb9	109	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
0134b932 TR	110
	111	val = (u32)c << PWM_DUTY_SHIFT;
	112
1d7796bd SP	113	/*
	114	* min period = max clock limit >> PWM_DUTY_WIDTH
	115	*/
	116	if (period_ns < pc->min_period_ns)
	117	return -EINVAL;
	118
0134b932 TR	119	/*
	120	* Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
	121	* cycles at the PWM clock rate will take period_ns nanoseconds.
1d7796bd SP	122	*
	123	* num_channels: If single instance of PWM controller has multiple
	124	* channels (e.g. Tegra210 or older) then it is not possible to
	125	* configure separate clock rates to each of the channels, in such
	126	* case the value stored during probe will be referred.
	127	*
	128	* If every PWM controller instance has one channel respectively, i.e.
	129	* nums_channels == 1 then only the clock rate can be modified
	130	* dynamically (e.g. Tegra186 or Tegra194).
0134b932	131	*/
1d7796bd SP	132	if (pc->soc->num_channels == 1) {
	133	/*
	134	* Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
	135	* with the maximum possible rate that the controller can
	136	* provide. Any further lower value can be derived by setting
	137	* PFM bits[0:12].
	138	*
	139	* required_clk_rate is a reference rate for source clock and
	140	* it is derived based on user requested period. By setting the
	141	* source clock rate as required_clk_rate, PWM controller will
	142	* be able to configure the requested period.
	143	*/
dd1f1da4	144	required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
f2719461	145	period_ns);
1d7796bd	146
5eccd0d9 JH	147	if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
	148	/*
	149	* required_clk_rate is a lower bound for the input
	150	* rate; for lower rates there is no value for PWM_SCALE
	151	* that yields a period less than or equal to the
	152	* requested period. Hence, for lower rates, double the
	153	* required_clk_rate to get a clock rate that can meet
	154	* the requested period.
	155	*/
	156	required_clk_rate *= 2;
	157
b662c6e8	158	err = dev_pm_opp_set_rate(pwmchip_parent(chip), required_clk_rate);
1d7796bd SP	159	if (err < 0)
	160	return -EINVAL;
	161
	162	/* Store the new rate for further references */
	163	pc->clk_rate = clk_get_rate(pc->clk);
	164	}
	165
250b76f4	166	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
8c193f47 UKK	167	rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,
8c193f47 UKK	168	(u64)NSEC_PER_SEC << PWM_DUTY_WIDTH);
0134b932 TR	169
	170	/*
	171	* Since the actual PWM divider is the register's frequency divider
1d7796bd	172	* field plus 1, we need to decrement to get the correct value to
0134b932 TR	173	* write to the register.
	174	*/
	175	if (rate > 0)
	176	rate--;
8c193f47 UKK	177	else
8c193f47 UKK	178	return -EINVAL;
0134b932 TR	179
	180	/*
	181	* Make sure that the rate will fit in the register's frequency
	182	* divider field.
	183	*/
	184	if (rate >> PWM_SCALE_WIDTH)
	185	return -EINVAL;
	186
	187	val \|= rate << PWM_SCALE_SHIFT;
	188
	189	/*
	190	* If the PWM channel is disabled, make sure to turn on the clock
	191	* before writing the register. Otherwise, keep it enabled.
	192	*/
5c31252c	193	if (!pwm_is_enabled(pwm)) {
b662c6e8	194	err = pm_runtime_resume_and_get(pwmchip_parent(chip));
3da9b0fe	195	if (err)
0134b932 TR	196	return err;
	197	} else
	198	val \|= PWM_ENABLE;
	199
	200	pwm_writel(pc, pwm->hwpwm, val);
	201
	202	/*
	203	* If the PWM is not enabled, turn the clock off again to save power.
	204	*/
5c31252c	205	if (!pwm_is_enabled(pwm))
b662c6e8	206	pm_runtime_put(pwmchip_parent(chip));
0134b932 TR	207
	208	return 0;
	209	}
	210
	211	static int tegra_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	212	{
	213	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	214	int rc = 0;
	215	u32 val;
	216
b662c6e8	217	rc = pm_runtime_resume_and_get(pwmchip_parent(chip));
3da9b0fe	218	if (rc)
0134b932 TR	219	return rc;
	220
	221	val = pwm_readl(pc, pwm->hwpwm);
	222	val \|= PWM_ENABLE;
	223	pwm_writel(pc, pwm->hwpwm, val);
	224
	225	return 0;
	226	}
	227
	228	static void tegra_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	229	{
	230	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	231	u32 val;
	232
	233	val = pwm_readl(pc, pwm->hwpwm);
	234	val &= ~PWM_ENABLE;
	235	pwm_writel(pc, pwm->hwpwm, val);
	236
b662c6e8	237	pm_runtime_put_sync(pwmchip_parent(chip));
0134b932 TR	238	}
0134b932 TR	239
fd3ddd43 UKK	240	static int tegra_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	241	const struct pwm_state *state)
	242	{
	243	int err;
	244	bool enabled = pwm->state.enabled;
	245
	246	if (state->polarity != PWM_POLARITY_NORMAL)
	247	return -EINVAL;
	248
	249	if (!state->enabled) {
	250	if (enabled)
	251	tegra_pwm_disable(chip, pwm);
	252
	253	return 0;
	254	}
	255
80943bbd	256	err = tegra_pwm_config(chip, pwm, state->duty_cycle, state->period);
fd3ddd43 UKK	257	if (err)
	258	return err;
	259
	260	if (!enabled)
	261	err = tegra_pwm_enable(chip, pwm);
	262
	263	return err;
	264	}
	265
0134b932	266	static const struct pwm_ops tegra_pwm_ops = {
fd3ddd43	267	.apply = tegra_pwm_apply,
0134b932 TR	268	};
	269
	270	static int tegra_pwm_probe(struct platform_device *pdev)
	271	{
aa37f83f	272	struct pwm_chip *chip;
f19460c1	273	struct tegra_pwm_chip *pc;
7550ebf0	274	const struct tegra_pwm_soc *soc;
0134b932 TR	275	int ret;
0134b932 TR	276
7550ebf0 UKK	277	soc = of_device_get_match_data(&pdev->dev);
	278
	279	chip = devm_pwmchip_alloc(&pdev->dev, soc->num_channels, sizeof(*pc));
	280	if (IS_ERR(chip))
	281	return PTR_ERR(chip);
	282	pc = to_tegra_pwm_chip(chip);
0134b932	283
7550ebf0	284	pc->soc = soc;
0134b932	285
f19460c1 UKK	286	pc->regs = devm_platform_ioremap_resource(pdev, 0);
	287	if (IS_ERR(pc->regs))
	288	return PTR_ERR(pc->regs);
0134b932	289
aa37f83f	290	platform_set_drvdata(pdev, chip);
0134b932	291
f19460c1 UKK	292	pc->clk = devm_clk_get(&pdev->dev, NULL);
	293	if (IS_ERR(pc->clk))
	294	return PTR_ERR(pc->clk);
0134b932	295
3da9b0fe DO	296	ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
	297	if (ret)
	298	return ret;
	299
	300	pm_runtime_enable(&pdev->dev);
	301	ret = pm_runtime_resume_and_get(&pdev->dev);
	302	if (ret)
	303	return ret;
	304
0527eb37	305	/* Set maximum frequency of the IP */
b662c6e8	306	ret = dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency);
0527eb37 LD	307	if (ret < 0) {
0527eb37 LD	308	dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
3da9b0fe	309	goto put_pm;
0527eb37 LD	310	}
	311
	312	/*
	313	* The requested and configured frequency may differ due to
	314	* clock register resolutions. Get the configured frequency
	315	* so that PWM period can be calculated more accurately.
	316	*/
f19460c1	317	pc->clk_rate = clk_get_rate(pc->clk);
46fa8bc0	318
1d7796bd	319	/* Set minimum limit of PWM period for the IP */
f19460c1 UKK	320	pc->min_period_ns =
f19460c1 UKK	321	(NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
1d7796bd	322
f19460c1 UKK	323	pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
	324	if (IS_ERR(pc->rst)) {
	325	ret = PTR_ERR(pc->rst);
5dfbd2bd	326	dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
3da9b0fe	327	goto put_pm;
5dfbd2bd RS	328	}
5dfbd2bd RS	329
f19460c1	330	reset_control_deassert(pc->rst);
5dfbd2bd	331
aa37f83f	332	chip->ops = &tegra_pwm_ops;
0134b932	333
aa37f83f	334	ret = pwmchip_add(chip);
0134b932 TR	335	if (ret < 0) {
0134b932 TR	336	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
f19460c1	337	reset_control_assert(pc->rst);
3da9b0fe	338	goto put_pm;
0134b932 TR	339	}
0134b932 TR	340
3da9b0fe DO	341	pm_runtime_put(&pdev->dev);
3da9b0fe DO	342
0134b932	343	return 0;
3da9b0fe DO	344	put_pm:
	345	pm_runtime_put_sync_suspend(&pdev->dev);
	346	pm_runtime_force_suspend(&pdev->dev);
	347	return ret;
0134b932 TR	348	}
0134b932 TR	349
e39cb6f9	350	static void tegra_pwm_remove(struct platform_device *pdev)
0134b932	351	{
aa37f83f UKK	352	struct pwm_chip *chip = platform_get_drvdata(pdev);
aa37f83f UKK	353	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
5dfbd2bd	354
aa37f83f	355	pwmchip_remove(chip);
2f1a3bd4	356
5dfbd2bd	357	reset_control_assert(pc->rst);
5dfbd2bd	358
3da9b0fe	359	pm_runtime_force_suspend(&pdev->dev);
0134b932 TR	360	}
0134b932 TR	361
3da9b0fe	362	static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev)
4a813b26	363	{
aa37f83f UKK	364	struct pwm_chip *chip = dev_get_drvdata(dev);
aa37f83f UKK	365	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
3da9b0fe DO	366	int err;
	367
	368	clk_disable_unprepare(pc->clk);
	369
	370	err = pinctrl_pm_select_sleep_state(dev);
	371	if (err) {
	372	clk_prepare_enable(pc->clk);
	373	return err;
	374	}
	375
	376	return 0;
4a813b26 LD	377	}
4a813b26 LD	378
3da9b0fe	379	static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)
4a813b26	380	{
aa37f83f UKK	381	struct pwm_chip *chip = dev_get_drvdata(dev);
aa37f83f UKK	382	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
3da9b0fe DO	383	int err;
	384
	385	err = pinctrl_pm_select_default_state(dev);
	386	if (err)
	387	return err;
	388
	389	err = clk_prepare_enable(pc->clk);
	390	if (err) {
	391	pinctrl_pm_select_sleep_state(dev);
	392	return err;
	393	}
	394
	395	return 0;
4a813b26	396	}
4a813b26	397
e9be88a2 LD	398	static const struct tegra_pwm_soc tegra20_pwm_soc = {
e9be88a2 LD	399	.num_channels = 4,
0527eb37	400	.max_frequency = 48000000UL,
e9be88a2 LD	401	};
	402
	403	static const struct tegra_pwm_soc tegra186_pwm_soc = {
	404	.num_channels = 1,
0527eb37	405	.max_frequency = 102000000UL,
e9be88a2 LD	406	};
e9be88a2 LD	407
2d0c08fc SP	408	static const struct tegra_pwm_soc tegra194_pwm_soc = {
	409	.num_channels = 1,
	410	.max_frequency = 408000000UL,
	411	};
	412
f1a8870a	413	static const struct of_device_id tegra_pwm_of_match[] = {
e9be88a2 LD	414	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
e9be88a2 LD	415	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
2d0c08fc	416	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
140fd977 TR	417	{ }
140fd977 TR	418	};
140fd977	419	MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
140fd977	420
4a813b26	421	static const struct dev_pm_ops tegra_pwm_pm_ops = {
3da9b0fe DO	422	SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume,
	423	NULL)
	424	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	425	pm_runtime_force_resume)
4a813b26 LD	426	};
4a813b26 LD	427
0134b932 TR	428	static struct platform_driver tegra_pwm_driver = {
	429	.driver = {
	430	.name = "tegra-pwm",
838bf09d	431	.of_match_table = tegra_pwm_of_match,
4a813b26	432	.pm = &tegra_pwm_pm_ops,
0134b932 TR	433	},
0134b932 TR	434	.probe = tegra_pwm_probe,
e39cb6f9	435	.remove_new = tegra_pwm_remove,
0134b932 TR	436	};
	437
	438	module_platform_driver(tegra_pwm_driver);
	439
	440	MODULE_LICENSE("GPL");
1d7796bd SP	441	MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
1d7796bd SP	442	MODULE_DESCRIPTION("Tegra PWM controller driver");
0134b932	443	MODULE_ALIAS("platform:tegra-pwm");