[linux-block.git] / drivers / pwm / pwm-tegra.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * drivers/pwm/pwm-tegra.c
 *
 * Tegra pulse-width-modulation controller driver
 *
 * Copyright (c) 2010-2020, NVIDIA Corporation.
 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
 *
 * Overview of Tegra Pulse Width Modulator Register:
 * 1. 13-bit: Frequency division (SCALE)
 * 2. 8-bit : Pulse division (DUTY)
 * 3. 1-bit : Enable bit
 *
 * The PWM clock frequency is divided by 256 before subdividing it based
 * on the programmable frequency division value to generate the required
 * frequency for PWM output. The maximum output frequency that can be
 * achieved is (max rate of source clock) / 256.
 * e.g. if source clock rate is 408 MHz, maximum output frequency can be:
 * 408 MHz/256 = 1.6 MHz.
 * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
 *
 * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
 * To achieve 100% duty cycle, program Bit [24] of this register to
 * 1’b1. In which case the other bits [23:16] are set to don't care.
 *
 * Limitations:
 * -	When PWM is disabled, the output is driven to inactive.
 * -	It does not allow the current PWM period to complete and
 *	stops abruptly.
 *
 * -	If the register is reconfigured while PWM is running,
 *	it does not complete the currently running period.
 *
 * -	If the user input duty is beyond acceptible limits,
 *	-EINVAL is returned.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm_opp.h>
#include <linux/pwm.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/reset.h>

#include <soc/tegra/common.h>

#define PWM_ENABLE	(1 << 31)
#define PWM_DUTY_WIDTH	8
#define PWM_DUTY_SHIFT	16
#define PWM_SCALE_WIDTH	13
#define PWM_SCALE_SHIFT	0

struct tegra_pwm_soc {
	unsigned int num_channels;

	/* Maximum IP frequency for given SoCs */
	unsigned long max_frequency;
};

struct tegra_pwm_chip {
	struct pwm_chip chip;
	struct device *dev;

	struct clk *clk;
	struct reset_control*rst;

	unsigned long clk_rate;
	unsigned long min_period_ns;

	void __iomem *regs;

	const struct tegra_pwm_soc *soc;
};

static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct tegra_pwm_chip, chip);
}

static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset)
{
	return readl(pc->regs + (offset << 4));
}

static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value)
{
	writel(value, pc->regs + (offset << 4));
}

static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			    int duty_ns, int period_ns)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	unsigned long long c = duty_ns;
	unsigned long rate, required_clk_rate;
	u32 val = 0;
	int err;

	/*
	 * Convert from duty_ns / period_ns to a fixed number of duty ticks
	 * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
	 * nearest integer during division.
	 */
	c *= (1 << PWM_DUTY_WIDTH);
	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);

	val = (u32)c << PWM_DUTY_SHIFT;

	/*
	 *  min period = max clock limit >> PWM_DUTY_WIDTH
	 */
	if (period_ns < pc->min_period_ns)
		return -EINVAL;

	/*
	 * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
	 * cycles at the PWM clock rate will take period_ns nanoseconds.
	 *
	 * num_channels: If single instance of PWM controller has multiple
	 * channels (e.g. Tegra210 or older) then it is not possible to
	 * configure separate clock rates to each of the channels, in such
	 * case the value stored during probe will be referred.
	 *
	 * If every PWM controller instance has one channel respectively, i.e.
	 * nums_channels == 1 then only the clock rate can be modified
	 * dynamically (e.g. Tegra186 or Tegra194).
	 */
	if (pc->soc->num_channels == 1) {
		/*
		 * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
		 * with the maximum possible rate that the controller can
		 * provide. Any further lower value can be derived by setting
		 * PFM bits[0:12].
		 *
		 * required_clk_rate is a reference rate for source clock and
		 * it is derived based on user requested period. By setting the
		 * source clock rate as required_clk_rate, PWM controller will
		 * be able to configure the requested period.
		 */
		required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
						     period_ns);

		if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
			/*
			 * required_clk_rate is a lower bound for the input
			 * rate; for lower rates there is no value for PWM_SCALE
			 * that yields a period less than or equal to the
			 * requested period. Hence, for lower rates, double the
			 * required_clk_rate to get a clock rate that can meet
			 * the requested period.
			 */
			required_clk_rate *= 2;

		err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);
		if (err < 0)
			return -EINVAL;

		/* Store the new rate for further references */
		pc->clk_rate = clk_get_rate(pc->clk);
	}

	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
	rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,
				   (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH);

	/*
	 * Since the actual PWM divider is the register's frequency divider
	 * field plus 1, we need to decrement to get the correct value to
	 * write to the register.
	 */
	if (rate > 0)
		rate--;
	else
		return -EINVAL;

	/*
	 * Make sure that the rate will fit in the register's frequency
	 * divider field.
	 */
	if (rate >> PWM_SCALE_WIDTH)
		return -EINVAL;

	val |= rate << PWM_SCALE_SHIFT;

	/*
	 * If the PWM channel is disabled, make sure to turn on the clock
	 * before writing the register. Otherwise, keep it enabled.
	 */
	if (!pwm_is_enabled(pwm)) {
		err = pm_runtime_resume_and_get(pc->dev);
		if (err)
			return err;
	} else
		val |= PWM_ENABLE;

	pwm_writel(pc, pwm->hwpwm, val);

	/*
	 * If the PWM is not enabled, turn the clock off again to save power.
	 */
	if (!pwm_is_enabled(pwm))
		pm_runtime_put(pc->dev);

	return 0;
}

static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	int rc = 0;
	u32 val;

	rc = pm_runtime_resume_and_get(pc->dev);
	if (rc)
		return rc;

	val = pwm_readl(pc, pwm->hwpwm);
	val |= PWM_ENABLE;
	pwm_writel(pc, pwm->hwpwm, val);

	return 0;
}

static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	u32 val;

	val = pwm_readl(pc, pwm->hwpwm);
	val &= ~PWM_ENABLE;
	pwm_writel(pc, pwm->hwpwm, val);

	pm_runtime_put_sync(pc->dev);
}

static int tegra_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{
	int err;
	bool enabled = pwm->state.enabled;

	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	if (!state->enabled) {
		if (enabled)
			tegra_pwm_disable(chip, pwm);

		return 0;
	}

	err = tegra_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
	if (err)
		return err;

	if (!enabled)
		err = tegra_pwm_enable(chip, pwm);

	return err;
}

static const struct pwm_ops tegra_pwm_ops = {
	.apply = tegra_pwm_apply,
	.owner = THIS_MODULE,
};

static int tegra_pwm_probe(struct platform_device *pdev)
{
	struct tegra_pwm_chip *pc;
	int ret;

	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	pc->soc = of_device_get_match_data(&pdev->dev);
	pc->dev = &pdev->dev;

	pc->regs = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pc->regs))
		return PTR_ERR(pc->regs);

	platform_set_drvdata(pdev, pc);

	pc->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pc->clk))
		return PTR_ERR(pc->clk);

	ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
	if (ret)
		return ret;

	pm_runtime_enable(&pdev->dev);
	ret = pm_runtime_resume_and_get(&pdev->dev);
	if (ret)
		return ret;

	/* Set maximum frequency of the IP */
	ret = dev_pm_opp_set_rate(pc->dev, pc->soc->max_frequency);
	if (ret < 0) {
		dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
		goto put_pm;
	}

	/*
	 * The requested and configured frequency may differ due to
	 * clock register resolutions. Get the configured frequency
	 * so that PWM period can be calculated more accurately.
	 */
	pc->clk_rate = clk_get_rate(pc->clk);

	/* Set minimum limit of PWM period for the IP */
	pc->min_period_ns =
	    (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;

	pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
	if (IS_ERR(pc->rst)) {
		ret = PTR_ERR(pc->rst);
		dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
		goto put_pm;
	}

	reset_control_deassert(pc->rst);

	pc->chip.dev = &pdev->dev;
	pc->chip.ops = &tegra_pwm_ops;
	pc->chip.npwm = pc->soc->num_channels;

	ret = pwmchip_add(&pc->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		reset_control_assert(pc->rst);
		goto put_pm;
	}

	pm_runtime_put(&pdev->dev);

	return 0;
put_pm:
	pm_runtime_put_sync_suspend(&pdev->dev);
	pm_runtime_force_suspend(&pdev->dev);
	return ret;
}

static void tegra_pwm_remove(struct platform_device *pdev)
{
	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);

	pwmchip_remove(&pc->chip);

	reset_control_assert(pc->rst);

	pm_runtime_force_suspend(&pdev->dev);
}

static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev)
{
	struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
	int err;

	clk_disable_unprepare(pc->clk);

	err = pinctrl_pm_select_sleep_state(dev);
	if (err) {
		clk_prepare_enable(pc->clk);
		return err;
	}

	return 0;
}

static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)
{
	struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
	int err;

	err = pinctrl_pm_select_default_state(dev);
	if (err)
		return err;

	err = clk_prepare_enable(pc->clk);
	if (err) {
		pinctrl_pm_select_sleep_state(dev);
		return err;
	}

	return 0;
}

static const struct tegra_pwm_soc tegra20_pwm_soc = {
	.num_channels = 4,
	.max_frequency = 48000000UL,
};

static const struct tegra_pwm_soc tegra186_pwm_soc = {
	.num_channels = 1,
	.max_frequency = 102000000UL,
};

static const struct tegra_pwm_soc tegra194_pwm_soc = {
	.num_channels = 1,
	.max_frequency = 408000000UL,
};

static const struct of_device_id tegra_pwm_of_match[] = {
	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
	{ }
};
MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);

static const struct dev_pm_ops tegra_pwm_pm_ops = {
	SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume,
			   NULL)
	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
				pm_runtime_force_resume)
};

static struct platform_driver tegra_pwm_driver = {
	.driver = {
		.name = "tegra-pwm",
		.of_match_table = tegra_pwm_of_match,
		.pm = &tegra_pwm_pm_ops,
	},
	.probe = tegra_pwm_probe,
	.remove_new = tegra_pwm_remove,
};

module_platform_driver(tegra_pwm_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
MODULE_DESCRIPTION("Tegra PWM controller driver");
MODULE_ALIAS("platform:tegra-pwm");
Commit	Line	Data
16216333	1	// SPDX-License-Identifier: GPL-2.0-or-later
0134b932 TR	2	/*
	3	* drivers/pwm/pwm-tegra.c
	4	*
	5	* Tegra pulse-width-modulation controller driver
	6	*
1d7796bd	7	* Copyright (c) 2010-2020, NVIDIA Corporation.
0134b932	8	* Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
1d7796bd SP	9	*
	10	* Overview of Tegra Pulse Width Modulator Register:
	11	* 1. 13-bit: Frequency division (SCALE)
	12	* 2. 8-bit : Pulse division (DUTY)
	13	* 3. 1-bit : Enable bit
	14	*
	15	* The PWM clock frequency is divided by 256 before subdividing it based
	16	* on the programmable frequency division value to generate the required
	17	* frequency for PWM output. The maximum output frequency that can be
	18	* achieved is (max rate of source clock) / 256.
	19	* e.g. if source clock rate is 408 MHz, maximum output frequency can be:
	20	* 408 MHz/256 = 1.6 MHz.
	21	* This 1.6 MHz frequency can further be divided using SCALE value in PWM.
	22	*
	23	* PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
	24	* To achieve 100% duty cycle, program Bit [24] of this register to
	25	* 1’b1. In which case the other bits [23:16] are set to don't care.
	26	*
	27	* Limitations:
	28	* - When PWM is disabled, the output is driven to inactive.
	29	* - It does not allow the current PWM period to complete and
	30	* stops abruptly.
	31	*
	32	* - If the register is reconfigured while PWM is running,
	33	* it does not complete the currently running period.
	34	*
	35	* - If the user input duty is beyond acceptible limits,
	36	* -EINVAL is returned.
0134b932 TR	37	*/
	38
	39	#include <linux/clk.h>
	40	#include <linux/err.h>
	41	#include <linux/io.h>
	42	#include <linux/module.h>
	43	#include <linux/of.h>
e9be88a2	44	#include <linux/of_device.h>
3da9b0fe	45	#include <linux/pm_opp.h>
0134b932 TR	46	#include <linux/pwm.h>
0134b932 TR	47	#include <linux/platform_device.h>
4a813b26	48	#include <linux/pinctrl/consumer.h>
3da9b0fe	49	#include <linux/pm_runtime.h>
0134b932	50	#include <linux/slab.h>
5dfbd2bd	51	#include <linux/reset.h>
0134b932	52
3da9b0fe DO	53	#include <soc/tegra/common.h>
3da9b0fe DO	54
0134b932 TR	55	#define PWM_ENABLE (1 << 31)
	56	#define PWM_DUTY_WIDTH 8
	57	#define PWM_DUTY_SHIFT 16
	58	#define PWM_SCALE_WIDTH 13
	59	#define PWM_SCALE_SHIFT 0
	60
e9be88a2 LD	61	struct tegra_pwm_soc {
e9be88a2 LD	62	unsigned int num_channels;
0527eb37 LD	63
	64	/* Maximum IP frequency for given SoCs */
	65	unsigned long max_frequency;
e9be88a2 LD	66	};
e9be88a2 LD	67
0134b932	68	struct tegra_pwm_chip {
e17c0b22 TR	69	struct pwm_chip chip;
e17c0b22 TR	70	struct device *dev;
0134b932	71
e17c0b22	72	struct clk *clk;
5dfbd2bd	73	struct reset_control*rst;
0134b932	74
46fa8bc0	75	unsigned long clk_rate;
1d7796bd	76	unsigned long min_period_ns;
46fa8bc0	77
4f57f5a0	78	void __iomem *regs;
e9be88a2 LD	79
e9be88a2 LD	80	const struct tegra_pwm_soc *soc;
0134b932 TR	81	};
	82
	83	static inline struct tegra_pwm_chip to_tegra_pwm_chip(struct pwm_chip chip)
	84	{
	85	return container_of(chip, struct tegra_pwm_chip, chip);
	86	}
	87
f19460c1	88	static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset)
0134b932	89	{
f19460c1	90	return readl(pc->regs + (offset << 4));
0134b932 TR	91	}
0134b932 TR	92
f19460c1	93	static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offset, u32 value)
0134b932	94	{
f19460c1	95	writel(value, pc->regs + (offset << 4));
0134b932 TR	96	}
	97
	98	static int tegra_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	99	int duty_ns, int period_ns)
	100	{
	101	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
8c193f47	102	unsigned long long c = duty_ns;
1d7796bd	103	unsigned long rate, required_clk_rate;
0134b932 TR	104	u32 val = 0;
	105	int err;
	106
	107	/*
	108	* Convert from duty_ns / period_ns to a fixed number of duty ticks
	109	* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
	110	* nearest integer during division.
	111	*/
b979ed53	112	c *= (1 << PWM_DUTY_WIDTH);
90241fb9	113	c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
0134b932 TR	114
	115	val = (u32)c << PWM_DUTY_SHIFT;
	116
1d7796bd SP	117	/*
	118	* min period = max clock limit >> PWM_DUTY_WIDTH
	119	*/
	120	if (period_ns < pc->min_period_ns)
	121	return -EINVAL;
	122
0134b932 TR	123	/*
	124	* Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
	125	* cycles at the PWM clock rate will take period_ns nanoseconds.
1d7796bd SP	126	*
	127	* num_channels: If single instance of PWM controller has multiple
	128	* channels (e.g. Tegra210 or older) then it is not possible to
	129	* configure separate clock rates to each of the channels, in such
	130	* case the value stored during probe will be referred.
	131	*
	132	* If every PWM controller instance has one channel respectively, i.e.
	133	* nums_channels == 1 then only the clock rate can be modified
	134	* dynamically (e.g. Tegra186 or Tegra194).
0134b932	135	*/
1d7796bd SP	136	if (pc->soc->num_channels == 1) {
	137	/*
	138	* Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
	139	* with the maximum possible rate that the controller can
	140	* provide. Any further lower value can be derived by setting
	141	* PFM bits[0:12].
	142	*
	143	* required_clk_rate is a reference rate for source clock and
	144	* it is derived based on user requested period. By setting the
	145	* source clock rate as required_clk_rate, PWM controller will
	146	* be able to configure the requested period.
	147	*/
dd1f1da4	148	required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
f2719461	149	period_ns);
1d7796bd	150
5eccd0d9 JH	151	if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
	152	/*
	153	* required_clk_rate is a lower bound for the input
	154	* rate; for lower rates there is no value for PWM_SCALE
	155	* that yields a period less than or equal to the
	156	* requested period. Hence, for lower rates, double the
	157	* required_clk_rate to get a clock rate that can meet
	158	* the requested period.
	159	*/
	160	required_clk_rate *= 2;
	161
3da9b0fe	162	err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);
1d7796bd SP	163	if (err < 0)
	164	return -EINVAL;
	165
	166	/* Store the new rate for further references */
	167	pc->clk_rate = clk_get_rate(pc->clk);
	168	}
	169
250b76f4	170	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
8c193f47 UKK	171	rate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,
8c193f47 UKK	172	(u64)NSEC_PER_SEC << PWM_DUTY_WIDTH);
0134b932 TR	173
	174	/*
	175	* Since the actual PWM divider is the register's frequency divider
1d7796bd	176	* field plus 1, we need to decrement to get the correct value to
0134b932 TR	177	* write to the register.
	178	*/
	179	if (rate > 0)
	180	rate--;
8c193f47 UKK	181	else
8c193f47 UKK	182	return -EINVAL;
0134b932 TR	183
	184	/*
	185	* Make sure that the rate will fit in the register's frequency
	186	* divider field.
	187	*/
	188	if (rate >> PWM_SCALE_WIDTH)
	189	return -EINVAL;
	190
	191	val \|= rate << PWM_SCALE_SHIFT;
	192
	193	/*
	194	* If the PWM channel is disabled, make sure to turn on the clock
	195	* before writing the register. Otherwise, keep it enabled.
	196	*/
5c31252c	197	if (!pwm_is_enabled(pwm)) {
3da9b0fe DO	198	err = pm_runtime_resume_and_get(pc->dev);
3da9b0fe DO	199	if (err)
0134b932 TR	200	return err;
	201	} else
	202	val \|= PWM_ENABLE;
	203
	204	pwm_writel(pc, pwm->hwpwm, val);
	205
	206	/*
	207	* If the PWM is not enabled, turn the clock off again to save power.
	208	*/
5c31252c	209	if (!pwm_is_enabled(pwm))
3da9b0fe	210	pm_runtime_put(pc->dev);
0134b932 TR	211
	212	return 0;
	213	}
	214
	215	static int tegra_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	216	{
	217	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	218	int rc = 0;
	219	u32 val;
	220
3da9b0fe DO	221	rc = pm_runtime_resume_and_get(pc->dev);
3da9b0fe DO	222	if (rc)
0134b932 TR	223	return rc;
	224
	225	val = pwm_readl(pc, pwm->hwpwm);
	226	val \|= PWM_ENABLE;
	227	pwm_writel(pc, pwm->hwpwm, val);
	228
	229	return 0;
	230	}
	231
	232	static void tegra_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	233	{
	234	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
	235	u32 val;
	236
	237	val = pwm_readl(pc, pwm->hwpwm);
	238	val &= ~PWM_ENABLE;
	239	pwm_writel(pc, pwm->hwpwm, val);
	240
3da9b0fe	241	pm_runtime_put_sync(pc->dev);
0134b932 TR	242	}
0134b932 TR	243
fd3ddd43 UKK	244	static int tegra_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	245	const struct pwm_state *state)
	246	{
	247	int err;
	248	bool enabled = pwm->state.enabled;
	249
	250	if (state->polarity != PWM_POLARITY_NORMAL)
	251	return -EINVAL;
	252
	253	if (!state->enabled) {
	254	if (enabled)
	255	tegra_pwm_disable(chip, pwm);
	256
	257	return 0;
	258	}
	259
	260	err = tegra_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
	261	if (err)
	262	return err;
	263
	264	if (!enabled)
	265	err = tegra_pwm_enable(chip, pwm);
	266
	267	return err;
	268	}
	269
0134b932	270	static const struct pwm_ops tegra_pwm_ops = {
fd3ddd43	271	.apply = tegra_pwm_apply,
0134b932 TR	272	.owner = THIS_MODULE,
	273	};
	274
	275	static int tegra_pwm_probe(struct platform_device *pdev)
	276	{
f19460c1	277	struct tegra_pwm_chip *pc;
0134b932 TR	278	int ret;
0134b932 TR	279
f19460c1 UKK	280	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
f19460c1 UKK	281	if (!pc)
0134b932	282	return -ENOMEM;
0134b932	283
f19460c1 UKK	284	pc->soc = of_device_get_match_data(&pdev->dev);
f19460c1 UKK	285	pc->dev = &pdev->dev;
0134b932	286
f19460c1 UKK	287	pc->regs = devm_platform_ioremap_resource(pdev, 0);
	288	if (IS_ERR(pc->regs))
	289	return PTR_ERR(pc->regs);
0134b932	290
f19460c1	291	platform_set_drvdata(pdev, pc);
0134b932	292
f19460c1 UKK	293	pc->clk = devm_clk_get(&pdev->dev, NULL);
	294	if (IS_ERR(pc->clk))
	295	return PTR_ERR(pc->clk);
0134b932	296
3da9b0fe DO	297	ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
	298	if (ret)
	299	return ret;
	300
	301	pm_runtime_enable(&pdev->dev);
	302	ret = pm_runtime_resume_and_get(&pdev->dev);
	303	if (ret)
	304	return ret;
	305
0527eb37	306	/* Set maximum frequency of the IP */
f19460c1	307	ret = dev_pm_opp_set_rate(pc->dev, pc->soc->max_frequency);
0527eb37 LD	308	if (ret < 0) {
0527eb37 LD	309	dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
3da9b0fe	310	goto put_pm;
0527eb37 LD	311	}
	312
	313	/*
	314	* The requested and configured frequency may differ due to
	315	* clock register resolutions. Get the configured frequency
	316	* so that PWM period can be calculated more accurately.
	317	*/
f19460c1	318	pc->clk_rate = clk_get_rate(pc->clk);
46fa8bc0	319
1d7796bd	320	/* Set minimum limit of PWM period for the IP */
f19460c1 UKK	321	pc->min_period_ns =
f19460c1 UKK	322	(NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
1d7796bd	323
f19460c1 UKK	324	pc->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
	325	if (IS_ERR(pc->rst)) {
	326	ret = PTR_ERR(pc->rst);
5dfbd2bd	327	dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
3da9b0fe	328	goto put_pm;
5dfbd2bd RS	329	}
5dfbd2bd RS	330
f19460c1	331	reset_control_deassert(pc->rst);
5dfbd2bd	332
f19460c1 UKK	333	pc->chip.dev = &pdev->dev;
	334	pc->chip.ops = &tegra_pwm_ops;
	335	pc->chip.npwm = pc->soc->num_channels;
0134b932	336
f19460c1	337	ret = pwmchip_add(&pc->chip);
0134b932 TR	338	if (ret < 0) {
0134b932 TR	339	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
f19460c1	340	reset_control_assert(pc->rst);
3da9b0fe	341	goto put_pm;
0134b932 TR	342	}
0134b932 TR	343
3da9b0fe DO	344	pm_runtime_put(&pdev->dev);
3da9b0fe DO	345
0134b932	346	return 0;
3da9b0fe DO	347	put_pm:
	348	pm_runtime_put_sync_suspend(&pdev->dev);
	349	pm_runtime_force_suspend(&pdev->dev);
	350	return ret;
0134b932 TR	351	}
0134b932 TR	352
e39cb6f9	353	static void tegra_pwm_remove(struct platform_device *pdev)
0134b932 TR	354	{
0134b932 TR	355	struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
5dfbd2bd	356
2f1a3bd4 UKK	357	pwmchip_remove(&pc->chip);
2f1a3bd4 UKK	358
5dfbd2bd	359	reset_control_assert(pc->rst);
5dfbd2bd	360
3da9b0fe	361	pm_runtime_force_suspend(&pdev->dev);
0134b932 TR	362	}
0134b932 TR	363
3da9b0fe	364	static int __maybe_unused tegra_pwm_runtime_suspend(struct device *dev)
4a813b26	365	{
3da9b0fe DO	366	struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
	367	int err;
	368
	369	clk_disable_unprepare(pc->clk);
	370
	371	err = pinctrl_pm_select_sleep_state(dev);
	372	if (err) {
	373	clk_prepare_enable(pc->clk);
	374	return err;
	375	}
	376
	377	return 0;
4a813b26 LD	378	}
4a813b26 LD	379
3da9b0fe	380	static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)
4a813b26	381	{
3da9b0fe DO	382	struct tegra_pwm_chip *pc = dev_get_drvdata(dev);
	383	int err;
	384
	385	err = pinctrl_pm_select_default_state(dev);
	386	if (err)
	387	return err;
	388
	389	err = clk_prepare_enable(pc->clk);
	390	if (err) {
	391	pinctrl_pm_select_sleep_state(dev);
	392	return err;
	393	}
	394
	395	return 0;
4a813b26	396	}
4a813b26	397
e9be88a2 LD	398	static const struct tegra_pwm_soc tegra20_pwm_soc = {
e9be88a2 LD	399	.num_channels = 4,
0527eb37	400	.max_frequency = 48000000UL,
e9be88a2 LD	401	};
	402
	403	static const struct tegra_pwm_soc tegra186_pwm_soc = {
	404	.num_channels = 1,
0527eb37	405	.max_frequency = 102000000UL,
e9be88a2 LD	406	};
e9be88a2 LD	407
2d0c08fc SP	408	static const struct tegra_pwm_soc tegra194_pwm_soc = {
	409	.num_channels = 1,
	410	.max_frequency = 408000000UL,
	411	};
	412
f1a8870a	413	static const struct of_device_id tegra_pwm_of_match[] = {
e9be88a2 LD	414	{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
e9be88a2 LD	415	{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
2d0c08fc	416	{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
140fd977 TR	417	{ }
140fd977 TR	418	};
140fd977	419	MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
140fd977	420
4a813b26	421	static const struct dev_pm_ops tegra_pwm_pm_ops = {
3da9b0fe DO	422	SET_RUNTIME_PM_OPS(tegra_pwm_runtime_suspend, tegra_pwm_runtime_resume,
	423	NULL)
	424	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
	425	pm_runtime_force_resume)
4a813b26 LD	426	};
4a813b26 LD	427
0134b932 TR	428	static struct platform_driver tegra_pwm_driver = {
	429	.driver = {
	430	.name = "tegra-pwm",
838bf09d	431	.of_match_table = tegra_pwm_of_match,
4a813b26	432	.pm = &tegra_pwm_pm_ops,
0134b932 TR	433	},
0134b932 TR	434	.probe = tegra_pwm_probe,
e39cb6f9	435	.remove_new = tegra_pwm_remove,
0134b932 TR	436	};
	437
	438	module_platform_driver(tegra_pwm_driver);
	439
	440	MODULE_LICENSE("GPL");
1d7796bd SP	441	MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
1d7796bd SP	442	MODULE_DESCRIPTION("Tegra PWM controller driver");
0134b932	443	MODULE_ALIAS("platform:tegra-pwm");