Commit | Line | Data |
---|---|---|
f50a7f3d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
09853ce7 AB |
2 | /* |
3 | * Driver for Allwinner sun4i Pulse Width Modulation Controller | |
4 | * | |
5 | * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> | |
9f28e95b JS |
6 | * |
7 | * Limitations: | |
8 | * - When outputing the source clock directly, the PWM logic will be bypassed | |
9 | * and the currently running period is not guaranteed to be completed | |
09853ce7 AB |
10 | */ |
11 | ||
12 | #include <linux/bitops.h> | |
13 | #include <linux/clk.h> | |
c32c5c50 | 14 | #include <linux/delay.h> |
09853ce7 AB |
15 | #include <linux/err.h> |
16 | #include <linux/io.h> | |
c32c5c50 | 17 | #include <linux/jiffies.h> |
09853ce7 AB |
18 | #include <linux/module.h> |
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/pwm.h> | |
a7fe9856 | 23 | #include <linux/reset.h> |
09853ce7 AB |
24 | #include <linux/slab.h> |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/time.h> | |
27 | ||
28 | #define PWM_CTRL_REG 0x0 | |
29 | ||
30 | #define PWM_CH_PRD_BASE 0x4 | |
31 | #define PWM_CH_PRD_OFFSET 0x4 | |
32 | #define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch)) | |
33 | ||
34 | #define PWMCH_OFFSET 15 | |
35 | #define PWM_PRESCAL_MASK GENMASK(3, 0) | |
36 | #define PWM_PRESCAL_OFF 0 | |
37 | #define PWM_EN BIT(4) | |
38 | #define PWM_ACT_STATE BIT(5) | |
39 | #define PWM_CLK_GATING BIT(6) | |
40 | #define PWM_MODE BIT(7) | |
41 | #define PWM_PULSE BIT(8) | |
42 | #define PWM_BYPASS BIT(9) | |
43 | ||
44 | #define PWM_RDY_BASE 28 | |
45 | #define PWM_RDY_OFFSET 1 | |
46 | #define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch)) | |
47 | ||
48 | #define PWM_PRD(prd) (((prd) - 1) << 16) | |
49 | #define PWM_PRD_MASK GENMASK(15, 0) | |
50 | ||
51 | #define PWM_DTY_MASK GENMASK(15, 0) | |
52 | ||
93e0dfb2 AB |
53 | #define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1) |
54 | #define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK) | |
55 | #define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK) | |
56 | ||
09853ce7 AB |
57 | #define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET)) |
58 | ||
59 | static const u32 prescaler_table[] = { | |
60 | 120, | |
61 | 180, | |
62 | 240, | |
63 | 360, | |
64 | 480, | |
65 | 0, | |
66 | 0, | |
67 | 0, | |
68 | 12000, | |
69 | 24000, | |
70 | 36000, | |
71 | 48000, | |
72 | 72000, | |
73 | 0, | |
74 | 0, | |
75 | 0, /* Actually 1 but tested separately */ | |
76 | }; | |
77 | ||
78 | struct sun4i_pwm_data { | |
79 | bool has_prescaler_bypass; | |
9f28e95b | 80 | bool has_direct_mod_clk_output; |
f6649f7a | 81 | unsigned int npwm; |
09853ce7 AB |
82 | }; |
83 | ||
84 | struct sun4i_pwm_chip { | |
85 | struct pwm_chip chip; | |
5b090b43 | 86 | struct clk *bus_clk; |
09853ce7 | 87 | struct clk *clk; |
a7fe9856 | 88 | struct reset_control *rst; |
09853ce7 AB |
89 | void __iomem *base; |
90 | spinlock_t ctrl_lock; | |
91 | const struct sun4i_pwm_data *data; | |
c32c5c50 | 92 | unsigned long next_period[2]; |
09853ce7 AB |
93 | }; |
94 | ||
95 | static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip) | |
96 | { | |
97 | return container_of(chip, struct sun4i_pwm_chip, chip); | |
98 | } | |
99 | ||
100 | static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip, | |
101 | unsigned long offset) | |
102 | { | |
103 | return readl(chip->base + offset); | |
104 | } | |
105 | ||
106 | static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip, | |
107 | u32 val, unsigned long offset) | |
108 | { | |
109 | writel(val, chip->base + offset); | |
110 | } | |
111 | ||
93e0dfb2 AB |
112 | static void sun4i_pwm_get_state(struct pwm_chip *chip, |
113 | struct pwm_device *pwm, | |
114 | struct pwm_state *state) | |
115 | { | |
116 | struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); | |
117 | u64 clk_rate, tmp; | |
118 | u32 val; | |
119 | unsigned int prescaler; | |
120 | ||
121 | clk_rate = clk_get_rate(sun4i_pwm->clk); | |
122 | ||
123 | val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); | |
124 | ||
9f28e95b JS |
125 | /* |
126 | * PWM chapter in H6 manual has a diagram which explains that if bypass | |
127 | * bit is set, no other setting has any meaning. Even more, experiment | |
128 | * proved that also enable bit is ignored in this case. | |
129 | */ | |
130 | if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && | |
131 | sun4i_pwm->data->has_direct_mod_clk_output) { | |
132 | state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); | |
133 | state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); | |
134 | state->polarity = PWM_POLARITY_NORMAL; | |
135 | state->enabled = true; | |
136 | return; | |
137 | } | |
138 | ||
989ae7a5 AB |
139 | if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && |
140 | sun4i_pwm->data->has_prescaler_bypass) | |
93e0dfb2 AB |
141 | prescaler = 1; |
142 | else | |
143 | prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; | |
144 | ||
145 | if (prescaler == 0) | |
146 | return; | |
147 | ||
148 | if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) | |
149 | state->polarity = PWM_POLARITY_NORMAL; | |
150 | else | |
151 | state->polarity = PWM_POLARITY_INVERSED; | |
152 | ||
989ae7a5 AB |
153 | if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) == |
154 | BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) | |
93e0dfb2 AB |
155 | state->enabled = true; |
156 | else | |
157 | state->enabled = false; | |
158 | ||
159 | val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); | |
160 | ||
50cc7e3e | 161 | tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val); |
93e0dfb2 AB |
162 | state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); |
163 | ||
50cc7e3e | 164 | tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val); |
93e0dfb2 AB |
165 | state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); |
166 | } | |
167 | ||
c32c5c50 | 168 | static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm, |
71523d18 | 169 | const struct pwm_state *state, |
9f28e95b JS |
170 | u32 *dty, u32 *prd, unsigned int *prsclr, |
171 | bool *bypass) | |
c32c5c50 AB |
172 | { |
173 | u64 clk_rate, div = 0; | |
f6003f94 | 174 | unsigned int prescaler = 0; |
c32c5c50 AB |
175 | |
176 | clk_rate = clk_get_rate(sun4i_pwm->clk); | |
177 | ||
9f28e95b JS |
178 | *bypass = sun4i_pwm->data->has_direct_mod_clk_output && |
179 | state->enabled && | |
180 | (state->period * clk_rate >= NSEC_PER_SEC) && | |
181 | (state->period * clk_rate < 2 * NSEC_PER_SEC) && | |
182 | (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); | |
183 | ||
184 | /* Skip calculation of other parameters if we bypass them */ | |
185 | if (*bypass) | |
186 | return 0; | |
187 | ||
c32c5c50 AB |
188 | if (sun4i_pwm->data->has_prescaler_bypass) { |
189 | /* First, test without any prescaler when available */ | |
190 | prescaler = PWM_PRESCAL_MASK; | |
c32c5c50 AB |
191 | /* |
192 | * When not using any prescaler, the clock period in nanoseconds | |
193 | * is not an integer so round it half up instead of | |
194 | * truncating to get less surprising values. | |
195 | */ | |
196 | div = clk_rate * state->period + NSEC_PER_SEC / 2; | |
197 | do_div(div, NSEC_PER_SEC); | |
198 | if (div - 1 > PWM_PRD_MASK) | |
199 | prescaler = 0; | |
200 | } | |
201 | ||
202 | if (prescaler == 0) { | |
203 | /* Go up from the first divider */ | |
204 | for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) { | |
f6003f94 UKK |
205 | unsigned int pval = prescaler_table[prescaler]; |
206 | ||
207 | if (!pval) | |
c32c5c50 | 208 | continue; |
f6003f94 | 209 | |
c32c5c50 AB |
210 | div = clk_rate; |
211 | do_div(div, pval); | |
212 | div = div * state->period; | |
213 | do_div(div, NSEC_PER_SEC); | |
214 | if (div - 1 <= PWM_PRD_MASK) | |
215 | break; | |
216 | } | |
217 | ||
218 | if (div - 1 > PWM_PRD_MASK) | |
219 | return -EINVAL; | |
220 | } | |
221 | ||
222 | *prd = div; | |
223 | div *= state->duty_cycle; | |
224 | do_div(div, state->period); | |
225 | *dty = div; | |
226 | *prsclr = prescaler; | |
227 | ||
c32c5c50 AB |
228 | return 0; |
229 | } | |
230 | ||
231 | static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, | |
71523d18 | 232 | const struct pwm_state *state) |
c32c5c50 AB |
233 | { |
234 | struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); | |
235 | struct pwm_state cstate; | |
413c2a11 | 236 | u32 ctrl, duty = 0, period = 0, val; |
c32c5c50 | 237 | int ret; |
413c2a11 | 238 | unsigned int delay_us, prescaler = 0; |
c32c5c50 | 239 | unsigned long now; |
9f28e95b | 240 | bool bypass; |
c32c5c50 AB |
241 | |
242 | pwm_get_state(pwm, &cstate); | |
243 | ||
244 | if (!cstate.enabled) { | |
245 | ret = clk_prepare_enable(sun4i_pwm->clk); | |
246 | if (ret) { | |
247 | dev_err(chip->dev, "failed to enable PWM clock\n"); | |
248 | return ret; | |
249 | } | |
250 | } | |
251 | ||
9f28e95b JS |
252 | ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler, |
253 | &bypass); | |
fa4d8178 CP |
254 | if (ret) { |
255 | dev_err(chip->dev, "period exceeds the maximum value\n"); | |
fa4d8178 CP |
256 | if (!cstate.enabled) |
257 | clk_disable_unprepare(sun4i_pwm->clk); | |
258 | return ret; | |
259 | } | |
c32c5c50 | 260 | |
3e954d96 CP |
261 | spin_lock(&sun4i_pwm->ctrl_lock); |
262 | ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); | |
263 | ||
9f28e95b JS |
264 | if (sun4i_pwm->data->has_direct_mod_clk_output) { |
265 | if (bypass) { | |
266 | ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); | |
267 | /* We can skip other parameter */ | |
268 | sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); | |
269 | spin_unlock(&sun4i_pwm->ctrl_lock); | |
270 | return 0; | |
271 | } | |
272 | ||
273 | ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); | |
274 | } | |
275 | ||
fa4d8178 CP |
276 | if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { |
277 | /* Prescaler changed, the clock has to be gated */ | |
278 | ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); | |
279 | sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); | |
c32c5c50 | 280 | |
fa4d8178 CP |
281 | ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); |
282 | ctrl |= BIT_CH(prescaler, pwm->hwpwm); | |
c32c5c50 AB |
283 | } |
284 | ||
fa4d8178 CP |
285 | val = (duty & PWM_DTY_MASK) | PWM_PRD(period); |
286 | sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); | |
287 | sun4i_pwm->next_period[pwm->hwpwm] = jiffies + | |
c7dcccae | 288 | nsecs_to_jiffies(cstate.period + 1000); |
fa4d8178 | 289 | |
c32c5c50 AB |
290 | if (state->polarity != PWM_POLARITY_NORMAL) |
291 | ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); | |
292 | else | |
293 | ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); | |
294 | ||
295 | ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); | |
fa4d8178 | 296 | |
6eefb79d | 297 | if (state->enabled) |
c32c5c50 | 298 | ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); |
c32c5c50 AB |
299 | |
300 | sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); | |
301 | ||
302 | spin_unlock(&sun4i_pwm->ctrl_lock); | |
303 | ||
304 | if (state->enabled) | |
305 | return 0; | |
306 | ||
c32c5c50 AB |
307 | /* We need a full period to elapse before disabling the channel. */ |
308 | now = jiffies; | |
d3817a64 | 309 | if (time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) { |
c32c5c50 AB |
310 | delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] - |
311 | now); | |
312 | if ((delay_us / 500) > MAX_UDELAY_MS) | |
313 | msleep(delay_us / 1000 + 1); | |
314 | else | |
315 | usleep_range(delay_us, delay_us * 2); | |
316 | } | |
c32c5c50 AB |
317 | |
318 | spin_lock(&sun4i_pwm->ctrl_lock); | |
319 | ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); | |
320 | ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); | |
321 | ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm); | |
322 | sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); | |
323 | spin_unlock(&sun4i_pwm->ctrl_lock); | |
324 | ||
325 | clk_disable_unprepare(sun4i_pwm->clk); | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
09853ce7 | 330 | static const struct pwm_ops sun4i_pwm_ops = { |
c32c5c50 | 331 | .apply = sun4i_pwm_apply, |
93e0dfb2 | 332 | .get_state = sun4i_pwm_get_state, |
09853ce7 AB |
333 | .owner = THIS_MODULE, |
334 | }; | |
335 | ||
7b4c7c56 | 336 | static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = { |
09853ce7 | 337 | .has_prescaler_bypass = false, |
f6649f7a HG |
338 | .npwm = 2, |
339 | }; | |
340 | ||
7b4c7c56 | 341 | static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = { |
f6649f7a | 342 | .has_prescaler_bypass = true, |
f6649f7a HG |
343 | .npwm = 2, |
344 | }; | |
345 | ||
7b4c7c56 | 346 | static const struct sun4i_pwm_data sun4i_pwm_single_bypass = { |
42ddcf4f | 347 | .has_prescaler_bypass = true, |
42ddcf4f MK |
348 | .npwm = 1, |
349 | }; | |
350 | ||
856c45d8 PV |
351 | static const struct sun4i_pwm_data sun50i_a64_pwm_data = { |
352 | .has_prescaler_bypass = true, | |
353 | .has_direct_mod_clk_output = true, | |
354 | .npwm = 1, | |
355 | }; | |
356 | ||
fdd2c12e JS |
357 | static const struct sun4i_pwm_data sun50i_h6_pwm_data = { |
358 | .has_prescaler_bypass = true, | |
359 | .has_direct_mod_clk_output = true, | |
360 | .npwm = 2, | |
361 | }; | |
362 | ||
09853ce7 AB |
363 | static const struct of_device_id sun4i_pwm_dt_ids[] = { |
364 | { | |
365 | .compatible = "allwinner,sun4i-a10-pwm", | |
7b4c7c56 | 366 | .data = &sun4i_pwm_dual_nobypass, |
f6649f7a HG |
367 | }, { |
368 | .compatible = "allwinner,sun5i-a10s-pwm", | |
7b4c7c56 | 369 | .data = &sun4i_pwm_dual_bypass, |
f6649f7a HG |
370 | }, { |
371 | .compatible = "allwinner,sun5i-a13-pwm", | |
7b4c7c56 | 372 | .data = &sun4i_pwm_single_bypass, |
09853ce7 AB |
373 | }, { |
374 | .compatible = "allwinner,sun7i-a20-pwm", | |
7b4c7c56 | 375 | .data = &sun4i_pwm_dual_bypass, |
42ddcf4f MK |
376 | }, { |
377 | .compatible = "allwinner,sun8i-h3-pwm", | |
7b4c7c56 | 378 | .data = &sun4i_pwm_single_bypass, |
856c45d8 PV |
379 | }, { |
380 | .compatible = "allwinner,sun50i-a64-pwm", | |
381 | .data = &sun50i_a64_pwm_data, | |
fdd2c12e JS |
382 | }, { |
383 | .compatible = "allwinner,sun50i-h6-pwm", | |
384 | .data = &sun50i_h6_pwm_data, | |
09853ce7 AB |
385 | }, { |
386 | /* sentinel */ | |
387 | }, | |
388 | }; | |
389 | MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids); | |
390 | ||
391 | static int sun4i_pwm_probe(struct platform_device *pdev) | |
392 | { | |
393 | struct sun4i_pwm_chip *pwm; | |
93e0dfb2 | 394 | int ret; |
09853ce7 AB |
395 | |
396 | pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); | |
397 | if (!pwm) | |
398 | return -ENOMEM; | |
399 | ||
df4f6e8c CL |
400 | pwm->data = of_device_get_match_data(&pdev->dev); |
401 | if (!pwm->data) | |
402 | return -ENODEV; | |
403 | ||
2e379ffb | 404 | pwm->base = devm_platform_ioremap_resource(pdev, 0); |
09853ce7 AB |
405 | if (IS_ERR(pwm->base)) |
406 | return PTR_ERR(pwm->base); | |
407 | ||
b8d74644 CP |
408 | /* |
409 | * All hardware variants need a source clock that is divided and | |
410 | * then feeds the counter that defines the output wave form. In the | |
411 | * device tree this clock is either unnamed or called "mod". | |
412 | * Some variants (e.g. H6) need another clock to access the | |
413 | * hardware registers; this is called "bus". | |
414 | * So we request "mod" first (and ignore the corner case that a | |
415 | * parent provides a "mod" clock while the right one would be the | |
416 | * unnamed one of the PWM device) and if this is not found we fall | |
417 | * back to the first clock of the PWM. | |
418 | */ | |
419 | pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); | |
5327f34b KK |
420 | if (IS_ERR(pwm->clk)) |
421 | return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk), | |
422 | "get mod clock failed\n"); | |
b8d74644 CP |
423 | |
424 | if (!pwm->clk) { | |
425 | pwm->clk = devm_clk_get(&pdev->dev, NULL); | |
5327f34b KK |
426 | if (IS_ERR(pwm->clk)) |
427 | return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk), | |
428 | "get unnamed clock failed\n"); | |
b8d74644 | 429 | } |
09853ce7 | 430 | |
5b090b43 | 431 | pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); |
5327f34b KK |
432 | if (IS_ERR(pwm->bus_clk)) |
433 | return dev_err_probe(&pdev->dev, PTR_ERR(pwm->bus_clk), | |
434 | "get bus clock failed\n"); | |
5b090b43 | 435 | |
a7fe9856 | 436 | pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); |
5327f34b KK |
437 | if (IS_ERR(pwm->rst)) |
438 | return dev_err_probe(&pdev->dev, PTR_ERR(pwm->rst), | |
439 | "get reset failed\n"); | |
a7fe9856 JS |
440 | |
441 | /* Deassert reset */ | |
442 | ret = reset_control_deassert(pwm->rst); | |
443 | if (ret) { | |
444 | dev_err(&pdev->dev, "cannot deassert reset control: %pe\n", | |
445 | ERR_PTR(ret)); | |
446 | return ret; | |
447 | } | |
448 | ||
5b090b43 JS |
449 | /* |
450 | * We're keeping the bus clock on for the sake of simplicity. | |
451 | * Actually it only needs to be on for hardware register accesses. | |
452 | */ | |
453 | ret = clk_prepare_enable(pwm->bus_clk); | |
454 | if (ret) { | |
455 | dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n", | |
456 | ERR_PTR(ret)); | |
457 | goto err_bus; | |
458 | } | |
459 | ||
09853ce7 AB |
460 | pwm->chip.dev = &pdev->dev; |
461 | pwm->chip.ops = &sun4i_pwm_ops; | |
f6649f7a | 462 | pwm->chip.npwm = pwm->data->npwm; |
09853ce7 AB |
463 | pwm->chip.of_xlate = of_pwm_xlate_with_flags; |
464 | pwm->chip.of_pwm_n_cells = 3; | |
09853ce7 AB |
465 | |
466 | spin_lock_init(&pwm->ctrl_lock); | |
467 | ||
468 | ret = pwmchip_add(&pwm->chip); | |
469 | if (ret < 0) { | |
470 | dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); | |
a7fe9856 | 471 | goto err_pwm_add; |
09853ce7 AB |
472 | } |
473 | ||
474 | platform_set_drvdata(pdev, pwm); | |
475 | ||
09853ce7 | 476 | return 0; |
a7fe9856 JS |
477 | |
478 | err_pwm_add: | |
5b090b43 JS |
479 | clk_disable_unprepare(pwm->bus_clk); |
480 | err_bus: | |
a7fe9856 JS |
481 | reset_control_assert(pwm->rst); |
482 | ||
483 | return ret; | |
09853ce7 AB |
484 | } |
485 | ||
486 | static int sun4i_pwm_remove(struct platform_device *pdev) | |
487 | { | |
488 | struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); | |
a7fe9856 JS |
489 | int ret; |
490 | ||
491 | ret = pwmchip_remove(&pwm->chip); | |
492 | if (ret) | |
493 | return ret; | |
494 | ||
5b090b43 | 495 | clk_disable_unprepare(pwm->bus_clk); |
a7fe9856 | 496 | reset_control_assert(pwm->rst); |
09853ce7 | 497 | |
a7fe9856 | 498 | return 0; |
09853ce7 AB |
499 | } |
500 | ||
501 | static struct platform_driver sun4i_pwm_driver = { | |
502 | .driver = { | |
503 | .name = "sun4i-pwm", | |
504 | .of_match_table = sun4i_pwm_dt_ids, | |
505 | }, | |
506 | .probe = sun4i_pwm_probe, | |
507 | .remove = sun4i_pwm_remove, | |
508 | }; | |
509 | module_platform_driver(sun4i_pwm_driver); | |
510 | ||
511 | MODULE_ALIAS("platform:sun4i-pwm"); | |
512 | MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>"); | |
513 | MODULE_DESCRIPTION("Allwinner sun4i PWM driver"); | |
514 | MODULE_LICENSE("GPL v2"); |