[linux-2.6-block.git] / drivers / pwm / pwm-sun4i.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Driver for Allwinner sun4i Pulse Width Modulation Controller
 *
 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
 */

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/time.h>

#define PWM_CTRL_REG		0x0

#define PWM_CH_PRD_BASE		0x4
#define PWM_CH_PRD_OFFSET	0x4
#define PWM_CH_PRD(ch)		(PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))

#define PWMCH_OFFSET		15
#define PWM_PRESCAL_MASK	GENMASK(3, 0)
#define PWM_PRESCAL_OFF		0
#define PWM_EN			BIT(4)
#define PWM_ACT_STATE		BIT(5)
#define PWM_CLK_GATING		BIT(6)
#define PWM_MODE		BIT(7)
#define PWM_PULSE		BIT(8)
#define PWM_BYPASS		BIT(9)

#define PWM_RDY_BASE		28
#define PWM_RDY_OFFSET		1
#define PWM_RDY(ch)		BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))

#define PWM_PRD(prd)		(((prd) - 1) << 16)
#define PWM_PRD_MASK		GENMASK(15, 0)

#define PWM_DTY_MASK		GENMASK(15, 0)

#define PWM_REG_PRD(reg)	((((reg) >> 16) & PWM_PRD_MASK) + 1)
#define PWM_REG_DTY(reg)	((reg) & PWM_DTY_MASK)
#define PWM_REG_PRESCAL(reg, chan)	(((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)

#define BIT_CH(bit, chan)	((bit) << ((chan) * PWMCH_OFFSET))

static const u32 prescaler_table[] = {
	120,
	180,
	240,
	360,
	480,
	0,
	0,
	0,
	12000,
	24000,
	36000,
	48000,
	72000,
	0,
	0,
	0, /* Actually 1 but tested separately */
};

struct sun4i_pwm_data {
	bool has_prescaler_bypass;
	unsigned int npwm;
};

struct sun4i_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	void __iomem *base;
	spinlock_t ctrl_lock;
	const struct sun4i_pwm_data *data;
	unsigned long next_period[2];
	bool needs_delay[2];
};

static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct sun4i_pwm_chip, chip);
}

static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
				  unsigned long offset)
{
	return readl(chip->base + offset);
}

static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
				    u32 val, unsigned long offset)
{
	writel(val, chip->base + offset);
}

static void sun4i_pwm_get_state(struct pwm_chip *chip,
				struct pwm_device *pwm,
				struct pwm_state *state)
{
	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
	u64 clk_rate, tmp;
	u32 val;
	unsigned int prescaler;

	clk_rate = clk_get_rate(sun4i_pwm->clk);

	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
	    sun4i_pwm->data->has_prescaler_bypass)
		prescaler = 1;
	else
		prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];

	if (prescaler == 0)
		return;

	if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
		state->polarity = PWM_POLARITY_NORMAL;
	else
		state->polarity = PWM_POLARITY_INVERSED;

	if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
	    BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
		state->enabled = true;
	else
		state->enabled = false;

	val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));

	tmp = prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);

	tmp = prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
}

static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
			       struct pwm_state *state,
			       u32 *dty, u32 *prd, unsigned int *prsclr)
{
	u64 clk_rate, div = 0;
	unsigned int pval, prescaler = 0;

	clk_rate = clk_get_rate(sun4i_pwm->clk);

	if (sun4i_pwm->data->has_prescaler_bypass) {
		/* First, test without any prescaler when available */
		prescaler = PWM_PRESCAL_MASK;
		pval = 1;
		/*
		 * When not using any prescaler, the clock period in nanoseconds
		 * is not an integer so round it half up instead of
		 * truncating to get less surprising values.
		 */
		div = clk_rate * state->period + NSEC_PER_SEC / 2;
		do_div(div, NSEC_PER_SEC);
		if (div - 1 > PWM_PRD_MASK)
			prescaler = 0;
	}

	if (prescaler == 0) {
		/* Go up from the first divider */
		for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
			if (!prescaler_table[prescaler])
				continue;
			pval = prescaler_table[prescaler];
			div = clk_rate;
			do_div(div, pval);
			div = div * state->period;
			do_div(div, NSEC_PER_SEC);
			if (div - 1 <= PWM_PRD_MASK)
				break;
		}

		if (div - 1 > PWM_PRD_MASK)
			return -EINVAL;
	}

	*prd = div;
	div *= state->duty_cycle;
	do_div(div, state->period);
	*dty = div;
	*prsclr = prescaler;

	div = (u64)pval * NSEC_PER_SEC * *prd;
	state->period = DIV_ROUND_CLOSEST_ULL(div, clk_rate);

	div = (u64)pval * NSEC_PER_SEC * *dty;
	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(div, clk_rate);

	return 0;
}

static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   struct pwm_state *state)
{
	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
	struct pwm_state cstate;
	u32 ctrl;
	int ret;
	unsigned int delay_us;
	unsigned long now;

	pwm_get_state(pwm, &cstate);

	if (!cstate.enabled) {
		ret = clk_prepare_enable(sun4i_pwm->clk);
		if (ret) {
			dev_err(chip->dev, "failed to enable PWM clock\n");
			return ret;
		}
	}

	spin_lock(&sun4i_pwm->ctrl_lock);
	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

	if ((cstate.period != state->period) ||
	    (cstate.duty_cycle != state->duty_cycle)) {
		u32 period, duty, val;
		unsigned int prescaler;

		ret = sun4i_pwm_calculate(sun4i_pwm, state,
					  &duty, &period, &prescaler);
		if (ret) {
			dev_err(chip->dev, "period exceeds the maximum value\n");
			spin_unlock(&sun4i_pwm->ctrl_lock);
			if (!cstate.enabled)
				clk_disable_unprepare(sun4i_pwm->clk);
			return ret;
		}

		if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
			/* Prescaler changed, the clock has to be gated */
			ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
			sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);

			ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
			ctrl |= BIT_CH(prescaler, pwm->hwpwm);
		}

		val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
		sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
		sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
			usecs_to_jiffies(cstate.period / 1000 + 1);
		sun4i_pwm->needs_delay[pwm->hwpwm] = true;
	}

	if (state->polarity != PWM_POLARITY_NORMAL)
		ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
	else
		ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);

	ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
	if (state->enabled) {
		ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
	} else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
		ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
		ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
	}

	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);

	spin_unlock(&sun4i_pwm->ctrl_lock);

	if (state->enabled)
		return 0;

	if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
		clk_disable_unprepare(sun4i_pwm->clk);
		return 0;
	}

	/* We need a full period to elapse before disabling the channel. */
	now = jiffies;
	if (sun4i_pwm->needs_delay[pwm->hwpwm] &&
	    time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
		delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
					   now);
		if ((delay_us / 500) > MAX_UDELAY_MS)
			msleep(delay_us / 1000 + 1);
		else
			usleep_range(delay_us, delay_us * 2);
	}
	sun4i_pwm->needs_delay[pwm->hwpwm] = false;

	spin_lock(&sun4i_pwm->ctrl_lock);
	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
	ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
	spin_unlock(&sun4i_pwm->ctrl_lock);

	clk_disable_unprepare(sun4i_pwm->clk);

	return 0;
}

static const struct pwm_ops sun4i_pwm_ops = {
	.apply = sun4i_pwm_apply,
	.get_state = sun4i_pwm_get_state,
	.owner = THIS_MODULE,
};

static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
	.has_prescaler_bypass = false,
	.npwm = 2,
};

static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
	.has_prescaler_bypass = true,
	.npwm = 2,
};

static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
	.has_prescaler_bypass = true,
	.npwm = 1,
};

static const struct of_device_id sun4i_pwm_dt_ids[] = {
	{
		.compatible = "allwinner,sun4i-a10-pwm",
		.data = &sun4i_pwm_dual_nobypass,
	}, {
		.compatible = "allwinner,sun5i-a10s-pwm",
		.data = &sun4i_pwm_dual_bypass,
	}, {
		.compatible = "allwinner,sun5i-a13-pwm",
		.data = &sun4i_pwm_single_bypass,
	}, {
		.compatible = "allwinner,sun7i-a20-pwm",
		.data = &sun4i_pwm_dual_bypass,
	}, {
		.compatible = "allwinner,sun8i-h3-pwm",
		.data = &sun4i_pwm_single_bypass,
	}, {
		/* sentinel */
	},
};
MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);

static int sun4i_pwm_probe(struct platform_device *pdev)
{
	struct sun4i_pwm_chip *pwm;
	struct resource *res;
	int ret;

	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
	if (!pwm)
		return -ENOMEM;

	pwm->data = of_device_get_match_data(&pdev->dev);
	if (!pwm->data)
		return -ENODEV;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pwm->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(pwm->base))
		return PTR_ERR(pwm->base);

	pwm->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pwm->clk))
		return PTR_ERR(pwm->clk);

	pwm->chip.dev = &pdev->dev;
	pwm->chip.ops = &sun4i_pwm_ops;
	pwm->chip.base = -1;
	pwm->chip.npwm = pwm->data->npwm;
	pwm->chip.of_xlate = of_pwm_xlate_with_flags;
	pwm->chip.of_pwm_n_cells = 3;

	spin_lock_init(&pwm->ctrl_lock);

	ret = pwmchip_add(&pwm->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
		return ret;
	}

	platform_set_drvdata(pdev, pwm);

	return 0;
}

static int sun4i_pwm_remove(struct platform_device *pdev)
{
	struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);

	return pwmchip_remove(&pwm->chip);
}

static struct platform_driver sun4i_pwm_driver = {
	.driver = {
		.name = "sun4i-pwm",
		.of_match_table = sun4i_pwm_dt_ids,
	},
	.probe = sun4i_pwm_probe,
	.remove = sun4i_pwm_remove,
};
module_platform_driver(sun4i_pwm_driver);

MODULE_ALIAS("platform:sun4i-pwm");
MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f50a7f3d	1	// SPDX-License-Identifier: GPL-2.0-only
09853ce7 AB	2	/*
	3	* Driver for Allwinner sun4i Pulse Width Modulation Controller
	4	*
	5	* Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
09853ce7 AB	6	*/
	7
	8	#include <linux/bitops.h>
	9	#include <linux/clk.h>
c32c5c50	10	#include <linux/delay.h>
09853ce7 AB	11	#include <linux/err.h>
09853ce7 AB	12	#include <linux/io.h>
c32c5c50	13	#include <linux/jiffies.h>
09853ce7 AB	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/of_device.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/pwm.h>
	19	#include <linux/slab.h>
	20	#include <linux/spinlock.h>
	21	#include <linux/time.h>
	22
	23	#define PWM_CTRL_REG 0x0
	24
	25	#define PWM_CH_PRD_BASE 0x4
	26	#define PWM_CH_PRD_OFFSET 0x4
	27	#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
	28
	29	#define PWMCH_OFFSET 15
	30	#define PWM_PRESCAL_MASK GENMASK(3, 0)
	31	#define PWM_PRESCAL_OFF 0
	32	#define PWM_EN BIT(4)
	33	#define PWM_ACT_STATE BIT(5)
	34	#define PWM_CLK_GATING BIT(6)
	35	#define PWM_MODE BIT(7)
	36	#define PWM_PULSE BIT(8)
	37	#define PWM_BYPASS BIT(9)
	38
	39	#define PWM_RDY_BASE 28
	40	#define PWM_RDY_OFFSET 1
	41	#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
	42
	43	#define PWM_PRD(prd) (((prd) - 1) << 16)
	44	#define PWM_PRD_MASK GENMASK(15, 0)
	45
	46	#define PWM_DTY_MASK GENMASK(15, 0)
	47
93e0dfb2 AB	48	#define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
	49	#define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
	50	#define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
	51
09853ce7 AB	52	#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
	53
	54	static const u32 prescaler_table[] = {
	55	120,
	56	180,
	57	240,
	58	360,
	59	480,
	60	0,
	61	0,
	62	0,
	63	12000,
	64	24000,
	65	36000,
	66	48000,
	67	72000,
	68	0,
	69	0,
	70	0, /* Actually 1 but tested separately */
	71	};
	72
	73	struct sun4i_pwm_data {
	74	bool has_prescaler_bypass;
f6649f7a	75	unsigned int npwm;
09853ce7 AB	76	};
	77
	78	struct sun4i_pwm_chip {
	79	struct pwm_chip chip;
	80	struct clk *clk;
	81	void __iomem *base;
	82	spinlock_t ctrl_lock;
	83	const struct sun4i_pwm_data *data;
c32c5c50 AB	84	unsigned long next_period[2];
c32c5c50 AB	85	bool needs_delay[2];
09853ce7 AB	86	};
	87
	88	static inline struct sun4i_pwm_chip to_sun4i_pwm_chip(struct pwm_chip chip)
	89	{
	90	return container_of(chip, struct sun4i_pwm_chip, chip);
	91	}
	92
	93	static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
	94	unsigned long offset)
	95	{
	96	return readl(chip->base + offset);
	97	}
	98
	99	static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
	100	u32 val, unsigned long offset)
	101	{
	102	writel(val, chip->base + offset);
	103	}
	104
93e0dfb2 AB	105	static void sun4i_pwm_get_state(struct pwm_chip *chip,
	106	struct pwm_device *pwm,
	107	struct pwm_state *state)
	108	{
	109	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
	110	u64 clk_rate, tmp;
	111	u32 val;
	112	unsigned int prescaler;
	113
	114	clk_rate = clk_get_rate(sun4i_pwm->clk);
	115
	116	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
	117
989ae7a5 AB	118	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
989ae7a5 AB	119	sun4i_pwm->data->has_prescaler_bypass)
93e0dfb2 AB	120	prescaler = 1;
	121	else
	122	prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
	123
	124	if (prescaler == 0)
	125	return;
	126
	127	if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
	128	state->polarity = PWM_POLARITY_NORMAL;
	129	else
	130	state->polarity = PWM_POLARITY_INVERSED;
	131
989ae7a5 AB	132	if ((val & BIT_CH(PWM_CLK_GATING \| PWM_EN, pwm->hwpwm)) ==
989ae7a5 AB	133	BIT_CH(PWM_CLK_GATING \| PWM_EN, pwm->hwpwm))
93e0dfb2 AB	134	state->enabled = true;
	135	else
	136	state->enabled = false;
	137
	138	val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
	139
	140	tmp = prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
	141	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
	142
	143	tmp = prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
	144	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
	145	}
	146
c32c5c50 AB	147	static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
	148	struct pwm_state *state,
	149	u32 dty, u32 prd, unsigned int *prsclr)
	150	{
	151	u64 clk_rate, div = 0;
	152	unsigned int pval, prescaler = 0;
	153
	154	clk_rate = clk_get_rate(sun4i_pwm->clk);
	155
	156	if (sun4i_pwm->data->has_prescaler_bypass) {
	157	/* First, test without any prescaler when available */
	158	prescaler = PWM_PRESCAL_MASK;
	159	pval = 1;
	160	/*
	161	* When not using any prescaler, the clock period in nanoseconds
	162	* is not an integer so round it half up instead of
	163	* truncating to get less surprising values.
	164	*/
	165	div = clk_rate * state->period + NSEC_PER_SEC / 2;
	166	do_div(div, NSEC_PER_SEC);
	167	if (div - 1 > PWM_PRD_MASK)
	168	prescaler = 0;
	169	}
	170
	171	if (prescaler == 0) {
	172	/* Go up from the first divider */
	173	for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
	174	if (!prescaler_table[prescaler])
	175	continue;
	176	pval = prescaler_table[prescaler];
	177	div = clk_rate;
	178	do_div(div, pval);
	179	div = div * state->period;
	180	do_div(div, NSEC_PER_SEC);
	181	if (div - 1 <= PWM_PRD_MASK)
	182	break;
	183	}
	184
	185	if (div - 1 > PWM_PRD_MASK)
	186	return -EINVAL;
	187	}
	188
	189	*prd = div;
	190	div *= state->duty_cycle;
	191	do_div(div, state->period);
	192	*dty = div;
	193	*prsclr = prescaler;
	194
	195	div = (u64)pval * NSEC_PER_SEC * *prd;
	196	state->period = DIV_ROUND_CLOSEST_ULL(div, clk_rate);
	197
	198	div = (u64)pval * NSEC_PER_SEC * *dty;
	199	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(div, clk_rate);
	200
	201	return 0;
	202	}
	203
	204	static int sun4i_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	205	struct pwm_state *state)
	206	{
	207	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
	208	struct pwm_state cstate;
	209	u32 ctrl;
	210	int ret;
211	unsigned int delay_us;
212	unsigned long now;
213
214	pwm_get_state(pwm, &cstate);
215
216	if (!cstate.enabled) {
217	ret = clk_prepare_enable(sun4i_pwm->clk);
218	if (ret) {
219	dev_err(chip->dev, "failed to enable PWM clock\n");
220	return ret;
221	}
222	}
223
224	spin_lock(&sun4i_pwm->ctrl_lock);
225	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
226
227	if ((cstate.period != state->period) \|\|
228	(cstate.duty_cycle != state->duty_cycle)) {
229	u32 period, duty, val;
230	unsigned int prescaler;
231
232	ret = sun4i_pwm_calculate(sun4i_pwm, state,
233	&duty, &period, &prescaler);
234	if (ret) {
235	dev_err(chip->dev, "period exceeds the maximum value\n");
236	spin_unlock(&sun4i_pwm->ctrl_lock);
237	if (!cstate.enabled)
238	clk_disable_unprepare(sun4i_pwm->clk);
239	return ret;
240	}
241
242	if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
243	/* Prescaler changed, the clock has to be gated */
244	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
245	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
246
247	ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
248	ctrl \|= BIT_CH(prescaler, pwm->hwpwm);
249	}
250
251	val = (duty & PWM_DTY_MASK) \| PWM_PRD(period);
252	sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
253	sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
254	usecs_to_jiffies(cstate.period / 1000 + 1);
255	sun4i_pwm->needs_delay[pwm->hwpwm] = true;
256	}
257
258	if (state->polarity != PWM_POLARITY_NORMAL)
259	ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
260	else
261	ctrl \|= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
262
263	ctrl \|= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
264	if (state->enabled) {
265	ctrl \|= BIT_CH(PWM_EN, pwm->hwpwm);
266	} else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
267	ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
268	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
269	}
270
271	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
272
273	spin_unlock(&sun4i_pwm->ctrl_lock);
274
275	if (state->enabled)
276	return 0;
277
278	if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
279	clk_disable_unprepare(sun4i_pwm->clk);
280	return 0;
281	}
282
283	/* We need a full period to elapse before disabling the channel. */
284	now = jiffies;
285	if (sun4i_pwm->needs_delay[pwm->hwpwm] &&
286	time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
287	delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
288	now);
289	if ((delay_us / 500) > MAX_UDELAY_MS)
290	msleep(delay_us / 1000 + 1);
291	else
292	usleep_range(delay_us, delay_us * 2);
293	}
294	sun4i_pwm->needs_delay[pwm->hwpwm] = false;
295
296	spin_lock(&sun4i_pwm->ctrl_lock);
297	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
298	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
299	ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
300	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
301	spin_unlock(&sun4i_pwm->ctrl_lock);
302
303	clk_disable_unprepare(sun4i_pwm->clk);
304
305	return 0;
306	}
307
09853ce7	308	static const struct pwm_ops sun4i_pwm_ops = {
c32c5c50	309	.apply = sun4i_pwm_apply,
93e0dfb2	310	.get_state = sun4i_pwm_get_state,
09853ce7 AB	311	.owner = THIS_MODULE,
	312	};
	313
7b4c7c56	314	static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
09853ce7	315	.has_prescaler_bypass = false,
f6649f7a HG	316	.npwm = 2,
	317	};
	318
7b4c7c56	319	static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
f6649f7a	320	.has_prescaler_bypass = true,
f6649f7a HG	321	.npwm = 2,
	322	};
	323
7b4c7c56	324	static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
42ddcf4f	325	.has_prescaler_bypass = true,
42ddcf4f MK	326	.npwm = 1,
	327	};
	328
09853ce7 AB	329	static const struct of_device_id sun4i_pwm_dt_ids[] = {
	330	{
	331	.compatible = "allwinner,sun4i-a10-pwm",
7b4c7c56	332	.data = &sun4i_pwm_dual_nobypass,
f6649f7a HG	333	}, {
f6649f7a HG	334	.compatible = "allwinner,sun5i-a10s-pwm",
7b4c7c56	335	.data = &sun4i_pwm_dual_bypass,
f6649f7a HG	336	}, {
f6649f7a HG	337	.compatible = "allwinner,sun5i-a13-pwm",
7b4c7c56	338	.data = &sun4i_pwm_single_bypass,
09853ce7 AB	339	}, {
09853ce7 AB	340	.compatible = "allwinner,sun7i-a20-pwm",
7b4c7c56	341	.data = &sun4i_pwm_dual_bypass,
42ddcf4f MK	342	}, {
42ddcf4f MK	343	.compatible = "allwinner,sun8i-h3-pwm",
7b4c7c56	344	.data = &sun4i_pwm_single_bypass,
09853ce7 AB	345	}, {
	346	/* sentinel */
	347	},
	348	};
	349	MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
	350
	351	static int sun4i_pwm_probe(struct platform_device *pdev)
	352	{
	353	struct sun4i_pwm_chip *pwm;
	354	struct resource *res;
93e0dfb2	355	int ret;
09853ce7 AB	356
	357	pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
	358	if (!pwm)
	359	return -ENOMEM;
	360
df4f6e8c CL	361	pwm->data = of_device_get_match_data(&pdev->dev);
	362	if (!pwm->data)
	363	return -ENODEV;
	364
09853ce7 AB	365	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	366	pwm->base = devm_ioremap_resource(&pdev->dev, res);
	367	if (IS_ERR(pwm->base))
	368	return PTR_ERR(pwm->base);
	369
	370	pwm->clk = devm_clk_get(&pdev->dev, NULL);
	371	if (IS_ERR(pwm->clk))
	372	return PTR_ERR(pwm->clk);
	373
	374	pwm->chip.dev = &pdev->dev;
	375	pwm->chip.ops = &sun4i_pwm_ops;
	376	pwm->chip.base = -1;
f6649f7a	377	pwm->chip.npwm = pwm->data->npwm;
09853ce7 AB	378	pwm->chip.of_xlate = of_pwm_xlate_with_flags;
09853ce7 AB	379	pwm->chip.of_pwm_n_cells = 3;
09853ce7 AB	380
	381	spin_lock_init(&pwm->ctrl_lock);
	382
	383	ret = pwmchip_add(&pwm->chip);
	384	if (ret < 0) {
	385	dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
	386	return ret;
	387	}
	388
	389	platform_set_drvdata(pdev, pwm);
	390
09853ce7	391	return 0;
09853ce7 AB	392	}
	393
	394	static int sun4i_pwm_remove(struct platform_device *pdev)
	395	{
	396	struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
	397
	398	return pwmchip_remove(&pwm->chip);
	399	}
	400
	401	static struct platform_driver sun4i_pwm_driver = {
	402	.driver = {
	403	.name = "sun4i-pwm",
	404	.of_match_table = sun4i_pwm_dt_ids,
	405	},
	406	.probe = sun4i_pwm_probe,
	407	.remove = sun4i_pwm_remove,
	408	};
	409	module_platform_driver(sun4i_pwm_driver);
	410
	411	MODULE_ALIAS("platform:sun4i-pwm");
	412	MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
	413	MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
	414	MODULE_LICENSE("GPL v2");