[linux-block.git] / drivers / pwm / pwm-sun4i.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Driver for Allwinner sun4i Pulse Width Modulation Controller
 *
 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
 *
 * Limitations:
 * - When outputing the source clock directly, the PWM logic will be bypassed
 *   and the currently running period is not guaranteed to be completed
 */

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/time.h>

#define PWM_CTRL_REG		0x0

#define PWM_CH_PRD_BASE		0x4
#define PWM_CH_PRD_OFFSET	0x4
#define PWM_CH_PRD(ch)		(PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))

#define PWMCH_OFFSET		15
#define PWM_PRESCAL_MASK	GENMASK(3, 0)
#define PWM_PRESCAL_OFF		0
#define PWM_EN			BIT(4)
#define PWM_ACT_STATE		BIT(5)
#define PWM_CLK_GATING		BIT(6)
#define PWM_MODE		BIT(7)
#define PWM_PULSE		BIT(8)
#define PWM_BYPASS		BIT(9)

#define PWM_RDY_BASE		28
#define PWM_RDY_OFFSET		1
#define PWM_RDY(ch)		BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))

#define PWM_PRD(prd)		(((prd) - 1) << 16)
#define PWM_PRD_MASK		GENMASK(15, 0)

#define PWM_DTY_MASK		GENMASK(15, 0)

#define PWM_REG_PRD(reg)	((((reg) >> 16) & PWM_PRD_MASK) + 1)
#define PWM_REG_DTY(reg)	((reg) & PWM_DTY_MASK)
#define PWM_REG_PRESCAL(reg, chan)	(((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)

#define BIT_CH(bit, chan)	((bit) << ((chan) * PWMCH_OFFSET))

static const u32 prescaler_table[] = {
	120,
	180,
	240,
	360,
	480,
	0,
	0,
	0,
	12000,
	24000,
	36000,
	48000,
	72000,
	0,
	0,
	0, /* Actually 1 but tested separately */
};

struct sun4i_pwm_data {
	bool has_prescaler_bypass;
	bool has_direct_mod_clk_output;
	unsigned int npwm;
};

struct sun4i_pwm_chip {
	struct pwm_chip chip;
	struct clk *bus_clk;
	struct clk *clk;
	struct reset_control *rst;
	void __iomem *base;
	spinlock_t ctrl_lock;
	const struct sun4i_pwm_data *data;
};

static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct sun4i_pwm_chip, chip);
}

static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
				  unsigned long offset)
{
	return readl(chip->base + offset);
}

static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
				    u32 val, unsigned long offset)
{
	writel(val, chip->base + offset);
}

static int sun4i_pwm_get_state(struct pwm_chip *chip,
			       struct pwm_device *pwm,
			       struct pwm_state *state)
{
	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
	u64 clk_rate, tmp;
	u32 val;
	unsigned int prescaler;

	clk_rate = clk_get_rate(sun4i_pwm->clk);
	if (!clk_rate)
		return -EINVAL;

	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

	/*
	 * PWM chapter in H6 manual has a diagram which explains that if bypass
	 * bit is set, no other setting has any meaning. Even more, experiment
	 * proved that also enable bit is ignored in this case.
	 */
	if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
	    sun4i_pwm->data->has_direct_mod_clk_output) {
		state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
		state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
		state->polarity = PWM_POLARITY_NORMAL;
		state->enabled = true;
		return 0;
	}

	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
	    sun4i_pwm->data->has_prescaler_bypass)
		prescaler = 1;
	else
		prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];

	if (prescaler == 0)
		return -EINVAL;

	if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
		state->polarity = PWM_POLARITY_NORMAL;
	else
		state->polarity = PWM_POLARITY_INVERSED;

	if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
	    BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
		state->enabled = true;
	else
		state->enabled = false;

	val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));

	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);

	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);

	return 0;
}

static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
			       const struct pwm_state *state,
			       u32 *dty, u32 *prd, unsigned int *prsclr,
			       bool *bypass)
{
	u64 clk_rate, div = 0;
	unsigned int prescaler = 0;

	clk_rate = clk_get_rate(sun4i_pwm->clk);

	*bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
		  state->enabled &&
		  (state->period * clk_rate >= NSEC_PER_SEC) &&
		  (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
		  (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);

	/* Skip calculation of other parameters if we bypass them */
	if (*bypass)
		return 0;

	if (sun4i_pwm->data->has_prescaler_bypass) {
		/* First, test without any prescaler when available */
		prescaler = PWM_PRESCAL_MASK;
		/*
		 * When not using any prescaler, the clock period in nanoseconds
		 * is not an integer so round it half up instead of
		 * truncating to get less surprising values.
		 */
		div = clk_rate * state->period + NSEC_PER_SEC / 2;
		do_div(div, NSEC_PER_SEC);
		if (div - 1 > PWM_PRD_MASK)
			prescaler = 0;
	}

	if (prescaler == 0) {
		/* Go up from the first divider */
		for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
			unsigned int pval = prescaler_table[prescaler];

			if (!pval)
				continue;

			div = clk_rate;
			do_div(div, pval);
			div = div * state->period;
			do_div(div, NSEC_PER_SEC);
			if (div - 1 <= PWM_PRD_MASK)
				break;
		}

		if (div - 1 > PWM_PRD_MASK)
			return -EINVAL;
	}

	*prd = div;
	div *= state->duty_cycle;
	do_div(div, state->period);
	*dty = div;
	*prsclr = prescaler;

	return 0;
}

static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{
	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
	struct pwm_state cstate;
	u32 ctrl, duty = 0, period = 0, val;
	int ret;
	unsigned int delay_us, prescaler = 0;
	bool bypass;

	pwm_get_state(pwm, &cstate);

	if (!cstate.enabled) {
		ret = clk_prepare_enable(sun4i_pwm->clk);
		if (ret) {
			dev_err(chip->dev, "failed to enable PWM clock\n");
			return ret;
		}
	}

	ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
				  &bypass);
	if (ret) {
		dev_err(chip->dev, "period exceeds the maximum value\n");
		if (!cstate.enabled)
			clk_disable_unprepare(sun4i_pwm->clk);
		return ret;
	}

	spin_lock(&sun4i_pwm->ctrl_lock);
	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);

	if (sun4i_pwm->data->has_direct_mod_clk_output) {
		if (bypass) {
			ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
			/* We can skip other parameter */
			sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
			spin_unlock(&sun4i_pwm->ctrl_lock);
			return 0;
		}

		ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
	}

	if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
		/* Prescaler changed, the clock has to be gated */
		ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
		sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);

		ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
		ctrl |= BIT_CH(prescaler, pwm->hwpwm);
	}

	val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
	sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));

	if (state->polarity != PWM_POLARITY_NORMAL)
		ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
	else
		ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);

	ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);

	if (state->enabled)
		ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);

	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);

	spin_unlock(&sun4i_pwm->ctrl_lock);

	if (state->enabled)
		return 0;

	/* We need a full period to elapse before disabling the channel. */
	delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC);
	if ((delay_us / 500) > MAX_UDELAY_MS)
		msleep(delay_us / 1000 + 1);
	else
		usleep_range(delay_us, delay_us * 2);

	spin_lock(&sun4i_pwm->ctrl_lock);
	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
	ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
	spin_unlock(&sun4i_pwm->ctrl_lock);

	clk_disable_unprepare(sun4i_pwm->clk);

	return 0;
}

static const struct pwm_ops sun4i_pwm_ops = {
	.apply = sun4i_pwm_apply,
	.get_state = sun4i_pwm_get_state,
	.owner = THIS_MODULE,
};

static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
	.has_prescaler_bypass = false,
	.npwm = 2,
};

static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
	.has_prescaler_bypass = true,
	.npwm = 2,
};

static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
	.has_prescaler_bypass = true,
	.npwm = 1,
};

static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
	.has_prescaler_bypass = true,
	.has_direct_mod_clk_output = true,
	.npwm = 1,
};

static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
	.has_prescaler_bypass = true,
	.has_direct_mod_clk_output = true,
	.npwm = 2,
};

static const struct of_device_id sun4i_pwm_dt_ids[] = {
	{
		.compatible = "allwinner,sun4i-a10-pwm",
		.data = &sun4i_pwm_dual_nobypass,
	}, {
		.compatible = "allwinner,sun5i-a10s-pwm",
		.data = &sun4i_pwm_dual_bypass,
	}, {
		.compatible = "allwinner,sun5i-a13-pwm",
		.data = &sun4i_pwm_single_bypass,
	}, {
		.compatible = "allwinner,sun7i-a20-pwm",
		.data = &sun4i_pwm_dual_bypass,
	}, {
		.compatible = "allwinner,sun8i-h3-pwm",
		.data = &sun4i_pwm_single_bypass,
	}, {
		.compatible = "allwinner,sun50i-a64-pwm",
		.data = &sun50i_a64_pwm_data,
	}, {
		.compatible = "allwinner,sun50i-h6-pwm",
		.data = &sun50i_h6_pwm_data,
	}, {
		/* sentinel */
	},
};
MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);

static int sun4i_pwm_probe(struct platform_device *pdev)
{
	struct sun4i_pwm_chip *sun4ichip;
	int ret;

	sun4ichip = devm_kzalloc(&pdev->dev, sizeof(*sun4ichip), GFP_KERNEL);
	if (!sun4ichip)
		return -ENOMEM;

	sun4ichip->data = of_device_get_match_data(&pdev->dev);
	if (!sun4ichip->data)
		return -ENODEV;

	sun4ichip->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(sun4ichip->base))
		return PTR_ERR(sun4ichip->base);

	/*
	 * All hardware variants need a source clock that is divided and
	 * then feeds the counter that defines the output wave form. In the
	 * device tree this clock is either unnamed or called "mod".
	 * Some variants (e.g. H6) need another clock to access the
	 * hardware registers; this is called "bus".
	 * So we request "mod" first (and ignore the corner case that a
	 * parent provides a "mod" clock while the right one would be the
	 * unnamed one of the PWM device) and if this is not found we fall
	 * back to the first clock of the PWM.
	 */
	sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod");
	if (IS_ERR(sun4ichip->clk))
		return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
				     "get mod clock failed\n");

	if (!sun4ichip->clk) {
		sun4ichip->clk = devm_clk_get(&pdev->dev, NULL);
		if (IS_ERR(sun4ichip->clk))
			return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
					     "get unnamed clock failed\n");
	}

	sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
	if (IS_ERR(sun4ichip->bus_clk))
		return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk),
				     "get bus clock failed\n");

	sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
	if (IS_ERR(sun4ichip->rst))
		return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst),
				     "get reset failed\n");

	/* Deassert reset */
	ret = reset_control_deassert(sun4ichip->rst);
	if (ret) {
		dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
			ERR_PTR(ret));
		return ret;
	}

	/*
	 * We're keeping the bus clock on for the sake of simplicity.
	 * Actually it only needs to be on for hardware register accesses.
	 */
	ret = clk_prepare_enable(sun4ichip->bus_clk);
	if (ret) {
		dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
			ERR_PTR(ret));
		goto err_bus;
	}

	sun4ichip->chip.dev = &pdev->dev;
	sun4ichip->chip.ops = &sun4i_pwm_ops;
	sun4ichip->chip.npwm = sun4ichip->data->npwm;

	spin_lock_init(&sun4ichip->ctrl_lock);

	ret = pwmchip_add(&sun4ichip->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
		goto err_pwm_add;
	}

	platform_set_drvdata(pdev, sun4ichip);

	return 0;

err_pwm_add:
	clk_disable_unprepare(sun4ichip->bus_clk);
err_bus:
	reset_control_assert(sun4ichip->rst);

	return ret;
}

static int sun4i_pwm_remove(struct platform_device *pdev)
{
	struct sun4i_pwm_chip *sun4ichip = platform_get_drvdata(pdev);

	pwmchip_remove(&sun4ichip->chip);

	clk_disable_unprepare(sun4ichip->bus_clk);
	reset_control_assert(sun4ichip->rst);

	return 0;
}

static struct platform_driver sun4i_pwm_driver = {
	.driver = {
		.name = "sun4i-pwm",
		.of_match_table = sun4i_pwm_dt_ids,
	},
	.probe = sun4i_pwm_probe,
	.remove = sun4i_pwm_remove,
};
module_platform_driver(sun4i_pwm_driver);

MODULE_ALIAS("platform:sun4i-pwm");
MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f50a7f3d	1	// SPDX-License-Identifier: GPL-2.0-only
09853ce7 AB	2	/*
	3	* Driver for Allwinner sun4i Pulse Width Modulation Controller
	4	*
	5	* Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
9f28e95b JS	6	*
	7	* Limitations:
	8	* - When outputing the source clock directly, the PWM logic will be bypassed
	9	* and the currently running period is not guaranteed to be completed
09853ce7 AB	10	*/
	11
	12	#include <linux/bitops.h>
	13	#include <linux/clk.h>
c32c5c50	14	#include <linux/delay.h>
09853ce7 AB	15	#include <linux/err.h>
09853ce7 AB	16	#include <linux/io.h>
c32c5c50	17	#include <linux/jiffies.h>
09853ce7 AB	18	#include <linux/module.h>
	19	#include <linux/of.h>
	20	#include <linux/of_device.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/pwm.h>
a7fe9856	23	#include <linux/reset.h>
09853ce7 AB	24	#include <linux/slab.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/time.h>
	27
	28	#define PWM_CTRL_REG 0x0
	29
	30	#define PWM_CH_PRD_BASE 0x4
	31	#define PWM_CH_PRD_OFFSET 0x4
	32	#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
	33
	34	#define PWMCH_OFFSET 15
	35	#define PWM_PRESCAL_MASK GENMASK(3, 0)
	36	#define PWM_PRESCAL_OFF 0
	37	#define PWM_EN BIT(4)
	38	#define PWM_ACT_STATE BIT(5)
	39	#define PWM_CLK_GATING BIT(6)
	40	#define PWM_MODE BIT(7)
	41	#define PWM_PULSE BIT(8)
	42	#define PWM_BYPASS BIT(9)
	43
	44	#define PWM_RDY_BASE 28
	45	#define PWM_RDY_OFFSET 1
	46	#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
	47
	48	#define PWM_PRD(prd) (((prd) - 1) << 16)
	49	#define PWM_PRD_MASK GENMASK(15, 0)
	50
	51	#define PWM_DTY_MASK GENMASK(15, 0)
	52
93e0dfb2 AB	53	#define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
	54	#define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
	55	#define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
	56
09853ce7 AB	57	#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
	58
	59	static const u32 prescaler_table[] = {
	60	120,
	61	180,
	62	240,
	63	360,
	64	480,
	65	0,
	66	0,
	67	0,
	68	12000,
	69	24000,
	70	36000,
	71	48000,
	72	72000,
	73	0,
	74	0,
	75	0, /* Actually 1 but tested separately */
	76	};
	77
	78	struct sun4i_pwm_data {
	79	bool has_prescaler_bypass;
9f28e95b	80	bool has_direct_mod_clk_output;
f6649f7a	81	unsigned int npwm;
09853ce7 AB	82	};
	83
	84	struct sun4i_pwm_chip {
	85	struct pwm_chip chip;
5b090b43	86	struct clk *bus_clk;
09853ce7	87	struct clk *clk;
a7fe9856	88	struct reset_control *rst;
09853ce7 AB	89	void __iomem *base;
	90	spinlock_t ctrl_lock;
	91	const struct sun4i_pwm_data *data;
	92	};
	93
	94	static inline struct sun4i_pwm_chip to_sun4i_pwm_chip(struct pwm_chip chip)
	95	{
	96	return container_of(chip, struct sun4i_pwm_chip, chip);
	97	}
	98
	99	static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
	100	unsigned long offset)
	101	{
	102	return readl(chip->base + offset);
	103	}
	104
	105	static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
	106	u32 val, unsigned long offset)
	107	{
	108	writel(val, chip->base + offset);
	109	}
	110
6c452cff UKK	111	static int sun4i_pwm_get_state(struct pwm_chip *chip,
	112	struct pwm_device *pwm,
	113	struct pwm_state *state)
93e0dfb2 AB	114	{
	115	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
	116	u64 clk_rate, tmp;
	117	u32 val;
	118	unsigned int prescaler;
	119
	120	clk_rate = clk_get_rate(sun4i_pwm->clk);
a08b318a AP	121	if (!clk_rate)
a08b318a AP	122	return -EINVAL;
93e0dfb2 AB	123
	124	val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
	125
9f28e95b JS	126	/*
	127	* PWM chapter in H6 manual has a diagram which explains that if bypass
	128	* bit is set, no other setting has any meaning. Even more, experiment
	129	* proved that also enable bit is ignored in this case.
	130	*/
	131	if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
	132	sun4i_pwm->data->has_direct_mod_clk_output) {
	133	state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
	134	state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
	135	state->polarity = PWM_POLARITY_NORMAL;
	136	state->enabled = true;
6c452cff	137	return 0;
9f28e95b JS	138	}
9f28e95b JS	139
989ae7a5 AB	140	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
989ae7a5 AB	141	sun4i_pwm->data->has_prescaler_bypass)
93e0dfb2 AB	142	prescaler = 1;
	143	else
	144	prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
	145
	146	if (prescaler == 0)
a08b318a	147	return -EINVAL;
93e0dfb2 AB	148
	149	if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
	150	state->polarity = PWM_POLARITY_NORMAL;
	151	else
	152	state->polarity = PWM_POLARITY_INVERSED;
	153
989ae7a5 AB	154	if ((val & BIT_CH(PWM_CLK_GATING \| PWM_EN, pwm->hwpwm)) ==
989ae7a5 AB	155	BIT_CH(PWM_CLK_GATING \| PWM_EN, pwm->hwpwm))
93e0dfb2 AB	156	state->enabled = true;
	157	else
	158	state->enabled = false;
	159
	160	val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
	161
50cc7e3e	162	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
93e0dfb2 AB	163	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
93e0dfb2 AB	164
50cc7e3e	165	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
93e0dfb2	166	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
6c452cff UKK	167
6c452cff UKK	168	return 0;
93e0dfb2 AB	169	}
93e0dfb2 AB	170
c32c5c50	171	static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
71523d18	172	const struct pwm_state *state,
9f28e95b JS	173	u32 dty, u32 prd, unsigned int *prsclr,
9f28e95b JS	174	bool *bypass)
c32c5c50 AB	175	{
c32c5c50 AB	176	u64 clk_rate, div = 0;
f6003f94	177	unsigned int prescaler = 0;
c32c5c50 AB	178
	179	clk_rate = clk_get_rate(sun4i_pwm->clk);
	180
9f28e95b JS	181	*bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
	182	state->enabled &&
	183	(state->period * clk_rate >= NSEC_PER_SEC) &&
	184	(state->period * clk_rate < 2 * NSEC_PER_SEC) &&
	185	(state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
	186
	187	/* Skip calculation of other parameters if we bypass them */
	188	if (*bypass)
	189	return 0;
	190
c32c5c50 AB	191	if (sun4i_pwm->data->has_prescaler_bypass) {
	192	/* First, test without any prescaler when available */
	193	prescaler = PWM_PRESCAL_MASK;
c32c5c50 AB	194	/*
	195	* When not using any prescaler, the clock period in nanoseconds
	196	* is not an integer so round it half up instead of
	197	* truncating to get less surprising values.
	198	*/
	199	div = clk_rate * state->period + NSEC_PER_SEC / 2;
	200	do_div(div, NSEC_PER_SEC);
	201	if (div - 1 > PWM_PRD_MASK)
	202	prescaler = 0;
	203	}
	204
	205	if (prescaler == 0) {
	206	/* Go up from the first divider */
	207	for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
f6003f94 UKK	208	unsigned int pval = prescaler_table[prescaler];
	209
	210	if (!pval)
c32c5c50	211	continue;
f6003f94	212
c32c5c50 AB	213	div = clk_rate;
	214	do_div(div, pval);
	215	div = div * state->period;
	216	do_div(div, NSEC_PER_SEC);
	217	if (div - 1 <= PWM_PRD_MASK)
	218	break;
	219	}
	220
	221	if (div - 1 > PWM_PRD_MASK)
	222	return -EINVAL;
	223	}
	224
	225	*prd = div;
	226	div *= state->duty_cycle;
	227	do_div(div, state->period);
	228	*dty = div;
	229	*prsclr = prescaler;
	230
c32c5c50 AB	231	return 0;
	232	}
	233
	234	static int sun4i_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	235	const struct pwm_state *state)
c32c5c50 AB	236	{
	237	struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
	238	struct pwm_state cstate;
413c2a11	239	u32 ctrl, duty = 0, period = 0, val;
c32c5c50	240	int ret;
413c2a11	241	unsigned int delay_us, prescaler = 0;
9f28e95b	242	bool bypass;
c32c5c50 AB	243
	244	pwm_get_state(pwm, &cstate);
	245
	246	if (!cstate.enabled) {
	247	ret = clk_prepare_enable(sun4i_pwm->clk);
	248	if (ret) {
	249	dev_err(chip->dev, "failed to enable PWM clock\n");
	250	return ret;
	251	}
	252	}
	253
9f28e95b JS	254	ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
9f28e95b JS	255	&bypass);
fa4d8178 CP	256	if (ret) {
fa4d8178 CP	257	dev_err(chip->dev, "period exceeds the maximum value\n");
fa4d8178 CP	258	if (!cstate.enabled)
	259	clk_disable_unprepare(sun4i_pwm->clk);
	260	return ret;
	261	}
c32c5c50	262
3e954d96 CP	263	spin_lock(&sun4i_pwm->ctrl_lock);
	264	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
	265
9f28e95b JS	266	if (sun4i_pwm->data->has_direct_mod_clk_output) {
	267	if (bypass) {
	268	ctrl \|= BIT_CH(PWM_BYPASS, pwm->hwpwm);
	269	/* We can skip other parameter */
	270	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
	271	spin_unlock(&sun4i_pwm->ctrl_lock);
	272	return 0;
	273	}
	274
	275	ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
	276	}
	277
fa4d8178 CP	278	if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
	279	/* Prescaler changed, the clock has to be gated */
	280	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
	281	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
c32c5c50	282
fa4d8178 CP	283	ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
fa4d8178 CP	284	ctrl \|= BIT_CH(prescaler, pwm->hwpwm);
c32c5c50 AB	285	}
c32c5c50 AB	286
fa4d8178 CP	287	val = (duty & PWM_DTY_MASK) \| PWM_PRD(period);
fa4d8178 CP	288	sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
fa4d8178	289
c32c5c50 AB	290	if (state->polarity != PWM_POLARITY_NORMAL)
	291	ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
	292	else
	293	ctrl \|= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
	294
	295	ctrl \|= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
fa4d8178	296
6eefb79d	297	if (state->enabled)
c32c5c50	298	ctrl \|= BIT_CH(PWM_EN, pwm->hwpwm);
c32c5c50 AB	299
	300	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
	301
	302	spin_unlock(&sun4i_pwm->ctrl_lock);
	303
	304	if (state->enabled)
	305	return 0;
	306
c32c5c50	307	/* We need a full period to elapse before disabling the channel. */
8246b478	308	delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC);
ba3e5037 MK	309	if ((delay_us / 500) > MAX_UDELAY_MS)
	310	msleep(delay_us / 1000 + 1);
	311	else
	312	usleep_range(delay_us, delay_us * 2);
c32c5c50 AB	313
	314	spin_lock(&sun4i_pwm->ctrl_lock);
	315	ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
	316	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
	317	ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
	318	sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
	319	spin_unlock(&sun4i_pwm->ctrl_lock);
	320
	321	clk_disable_unprepare(sun4i_pwm->clk);
	322
	323	return 0;
	324	}
	325
09853ce7	326	static const struct pwm_ops sun4i_pwm_ops = {
c32c5c50	327	.apply = sun4i_pwm_apply,
93e0dfb2	328	.get_state = sun4i_pwm_get_state,
09853ce7 AB	329	.owner = THIS_MODULE,
	330	};
	331
7b4c7c56	332	static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
09853ce7	333	.has_prescaler_bypass = false,
f6649f7a HG	334	.npwm = 2,
	335	};
	336
7b4c7c56	337	static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
f6649f7a	338	.has_prescaler_bypass = true,
f6649f7a HG	339	.npwm = 2,
	340	};
	341
7b4c7c56	342	static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
42ddcf4f	343	.has_prescaler_bypass = true,
42ddcf4f MK	344	.npwm = 1,
	345	};
	346
856c45d8 PV	347	static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
	348	.has_prescaler_bypass = true,
	349	.has_direct_mod_clk_output = true,
	350	.npwm = 1,
	351	};
	352
fdd2c12e JS	353	static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
	354	.has_prescaler_bypass = true,
	355	.has_direct_mod_clk_output = true,
	356	.npwm = 2,
	357	};
	358
09853ce7 AB	359	static const struct of_device_id sun4i_pwm_dt_ids[] = {
	360	{
	361	.compatible = "allwinner,sun4i-a10-pwm",
7b4c7c56	362	.data = &sun4i_pwm_dual_nobypass,
f6649f7a HG	363	}, {
f6649f7a HG	364	.compatible = "allwinner,sun5i-a10s-pwm",
7b4c7c56	365	.data = &sun4i_pwm_dual_bypass,
f6649f7a HG	366	}, {
f6649f7a HG	367	.compatible = "allwinner,sun5i-a13-pwm",
7b4c7c56	368	.data = &sun4i_pwm_single_bypass,
09853ce7 AB	369	}, {
09853ce7 AB	370	.compatible = "allwinner,sun7i-a20-pwm",
7b4c7c56	371	.data = &sun4i_pwm_dual_bypass,
42ddcf4f MK	372	}, {
42ddcf4f MK	373	.compatible = "allwinner,sun8i-h3-pwm",
7b4c7c56	374	.data = &sun4i_pwm_single_bypass,
856c45d8 PV	375	}, {
	376	.compatible = "allwinner,sun50i-a64-pwm",
	377	.data = &sun50i_a64_pwm_data,
fdd2c12e JS	378	}, {
	379	.compatible = "allwinner,sun50i-h6-pwm",
	380	.data = &sun50i_h6_pwm_data,
09853ce7 AB	381	}, {
	382	/* sentinel */
	383	},
	384	};
	385	MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
	386
	387	static int sun4i_pwm_probe(struct platform_device *pdev)
	388	{
c4fab452	389	struct sun4i_pwm_chip *sun4ichip;
93e0dfb2	390	int ret;
09853ce7	391
c4fab452 UKK	392	sun4ichip = devm_kzalloc(&pdev->dev, sizeof(*sun4ichip), GFP_KERNEL);
c4fab452 UKK	393	if (!sun4ichip)
09853ce7 AB	394	return -ENOMEM;
09853ce7 AB	395
c4fab452 UKK	396	sun4ichip->data = of_device_get_match_data(&pdev->dev);
c4fab452 UKK	397	if (!sun4ichip->data)
df4f6e8c CL	398	return -ENODEV;
df4f6e8c CL	399
c4fab452 UKK	400	sun4ichip->base = devm_platform_ioremap_resource(pdev, 0);
	401	if (IS_ERR(sun4ichip->base))
	402	return PTR_ERR(sun4ichip->base);
09853ce7	403
b8d74644 CP	404	/*
	405	* All hardware variants need a source clock that is divided and
	406	* then feeds the counter that defines the output wave form. In the
	407	* device tree this clock is either unnamed or called "mod".
	408	* Some variants (e.g. H6) need another clock to access the
	409	* hardware registers; this is called "bus".
	410	* So we request "mod" first (and ignore the corner case that a
	411	* parent provides a "mod" clock while the right one would be the
	412	* unnamed one of the PWM device) and if this is not found we fall
	413	* back to the first clock of the PWM.
	414	*/
c4fab452 UKK	415	sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod");
	416	if (IS_ERR(sun4ichip->clk))
	417	return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
5327f34b	418	"get mod clock failed\n");
b8d74644	419
c4fab452 UKK	420	if (!sun4ichip->clk) {
	421	sun4ichip->clk = devm_clk_get(&pdev->dev, NULL);
	422	if (IS_ERR(sun4ichip->clk))
	423	return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
5327f34b	424	"get unnamed clock failed\n");
b8d74644	425	}
09853ce7	426
c4fab452 UKK	427	sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
	428	if (IS_ERR(sun4ichip->bus_clk))
	429	return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk),
5327f34b	430	"get bus clock failed\n");
5b090b43	431
c4fab452 UKK	432	sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
	433	if (IS_ERR(sun4ichip->rst))
	434	return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst),
5327f34b	435	"get reset failed\n");
a7fe9856 JS	436
a7fe9856 JS	437	/* Deassert reset */
c4fab452	438	ret = reset_control_deassert(sun4ichip->rst);
a7fe9856 JS	439	if (ret) {
	440	dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
	441	ERR_PTR(ret));
	442	return ret;
	443	}
	444
5b090b43 JS	445	/*
	446	* We're keeping the bus clock on for the sake of simplicity.
	447	* Actually it only needs to be on for hardware register accesses.
	448	*/
c4fab452	449	ret = clk_prepare_enable(sun4ichip->bus_clk);
5b090b43 JS	450	if (ret) {
	451	dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
	452	ERR_PTR(ret));
	453	goto err_bus;
	454	}
	455
c4fab452 UKK	456	sun4ichip->chip.dev = &pdev->dev;
	457	sun4ichip->chip.ops = &sun4i_pwm_ops;
	458	sun4ichip->chip.npwm = sun4ichip->data->npwm;
09853ce7	459
c4fab452	460	spin_lock_init(&sun4ichip->ctrl_lock);
09853ce7	461
c4fab452	462	ret = pwmchip_add(&sun4ichip->chip);
09853ce7 AB	463	if (ret < 0) {
09853ce7 AB	464	dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
a7fe9856	465	goto err_pwm_add;
09853ce7 AB	466	}
09853ce7 AB	467
c4fab452	468	platform_set_drvdata(pdev, sun4ichip);
09853ce7	469
09853ce7	470	return 0;
a7fe9856 JS	471
a7fe9856 JS	472	err_pwm_add:
c4fab452	473	clk_disable_unprepare(sun4ichip->bus_clk);
5b090b43	474	err_bus:
c4fab452	475	reset_control_assert(sun4ichip->rst);
a7fe9856 JS	476
a7fe9856 JS	477	return ret;
09853ce7 AB	478	}
	479
	480	static int sun4i_pwm_remove(struct platform_device *pdev)
	481	{
c4fab452	482	struct sun4i_pwm_chip *sun4ichip = platform_get_drvdata(pdev);
a7fe9856	483
c4fab452	484	pwmchip_remove(&sun4ichip->chip);
a7fe9856	485
c4fab452 UKK	486	clk_disable_unprepare(sun4ichip->bus_clk);
c4fab452 UKK	487	reset_control_assert(sun4ichip->rst);
09853ce7	488
a7fe9856	489	return 0;
09853ce7 AB	490	}
	491
	492	static struct platform_driver sun4i_pwm_driver = {
	493	.driver = {
	494	.name = "sun4i-pwm",
	495	.of_match_table = sun4i_pwm_dt_ids,
	496	},
	497	.probe = sun4i_pwm_probe,
	498	.remove = sun4i_pwm_remove,
	499	};
	500	module_platform_driver(sun4i_pwm_driver);
	501
	502	MODULE_ALIAS("platform:sun4i-pwm");
	503	MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
	504	MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
	505	MODULE_LICENSE("GPL v2");