[linux-block.git] / drivers / pwm / pwm-sun4i.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Driver for Allwinner sun4i Pulse Width Modulation Controller
 *
 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
 *
 * Limitations:
 * - When outputing the source clock directly, the PWM logic will be bypassed
 *   and the currently running period is not guaranteed to be completed
 */

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/time.h>

#define PWM_CTRL_REG		0x0

#define PWM_CH_PRD_BASE		0x4
#define PWM_CH_PRD_OFFSET	0x4
#define PWM_CH_PRD(ch)		(PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))

#define PWMCH_OFFSET		15
#define PWM_PRESCAL_MASK	GENMASK(3, 0)
#define PWM_PRESCAL_OFF		0
#define PWM_EN			BIT(4)
#define PWM_ACT_STATE		BIT(5)
#define PWM_CLK_GATING		BIT(6)
#define PWM_MODE		BIT(7)
#define PWM_PULSE		BIT(8)
#define PWM_BYPASS		BIT(9)

#define PWM_RDY_BASE		28
#define PWM_RDY_OFFSET		1
#define PWM_RDY(ch)		BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))

#define PWM_PRD(prd)		(((prd) - 1) << 16)
#define PWM_PRD_MASK		GENMASK(15, 0)

#define PWM_DTY_MASK		GENMASK(15, 0)

#define PWM_REG_PRD(reg)	((((reg) >> 16) & PWM_PRD_MASK) + 1)
#define PWM_REG_DTY(reg)	((reg) & PWM_DTY_MASK)
#define PWM_REG_PRESCAL(reg, chan)	(((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)

#define BIT_CH(bit, chan)	((bit) << ((chan) * PWMCH_OFFSET))

static const u32 prescaler_table[] = {
	120,
	180,
	240,
	360,
	480,
	0,
	0,
	0,
	12000,
	24000,
	36000,
	48000,
	72000,
	0,
	0,
	0, /* Actually 1 but tested separately */
};

struct sun4i_pwm_data {
	bool has_prescaler_bypass;
	bool has_direct_mod_clk_output;
	unsigned int npwm;
};

struct sun4i_pwm_chip {
	struct clk *bus_clk;
	struct clk *clk;
	struct reset_control *rst;
	void __iomem *base;
	spinlock_t ctrl_lock;
	const struct sun4i_pwm_data *data;
};

static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
{
	return pwmchip_get_drvdata(chip);
}

static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *sun4ichip,
				  unsigned long offset)
{
	return readl(sun4ichip->base + offset);
}

static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *sun4ichip,
				    u32 val, unsigned long offset)
{
	writel(val, sun4ichip->base + offset);
}

static int sun4i_pwm_get_state(struct pwm_chip *chip,
			       struct pwm_device *pwm,
			       struct pwm_state *state)
{
	struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip);
	u64 clk_rate, tmp;
	u32 val;
	unsigned int prescaler;

	clk_rate = clk_get_rate(sun4ichip->clk);
	if (!clk_rate)
		return -EINVAL;

	val = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG);

	/*
	 * PWM chapter in H6 manual has a diagram which explains that if bypass
	 * bit is set, no other setting has any meaning. Even more, experiment
	 * proved that also enable bit is ignored in this case.
	 */
	if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
	    sun4ichip->data->has_direct_mod_clk_output) {
		state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
		state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
		state->polarity = PWM_POLARITY_NORMAL;
		state->enabled = true;
		return 0;
	}

	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
	    sun4ichip->data->has_prescaler_bypass)
		prescaler = 1;
	else
		prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];

	if (prescaler == 0)
		return -EINVAL;

	if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
		state->polarity = PWM_POLARITY_NORMAL;
	else
		state->polarity = PWM_POLARITY_INVERSED;

	if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
	    BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
		state->enabled = true;
	else
		state->enabled = false;

	val = sun4i_pwm_readl(sun4ichip, PWM_CH_PRD(pwm->hwpwm));

	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);

	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);

	return 0;
}

static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4ichip,
			       const struct pwm_state *state,
			       u32 *dty, u32 *prd, unsigned int *prsclr,
			       bool *bypass)
{
	u64 clk_rate, div = 0;
	unsigned int prescaler = 0;

	clk_rate = clk_get_rate(sun4ichip->clk);

	*bypass = sun4ichip->data->has_direct_mod_clk_output &&
		  state->enabled &&
		  (state->period * clk_rate >= NSEC_PER_SEC) &&
		  (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
		  (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);

	/* Skip calculation of other parameters if we bypass them */
	if (*bypass)
		return 0;

	if (sun4ichip->data->has_prescaler_bypass) {
		/* First, test without any prescaler when available */
		prescaler = PWM_PRESCAL_MASK;
		/*
		 * When not using any prescaler, the clock period in nanoseconds
		 * is not an integer so round it half up instead of
		 * truncating to get less surprising values.
		 */
		div = clk_rate * state->period + NSEC_PER_SEC / 2;
		do_div(div, NSEC_PER_SEC);
		if (div - 1 > PWM_PRD_MASK)
			prescaler = 0;
	}

	if (prescaler == 0) {
		/* Go up from the first divider */
		for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
			unsigned int pval = prescaler_table[prescaler];

			if (!pval)
				continue;

			div = clk_rate;
			do_div(div, pval);
			div = div * state->period;
			do_div(div, NSEC_PER_SEC);
			if (div - 1 <= PWM_PRD_MASK)
				break;
		}

		if (div - 1 > PWM_PRD_MASK)
			return -EINVAL;
	}

	*prd = div;
	div *= state->duty_cycle;
	do_div(div, state->period);
	*dty = div;
	*prsclr = prescaler;

	return 0;
}

static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   const struct pwm_state *state)
{
	struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip);
	struct pwm_state cstate;
	u32 ctrl, duty = 0, period = 0, val;
	int ret;
	unsigned int delay_us, prescaler = 0;
	bool bypass;

	pwm_get_state(pwm, &cstate);

	if (!cstate.enabled) {
		ret = clk_prepare_enable(sun4ichip->clk);
		if (ret) {
			dev_err(pwmchip_parent(chip), "failed to enable PWM clock\n");
			return ret;
		}
	}

	ret = sun4i_pwm_calculate(sun4ichip, state, &duty, &period, &prescaler,
				  &bypass);
	if (ret) {
		dev_err(pwmchip_parent(chip), "period exceeds the maximum value\n");
		if (!cstate.enabled)
			clk_disable_unprepare(sun4ichip->clk);
		return ret;
	}

	spin_lock(&sun4ichip->ctrl_lock);
	ctrl = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG);

	if (sun4ichip->data->has_direct_mod_clk_output) {
		if (bypass) {
			ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
			/* We can skip other parameter */
			sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
			spin_unlock(&sun4ichip->ctrl_lock);
			return 0;
		}

		ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
	}

	if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
		/* Prescaler changed, the clock has to be gated */
		ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
		sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);

		ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
		ctrl |= BIT_CH(prescaler, pwm->hwpwm);
	}

	val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
	sun4i_pwm_writel(sun4ichip, val, PWM_CH_PRD(pwm->hwpwm));

	if (state->polarity != PWM_POLARITY_NORMAL)
		ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
	else
		ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);

	ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);

	if (state->enabled)
		ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);

	sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);

	spin_unlock(&sun4ichip->ctrl_lock);

	if (state->enabled)
		return 0;

	/* We need a full period to elapse before disabling the channel. */
	delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC);
	if ((delay_us / 500) > MAX_UDELAY_MS)
		msleep(delay_us / 1000 + 1);
	else
		usleep_range(delay_us, delay_us * 2);

	spin_lock(&sun4ichip->ctrl_lock);
	ctrl = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG);
	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
	ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
	sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
	spin_unlock(&sun4ichip->ctrl_lock);

	clk_disable_unprepare(sun4ichip->clk);

	return 0;
}

static const struct pwm_ops sun4i_pwm_ops = {
	.apply = sun4i_pwm_apply,
	.get_state = sun4i_pwm_get_state,
};

static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
	.has_prescaler_bypass = false,
	.npwm = 2,
};

static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
	.has_prescaler_bypass = true,
	.npwm = 2,
};

static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
	.has_prescaler_bypass = true,
	.npwm = 1,
};

static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
	.has_prescaler_bypass = true,
	.has_direct_mod_clk_output = true,
	.npwm = 1,
};

static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
	.has_prescaler_bypass = true,
	.has_direct_mod_clk_output = true,
	.npwm = 2,
};

static const struct of_device_id sun4i_pwm_dt_ids[] = {
	{
		.compatible = "allwinner,sun4i-a10-pwm",
		.data = &sun4i_pwm_dual_nobypass,
	}, {
		.compatible = "allwinner,sun5i-a10s-pwm",
		.data = &sun4i_pwm_dual_bypass,
	}, {
		.compatible = "allwinner,sun5i-a13-pwm",
		.data = &sun4i_pwm_single_bypass,
	}, {
		.compatible = "allwinner,sun7i-a20-pwm",
		.data = &sun4i_pwm_dual_bypass,
	}, {
		.compatible = "allwinner,sun8i-h3-pwm",
		.data = &sun4i_pwm_single_bypass,
	}, {
		.compatible = "allwinner,sun50i-a64-pwm",
		.data = &sun50i_a64_pwm_data,
	}, {
		.compatible = "allwinner,sun50i-h6-pwm",
		.data = &sun50i_h6_pwm_data,
	}, {
		/* sentinel */
	},
};
MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);

static int sun4i_pwm_probe(struct platform_device *pdev)
{
	struct pwm_chip *chip;
	const struct sun4i_pwm_data *data;
	struct sun4i_pwm_chip *sun4ichip;
	int ret;

	data = of_device_get_match_data(&pdev->dev);
	if (!data)
		return -ENODEV;

	chip = devm_pwmchip_alloc(&pdev->dev, data->npwm, sizeof(*sun4ichip));
	if (IS_ERR(chip))
		return PTR_ERR(chip);
	sun4ichip = to_sun4i_pwm_chip(chip);

	sun4ichip->data = data;
	sun4ichip->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(sun4ichip->base))
		return PTR_ERR(sun4ichip->base);

	/*
	 * All hardware variants need a source clock that is divided and
	 * then feeds the counter that defines the output wave form. In the
	 * device tree this clock is either unnamed or called "mod".
	 * Some variants (e.g. H6) need another clock to access the
	 * hardware registers; this is called "bus".
	 * So we request "mod" first (and ignore the corner case that a
	 * parent provides a "mod" clock while the right one would be the
	 * unnamed one of the PWM device) and if this is not found we fall
	 * back to the first clock of the PWM.
	 */
	sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod");
	if (IS_ERR(sun4ichip->clk))
		return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
				     "get mod clock failed\n");

	if (!sun4ichip->clk) {
		sun4ichip->clk = devm_clk_get(&pdev->dev, NULL);
		if (IS_ERR(sun4ichip->clk))
			return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
					     "get unnamed clock failed\n");
	}

	sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
	if (IS_ERR(sun4ichip->bus_clk))
		return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk),
				     "get bus clock failed\n");

	sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
	if (IS_ERR(sun4ichip->rst))
		return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst),
				     "get reset failed\n");

	/* Deassert reset */
	ret = reset_control_deassert(sun4ichip->rst);
	if (ret) {
		dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
			ERR_PTR(ret));
		return ret;
	}

	/*
	 * We're keeping the bus clock on for the sake of simplicity.
	 * Actually it only needs to be on for hardware register accesses.
	 */
	ret = clk_prepare_enable(sun4ichip->bus_clk);
	if (ret) {
		dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
			ERR_PTR(ret));
		goto err_bus;
	}

	chip->ops = &sun4i_pwm_ops;

	spin_lock_init(&sun4ichip->ctrl_lock);

	ret = pwmchip_add(chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
		goto err_pwm_add;
	}

	platform_set_drvdata(pdev, chip);

	return 0;

err_pwm_add:
	clk_disable_unprepare(sun4ichip->bus_clk);
err_bus:
	reset_control_assert(sun4ichip->rst);

	return ret;
}

static void sun4i_pwm_remove(struct platform_device *pdev)
{
	struct pwm_chip *chip = platform_get_drvdata(pdev);
	struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip);

	pwmchip_remove(chip);

	clk_disable_unprepare(sun4ichip->bus_clk);
	reset_control_assert(sun4ichip->rst);
}

static struct platform_driver sun4i_pwm_driver = {
	.driver = {
		.name = "sun4i-pwm",
		.of_match_table = sun4i_pwm_dt_ids,
	},
	.probe = sun4i_pwm_probe,
	.remove_new = sun4i_pwm_remove,
};
module_platform_driver(sun4i_pwm_driver);

MODULE_ALIAS("platform:sun4i-pwm");
MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
f50a7f3d	1	// SPDX-License-Identifier: GPL-2.0-only
09853ce7 AB	2	/*
	3	* Driver for Allwinner sun4i Pulse Width Modulation Controller
	4	*
	5	* Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
9f28e95b JS	6	*
	7	* Limitations:
	8	* - When outputing the source clock directly, the PWM logic will be bypassed
	9	* and the currently running period is not guaranteed to be completed
09853ce7 AB	10	*/
	11
	12	#include <linux/bitops.h>
	13	#include <linux/clk.h>
c32c5c50	14	#include <linux/delay.h>
09853ce7 AB	15	#include <linux/err.h>
09853ce7 AB	16	#include <linux/io.h>
c32c5c50	17	#include <linux/jiffies.h>
09853ce7 AB	18	#include <linux/module.h>
09853ce7 AB	19	#include <linux/of.h>
09853ce7 AB	20	#include <linux/platform_device.h>
09853ce7 AB	21	#include <linux/pwm.h>
a7fe9856	22	#include <linux/reset.h>
09853ce7 AB	23	#include <linux/slab.h>
	24	#include <linux/spinlock.h>
	25	#include <linux/time.h>
	26
	27	#define PWM_CTRL_REG 0x0
	28
	29	#define PWM_CH_PRD_BASE 0x4
	30	#define PWM_CH_PRD_OFFSET 0x4
	31	#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
	32
	33	#define PWMCH_OFFSET 15
	34	#define PWM_PRESCAL_MASK GENMASK(3, 0)
	35	#define PWM_PRESCAL_OFF 0
	36	#define PWM_EN BIT(4)
	37	#define PWM_ACT_STATE BIT(5)
	38	#define PWM_CLK_GATING BIT(6)
	39	#define PWM_MODE BIT(7)
	40	#define PWM_PULSE BIT(8)
	41	#define PWM_BYPASS BIT(9)
	42
	43	#define PWM_RDY_BASE 28
	44	#define PWM_RDY_OFFSET 1
	45	#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
	46
	47	#define PWM_PRD(prd) (((prd) - 1) << 16)
	48	#define PWM_PRD_MASK GENMASK(15, 0)
	49
	50	#define PWM_DTY_MASK GENMASK(15, 0)
	51
93e0dfb2 AB	52	#define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
	53	#define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
	54	#define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
	55
09853ce7 AB	56	#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
	57
	58	static const u32 prescaler_table[] = {
	59	120,
	60	180,
	61	240,
	62	360,
	63	480,
	64	0,
	65	0,
	66	0,
	67	12000,
	68	24000,
	69	36000,
	70	48000,
	71	72000,
	72	0,
	73	0,
	74	0, /* Actually 1 but tested separately */
	75	};
	76
	77	struct sun4i_pwm_data {
	78	bool has_prescaler_bypass;
9f28e95b	79	bool has_direct_mod_clk_output;
f6649f7a	80	unsigned int npwm;
09853ce7 AB	81	};
	82
	83	struct sun4i_pwm_chip {
5b090b43	84	struct clk *bus_clk;
09853ce7	85	struct clk *clk;
a7fe9856	86	struct reset_control *rst;
09853ce7 AB	87	void __iomem *base;
	88	spinlock_t ctrl_lock;
	89	const struct sun4i_pwm_data *data;
	90	};
	91
	92	static inline struct sun4i_pwm_chip to_sun4i_pwm_chip(struct pwm_chip chip)
	93	{
362e3f88	94	return pwmchip_get_drvdata(chip);
09853ce7 AB	95	}
09853ce7 AB	96
2eb3ff5f	97	static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *sun4ichip,
09853ce7 AB	98	unsigned long offset)
09853ce7 AB	99	{
2eb3ff5f	100	return readl(sun4ichip->base + offset);
09853ce7 AB	101	}
09853ce7 AB	102
2eb3ff5f	103	static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *sun4ichip,
09853ce7 AB	104	u32 val, unsigned long offset)
09853ce7 AB	105	{
2eb3ff5f	106	writel(val, sun4ichip->base + offset);
09853ce7 AB	107	}
09853ce7 AB	108
6c452cff UKK	109	static int sun4i_pwm_get_state(struct pwm_chip *chip,
	110	struct pwm_device *pwm,
	111	struct pwm_state *state)
93e0dfb2	112	{
2eb3ff5f	113	struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip);
93e0dfb2 AB	114	u64 clk_rate, tmp;
	115	u32 val;
	116	unsigned int prescaler;
	117
2eb3ff5f	118	clk_rate = clk_get_rate(sun4ichip->clk);
a08b318a AP	119	if (!clk_rate)
a08b318a AP	120	return -EINVAL;
93e0dfb2	121
2eb3ff5f	122	val = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG);
93e0dfb2	123
9f28e95b JS	124	/*
	125	* PWM chapter in H6 manual has a diagram which explains that if bypass
	126	* bit is set, no other setting has any meaning. Even more, experiment
	127	* proved that also enable bit is ignored in this case.
	128	*/
	129	if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
2eb3ff5f	130	sun4ichip->data->has_direct_mod_clk_output) {
9f28e95b JS	131	state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
	132	state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
	133	state->polarity = PWM_POLARITY_NORMAL;
	134	state->enabled = true;
6c452cff	135	return 0;
9f28e95b JS	136	}
9f28e95b JS	137
989ae7a5	138	if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
2eb3ff5f	139	sun4ichip->data->has_prescaler_bypass)
93e0dfb2 AB	140	prescaler = 1;
	141	else
	142	prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
	143
	144	if (prescaler == 0)
a08b318a	145	return -EINVAL;
93e0dfb2 AB	146
	147	if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
	148	state->polarity = PWM_POLARITY_NORMAL;
	149	else
	150	state->polarity = PWM_POLARITY_INVERSED;
	151
989ae7a5 AB	152	if ((val & BIT_CH(PWM_CLK_GATING \| PWM_EN, pwm->hwpwm)) ==
989ae7a5 AB	153	BIT_CH(PWM_CLK_GATING \| PWM_EN, pwm->hwpwm))
93e0dfb2 AB	154	state->enabled = true;
	155	else
	156	state->enabled = false;
	157
2eb3ff5f	158	val = sun4i_pwm_readl(sun4ichip, PWM_CH_PRD(pwm->hwpwm));
93e0dfb2	159
50cc7e3e	160	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
93e0dfb2 AB	161	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
93e0dfb2 AB	162
50cc7e3e	163	tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
93e0dfb2	164	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
6c452cff UKK	165
6c452cff UKK	166	return 0;
93e0dfb2 AB	167	}
93e0dfb2 AB	168
2eb3ff5f	169	static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4ichip,
71523d18	170	const struct pwm_state *state,
9f28e95b JS	171	u32 dty, u32 prd, unsigned int *prsclr,
9f28e95b JS	172	bool *bypass)
c32c5c50 AB	173	{
c32c5c50 AB	174	u64 clk_rate, div = 0;
f6003f94	175	unsigned int prescaler = 0;
c32c5c50	176
2eb3ff5f	177	clk_rate = clk_get_rate(sun4ichip->clk);
c32c5c50	178
2eb3ff5f	179	*bypass = sun4ichip->data->has_direct_mod_clk_output &&
9f28e95b JS	180	state->enabled &&
	181	(state->period * clk_rate >= NSEC_PER_SEC) &&
	182	(state->period * clk_rate < 2 * NSEC_PER_SEC) &&
	183	(state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
	184
	185	/* Skip calculation of other parameters if we bypass them */
	186	if (*bypass)
	187	return 0;
	188
2eb3ff5f	189	if (sun4ichip->data->has_prescaler_bypass) {
c32c5c50 AB	190	/* First, test without any prescaler when available */
c32c5c50 AB	191	prescaler = PWM_PRESCAL_MASK;
c32c5c50 AB	192	/*
	193	* When not using any prescaler, the clock period in nanoseconds
	194	* is not an integer so round it half up instead of
	195	* truncating to get less surprising values.
	196	*/
	197	div = clk_rate * state->period + NSEC_PER_SEC / 2;
	198	do_div(div, NSEC_PER_SEC);
	199	if (div - 1 > PWM_PRD_MASK)
	200	prescaler = 0;
	201	}
	202
	203	if (prescaler == 0) {
	204	/* Go up from the first divider */
	205	for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
f6003f94 UKK	206	unsigned int pval = prescaler_table[prescaler];
	207
	208	if (!pval)
c32c5c50	209	continue;
f6003f94	210
c32c5c50 AB	211	div = clk_rate;
	212	do_div(div, pval);
	213	div = div * state->period;
	214	do_div(div, NSEC_PER_SEC);
	215	if (div - 1 <= PWM_PRD_MASK)
	216	break;
	217	}
	218
	219	if (div - 1 > PWM_PRD_MASK)
	220	return -EINVAL;
	221	}
	222
	223	*prd = div;
	224	div *= state->duty_cycle;
	225	do_div(div, state->period);
	226	*dty = div;
	227	*prsclr = prescaler;
	228
c32c5c50 AB	229	return 0;
	230	}
	231
	232	static int sun4i_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	233	const struct pwm_state *state)
c32c5c50	234	{
2eb3ff5f	235	struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip);
c32c5c50	236	struct pwm_state cstate;
413c2a11	237	u32 ctrl, duty = 0, period = 0, val;
c32c5c50	238	int ret;
413c2a11	239	unsigned int delay_us, prescaler = 0;
9f28e95b	240	bool bypass;
c32c5c50 AB	241
	242	pwm_get_state(pwm, &cstate);
	243
	244	if (!cstate.enabled) {
2eb3ff5f	245	ret = clk_prepare_enable(sun4ichip->clk);
c32c5c50	246	if (ret) {
d6ada1d4	247	dev_err(pwmchip_parent(chip), "failed to enable PWM clock\n");
c32c5c50 AB	248	return ret;
	249	}
	250	}
	251
2eb3ff5f	252	ret = sun4i_pwm_calculate(sun4ichip, state, &duty, &period, &prescaler,
9f28e95b	253	&bypass);
fa4d8178	254	if (ret) {
d6ada1d4	255	dev_err(pwmchip_parent(chip), "period exceeds the maximum value\n");
fa4d8178	256	if (!cstate.enabled)
2eb3ff5f	257	clk_disable_unprepare(sun4ichip->clk);
fa4d8178 CP	258	return ret;
fa4d8178 CP	259	}
c32c5c50	260
2eb3ff5f UKK	261	spin_lock(&sun4ichip->ctrl_lock);
2eb3ff5f UKK	262	ctrl = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG);
3e954d96	263
2eb3ff5f	264	if (sun4ichip->data->has_direct_mod_clk_output) {
9f28e95b JS	265	if (bypass) {
	266	ctrl \|= BIT_CH(PWM_BYPASS, pwm->hwpwm);
	267	/* We can skip other parameter */
2eb3ff5f UKK	268	sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
2eb3ff5f UKK	269	spin_unlock(&sun4ichip->ctrl_lock);
9f28e95b JS	270	return 0;
	271	}
	272
	273	ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm);
	274	}
	275
fa4d8178 CP	276	if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
	277	/* Prescaler changed, the clock has to be gated */
	278	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
2eb3ff5f	279	sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
c32c5c50	280
fa4d8178 CP	281	ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
fa4d8178 CP	282	ctrl \|= BIT_CH(prescaler, pwm->hwpwm);
c32c5c50 AB	283	}
c32c5c50 AB	284
fa4d8178	285	val = (duty & PWM_DTY_MASK) \| PWM_PRD(period);
2eb3ff5f	286	sun4i_pwm_writel(sun4ichip, val, PWM_CH_PRD(pwm->hwpwm));
fa4d8178	287
c32c5c50 AB	288	if (state->polarity != PWM_POLARITY_NORMAL)
	289	ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
	290	else
	291	ctrl \|= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
	292
	293	ctrl \|= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
fa4d8178	294
6eefb79d	295	if (state->enabled)
c32c5c50	296	ctrl \|= BIT_CH(PWM_EN, pwm->hwpwm);
c32c5c50	297
2eb3ff5f	298	sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
c32c5c50	299
2eb3ff5f	300	spin_unlock(&sun4ichip->ctrl_lock);
c32c5c50 AB	301
	302	if (state->enabled)
	303	return 0;
	304
c32c5c50	305	/* We need a full period to elapse before disabling the channel. */
8246b478	306	delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC);
ba3e5037 MK	307	if ((delay_us / 500) > MAX_UDELAY_MS)
	308	msleep(delay_us / 1000 + 1);
	309	else
	310	usleep_range(delay_us, delay_us * 2);
c32c5c50	311
2eb3ff5f UKK	312	spin_lock(&sun4ichip->ctrl_lock);
2eb3ff5f UKK	313	ctrl = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG);
c32c5c50 AB	314	ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
c32c5c50 AB	315	ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
2eb3ff5f UKK	316	sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
2eb3ff5f UKK	317	spin_unlock(&sun4ichip->ctrl_lock);
c32c5c50	318
2eb3ff5f	319	clk_disable_unprepare(sun4ichip->clk);
c32c5c50 AB	320
	321	return 0;
	322	}
	323
09853ce7	324	static const struct pwm_ops sun4i_pwm_ops = {
c32c5c50	325	.apply = sun4i_pwm_apply,
93e0dfb2	326	.get_state = sun4i_pwm_get_state,
09853ce7 AB	327	};
09853ce7 AB	328
7b4c7c56	329	static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
09853ce7	330	.has_prescaler_bypass = false,
f6649f7a HG	331	.npwm = 2,
	332	};
	333
7b4c7c56	334	static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
f6649f7a	335	.has_prescaler_bypass = true,
f6649f7a HG	336	.npwm = 2,
	337	};
	338
7b4c7c56	339	static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
42ddcf4f	340	.has_prescaler_bypass = true,
42ddcf4f MK	341	.npwm = 1,
	342	};
	343
856c45d8 PV	344	static const struct sun4i_pwm_data sun50i_a64_pwm_data = {
	345	.has_prescaler_bypass = true,
	346	.has_direct_mod_clk_output = true,
	347	.npwm = 1,
	348	};
	349
fdd2c12e JS	350	static const struct sun4i_pwm_data sun50i_h6_pwm_data = {
	351	.has_prescaler_bypass = true,
	352	.has_direct_mod_clk_output = true,
	353	.npwm = 2,
	354	};
	355
09853ce7 AB	356	static const struct of_device_id sun4i_pwm_dt_ids[] = {
	357	{
	358	.compatible = "allwinner,sun4i-a10-pwm",
7b4c7c56	359	.data = &sun4i_pwm_dual_nobypass,
f6649f7a HG	360	}, {
f6649f7a HG	361	.compatible = "allwinner,sun5i-a10s-pwm",
7b4c7c56	362	.data = &sun4i_pwm_dual_bypass,
f6649f7a HG	363	}, {
f6649f7a HG	364	.compatible = "allwinner,sun5i-a13-pwm",
7b4c7c56	365	.data = &sun4i_pwm_single_bypass,
09853ce7 AB	366	}, {
09853ce7 AB	367	.compatible = "allwinner,sun7i-a20-pwm",
7b4c7c56	368	.data = &sun4i_pwm_dual_bypass,
42ddcf4f MK	369	}, {
42ddcf4f MK	370	.compatible = "allwinner,sun8i-h3-pwm",
7b4c7c56	371	.data = &sun4i_pwm_single_bypass,
856c45d8 PV	372	}, {
	373	.compatible = "allwinner,sun50i-a64-pwm",
	374	.data = &sun50i_a64_pwm_data,
fdd2c12e JS	375	}, {
	376	.compatible = "allwinner,sun50i-h6-pwm",
	377	.data = &sun50i_h6_pwm_data,
09853ce7 AB	378	}, {
	379	/* sentinel */
	380	},
	381	};
	382	MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
	383
	384	static int sun4i_pwm_probe(struct platform_device *pdev)
	385	{
2d7224f4	386	struct pwm_chip *chip;
362e3f88	387	const struct sun4i_pwm_data *data;
c4fab452	388	struct sun4i_pwm_chip *sun4ichip;
93e0dfb2	389	int ret;
09853ce7	390
362e3f88 UKK	391	data = of_device_get_match_data(&pdev->dev);
362e3f88 UKK	392	if (!data)
df4f6e8c CL	393	return -ENODEV;
df4f6e8c CL	394
362e3f88 UKK	395	chip = devm_pwmchip_alloc(&pdev->dev, data->npwm, sizeof(*sun4ichip));
	396	if (IS_ERR(chip))
	397	return PTR_ERR(chip);
	398	sun4ichip = to_sun4i_pwm_chip(chip);
	399
	400	sun4ichip->data = data;
c4fab452 UKK	401	sun4ichip->base = devm_platform_ioremap_resource(pdev, 0);
	402	if (IS_ERR(sun4ichip->base))
	403	return PTR_ERR(sun4ichip->base);
09853ce7	404
b8d74644 CP	405	/*
	406	* All hardware variants need a source clock that is divided and
	407	* then feeds the counter that defines the output wave form. In the
	408	* device tree this clock is either unnamed or called "mod".
	409	* Some variants (e.g. H6) need another clock to access the
	410	* hardware registers; this is called "bus".
	411	* So we request "mod" first (and ignore the corner case that a
	412	* parent provides a "mod" clock while the right one would be the
	413	* unnamed one of the PWM device) and if this is not found we fall
	414	* back to the first clock of the PWM.
	415	*/
c4fab452 UKK	416	sun4ichip->clk = devm_clk_get_optional(&pdev->dev, "mod");
	417	if (IS_ERR(sun4ichip->clk))
	418	return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
5327f34b	419	"get mod clock failed\n");
b8d74644	420
c4fab452 UKK	421	if (!sun4ichip->clk) {
	422	sun4ichip->clk = devm_clk_get(&pdev->dev, NULL);
	423	if (IS_ERR(sun4ichip->clk))
	424	return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->clk),
5327f34b	425	"get unnamed clock failed\n");
b8d74644	426	}
09853ce7	427
c4fab452 UKK	428	sun4ichip->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
	429	if (IS_ERR(sun4ichip->bus_clk))
	430	return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->bus_clk),
5327f34b	431	"get bus clock failed\n");
5b090b43	432
c4fab452 UKK	433	sun4ichip->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
	434	if (IS_ERR(sun4ichip->rst))
	435	return dev_err_probe(&pdev->dev, PTR_ERR(sun4ichip->rst),
5327f34b	436	"get reset failed\n");
a7fe9856 JS	437
a7fe9856 JS	438	/* Deassert reset */
c4fab452	439	ret = reset_control_deassert(sun4ichip->rst);
a7fe9856 JS	440	if (ret) {
	441	dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
	442	ERR_PTR(ret));
	443	return ret;
	444	}
	445
5b090b43 JS	446	/*
	447	* We're keeping the bus clock on for the sake of simplicity.
	448	* Actually it only needs to be on for hardware register accesses.
	449	*/
c4fab452	450	ret = clk_prepare_enable(sun4ichip->bus_clk);
5b090b43 JS	451	if (ret) {
	452	dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
	453	ERR_PTR(ret));
	454	goto err_bus;
	455	}
	456
2d7224f4	457	chip->ops = &sun4i_pwm_ops;
09853ce7	458
c4fab452	459	spin_lock_init(&sun4ichip->ctrl_lock);
09853ce7	460
2d7224f4	461	ret = pwmchip_add(chip);
09853ce7 AB	462	if (ret < 0) {
09853ce7 AB	463	dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
a7fe9856	464	goto err_pwm_add;
09853ce7 AB	465	}
09853ce7 AB	466
2d7224f4	467	platform_set_drvdata(pdev, chip);
09853ce7	468
09853ce7	469	return 0;
a7fe9856 JS	470
a7fe9856 JS	471	err_pwm_add:
c4fab452	472	clk_disable_unprepare(sun4ichip->bus_clk);
5b090b43	473	err_bus:
c4fab452	474	reset_control_assert(sun4ichip->rst);
a7fe9856 JS	475
a7fe9856 JS	476	return ret;
09853ce7 AB	477	}
09853ce7 AB	478
0bda6b01	479	static void sun4i_pwm_remove(struct platform_device *pdev)
09853ce7	480	{
2d7224f4 UKK	481	struct pwm_chip *chip = platform_get_drvdata(pdev);
2d7224f4 UKK	482	struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip);
a7fe9856	483
2d7224f4	484	pwmchip_remove(chip);
a7fe9856	485
c4fab452 UKK	486	clk_disable_unprepare(sun4ichip->bus_clk);
c4fab452 UKK	487	reset_control_assert(sun4ichip->rst);
09853ce7 AB	488	}
	489
	490	static struct platform_driver sun4i_pwm_driver = {
	491	.driver = {
	492	.name = "sun4i-pwm",
	493	.of_match_table = sun4i_pwm_dt_ids,
	494	},
	495	.probe = sun4i_pwm_probe,
0bda6b01	496	.remove_new = sun4i_pwm_remove,
09853ce7 AB	497	};
	498	module_platform_driver(sun4i_pwm_driver);
	499
	500	MODULE_ALIAS("platform:sun4i-pwm");
	501	MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
	502	MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
	503	MODULE_LICENSE("GPL v2");