Commit | Line | Data |
---|---|---|
09853ce7 AB |
1 | /* |
2 | * Driver for Allwinner sun4i Pulse Width Modulation Controller | |
3 | * | |
4 | * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> | |
5 | * | |
6 | * Licensed under GPLv2. | |
7 | */ | |
8 | ||
9 | #include <linux/bitops.h> | |
10 | #include <linux/clk.h> | |
c32c5c50 | 11 | #include <linux/delay.h> |
09853ce7 AB |
12 | #include <linux/err.h> |
13 | #include <linux/io.h> | |
c32c5c50 | 14 | #include <linux/jiffies.h> |
09853ce7 AB |
15 | #include <linux/module.h> |
16 | #include <linux/of.h> | |
17 | #include <linux/of_device.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/pwm.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/time.h> | |
23 | ||
24 | #define PWM_CTRL_REG 0x0 | |
25 | ||
26 | #define PWM_CH_PRD_BASE 0x4 | |
27 | #define PWM_CH_PRD_OFFSET 0x4 | |
28 | #define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch)) | |
29 | ||
30 | #define PWMCH_OFFSET 15 | |
31 | #define PWM_PRESCAL_MASK GENMASK(3, 0) | |
32 | #define PWM_PRESCAL_OFF 0 | |
33 | #define PWM_EN BIT(4) | |
34 | #define PWM_ACT_STATE BIT(5) | |
35 | #define PWM_CLK_GATING BIT(6) | |
36 | #define PWM_MODE BIT(7) | |
37 | #define PWM_PULSE BIT(8) | |
38 | #define PWM_BYPASS BIT(9) | |
39 | ||
40 | #define PWM_RDY_BASE 28 | |
41 | #define PWM_RDY_OFFSET 1 | |
42 | #define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch)) | |
43 | ||
44 | #define PWM_PRD(prd) (((prd) - 1) << 16) | |
45 | #define PWM_PRD_MASK GENMASK(15, 0) | |
46 | ||
47 | #define PWM_DTY_MASK GENMASK(15, 0) | |
48 | ||
93e0dfb2 AB |
49 | #define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1) |
50 | #define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK) | |
51 | #define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK) | |
52 | ||
09853ce7 AB |
53 | #define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET)) |
54 | ||
55 | static const u32 prescaler_table[] = { | |
56 | 120, | |
57 | 180, | |
58 | 240, | |
59 | 360, | |
60 | 480, | |
61 | 0, | |
62 | 0, | |
63 | 0, | |
64 | 12000, | |
65 | 24000, | |
66 | 36000, | |
67 | 48000, | |
68 | 72000, | |
69 | 0, | |
70 | 0, | |
71 | 0, /* Actually 1 but tested separately */ | |
72 | }; | |
73 | ||
74 | struct sun4i_pwm_data { | |
75 | bool has_prescaler_bypass; | |
76 | bool has_rdy; | |
f6649f7a | 77 | unsigned int npwm; |
09853ce7 AB |
78 | }; |
79 | ||
80 | struct sun4i_pwm_chip { | |
81 | struct pwm_chip chip; | |
82 | struct clk *clk; | |
83 | void __iomem *base; | |
84 | spinlock_t ctrl_lock; | |
85 | const struct sun4i_pwm_data *data; | |
c32c5c50 AB |
86 | unsigned long next_period[2]; |
87 | bool needs_delay[2]; | |
09853ce7 AB |
88 | }; |
89 | ||
90 | static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip) | |
91 | { | |
92 | return container_of(chip, struct sun4i_pwm_chip, chip); | |
93 | } | |
94 | ||
95 | static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip, | |
96 | unsigned long offset) | |
97 | { | |
98 | return readl(chip->base + offset); | |
99 | } | |
100 | ||
101 | static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip, | |
102 | u32 val, unsigned long offset) | |
103 | { | |
104 | writel(val, chip->base + offset); | |
105 | } | |
106 | ||
93e0dfb2 AB |
107 | static void sun4i_pwm_get_state(struct pwm_chip *chip, |
108 | struct pwm_device *pwm, | |
109 | struct pwm_state *state) | |
110 | { | |
111 | struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); | |
112 | u64 clk_rate, tmp; | |
113 | u32 val; | |
114 | unsigned int prescaler; | |
115 | ||
116 | clk_rate = clk_get_rate(sun4i_pwm->clk); | |
117 | ||
118 | val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); | |
119 | ||
120 | if ((val == PWM_PRESCAL_MASK) && sun4i_pwm->data->has_prescaler_bypass) | |
121 | prescaler = 1; | |
122 | else | |
123 | prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)]; | |
124 | ||
125 | if (prescaler == 0) | |
126 | return; | |
127 | ||
128 | if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm)) | |
129 | state->polarity = PWM_POLARITY_NORMAL; | |
130 | else | |
131 | state->polarity = PWM_POLARITY_INVERSED; | |
132 | ||
133 | if (val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) | |
134 | state->enabled = true; | |
135 | else | |
136 | state->enabled = false; | |
137 | ||
138 | val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm)); | |
139 | ||
140 | tmp = prescaler * NSEC_PER_SEC * PWM_REG_DTY(val); | |
141 | state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); | |
142 | ||
143 | tmp = prescaler * NSEC_PER_SEC * PWM_REG_PRD(val); | |
144 | state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); | |
145 | } | |
146 | ||
c32c5c50 AB |
147 | static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm, |
148 | struct pwm_state *state, | |
149 | u32 *dty, u32 *prd, unsigned int *prsclr) | |
150 | { | |
151 | u64 clk_rate, div = 0; | |
152 | unsigned int pval, prescaler = 0; | |
153 | ||
154 | clk_rate = clk_get_rate(sun4i_pwm->clk); | |
155 | ||
156 | if (sun4i_pwm->data->has_prescaler_bypass) { | |
157 | /* First, test without any prescaler when available */ | |
158 | prescaler = PWM_PRESCAL_MASK; | |
159 | pval = 1; | |
160 | /* | |
161 | * When not using any prescaler, the clock period in nanoseconds | |
162 | * is not an integer so round it half up instead of | |
163 | * truncating to get less surprising values. | |
164 | */ | |
165 | div = clk_rate * state->period + NSEC_PER_SEC / 2; | |
166 | do_div(div, NSEC_PER_SEC); | |
167 | if (div - 1 > PWM_PRD_MASK) | |
168 | prescaler = 0; | |
169 | } | |
170 | ||
171 | if (prescaler == 0) { | |
172 | /* Go up from the first divider */ | |
173 | for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) { | |
174 | if (!prescaler_table[prescaler]) | |
175 | continue; | |
176 | pval = prescaler_table[prescaler]; | |
177 | div = clk_rate; | |
178 | do_div(div, pval); | |
179 | div = div * state->period; | |
180 | do_div(div, NSEC_PER_SEC); | |
181 | if (div - 1 <= PWM_PRD_MASK) | |
182 | break; | |
183 | } | |
184 | ||
185 | if (div - 1 > PWM_PRD_MASK) | |
186 | return -EINVAL; | |
187 | } | |
188 | ||
189 | *prd = div; | |
190 | div *= state->duty_cycle; | |
191 | do_div(div, state->period); | |
192 | *dty = div; | |
193 | *prsclr = prescaler; | |
194 | ||
195 | div = (u64)pval * NSEC_PER_SEC * *prd; | |
196 | state->period = DIV_ROUND_CLOSEST_ULL(div, clk_rate); | |
197 | ||
198 | div = (u64)pval * NSEC_PER_SEC * *dty; | |
199 | state->duty_cycle = DIV_ROUND_CLOSEST_ULL(div, clk_rate); | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, | |
205 | struct pwm_state *state) | |
206 | { | |
207 | struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); | |
208 | struct pwm_state cstate; | |
209 | u32 ctrl; | |
210 | int ret; | |
211 | unsigned int delay_us; | |
212 | unsigned long now; | |
213 | ||
214 | pwm_get_state(pwm, &cstate); | |
215 | ||
216 | if (!cstate.enabled) { | |
217 | ret = clk_prepare_enable(sun4i_pwm->clk); | |
218 | if (ret) { | |
219 | dev_err(chip->dev, "failed to enable PWM clock\n"); | |
220 | return ret; | |
221 | } | |
222 | } | |
223 | ||
224 | spin_lock(&sun4i_pwm->ctrl_lock); | |
225 | ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); | |
226 | ||
227 | if ((cstate.period != state->period) || | |
228 | (cstate.duty_cycle != state->duty_cycle)) { | |
229 | u32 period, duty, val; | |
230 | unsigned int prescaler; | |
231 | ||
232 | ret = sun4i_pwm_calculate(sun4i_pwm, state, | |
233 | &duty, &period, &prescaler); | |
234 | if (ret) { | |
235 | dev_err(chip->dev, "period exceeds the maximum value\n"); | |
236 | spin_unlock(&sun4i_pwm->ctrl_lock); | |
237 | if (!cstate.enabled) | |
238 | clk_disable_unprepare(sun4i_pwm->clk); | |
239 | return ret; | |
240 | } | |
241 | ||
242 | if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { | |
243 | /* Prescaler changed, the clock has to be gated */ | |
244 | ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); | |
245 | sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); | |
246 | ||
247 | ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); | |
248 | ctrl |= BIT_CH(prescaler, pwm->hwpwm); | |
249 | } | |
250 | ||
251 | val = (duty & PWM_DTY_MASK) | PWM_PRD(period); | |
252 | sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); | |
253 | sun4i_pwm->next_period[pwm->hwpwm] = jiffies + | |
254 | usecs_to_jiffies(cstate.period / 1000 + 1); | |
255 | sun4i_pwm->needs_delay[pwm->hwpwm] = true; | |
256 | } | |
257 | ||
258 | if (state->polarity != PWM_POLARITY_NORMAL) | |
259 | ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); | |
260 | else | |
261 | ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); | |
262 | ||
263 | ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); | |
264 | if (state->enabled) { | |
265 | ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); | |
266 | } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) { | |
267 | ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm); | |
268 | ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); | |
269 | } | |
270 | ||
271 | sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); | |
272 | ||
273 | spin_unlock(&sun4i_pwm->ctrl_lock); | |
274 | ||
275 | if (state->enabled) | |
276 | return 0; | |
277 | ||
278 | if (!sun4i_pwm->needs_delay[pwm->hwpwm]) { | |
279 | clk_disable_unprepare(sun4i_pwm->clk); | |
280 | return 0; | |
281 | } | |
282 | ||
283 | /* We need a full period to elapse before disabling the channel. */ | |
284 | now = jiffies; | |
285 | if (sun4i_pwm->needs_delay[pwm->hwpwm] && | |
286 | time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) { | |
287 | delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] - | |
288 | now); | |
289 | if ((delay_us / 500) > MAX_UDELAY_MS) | |
290 | msleep(delay_us / 1000 + 1); | |
291 | else | |
292 | usleep_range(delay_us, delay_us * 2); | |
293 | } | |
294 | sun4i_pwm->needs_delay[pwm->hwpwm] = false; | |
295 | ||
296 | spin_lock(&sun4i_pwm->ctrl_lock); | |
297 | ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); | |
298 | ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); | |
299 | ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm); | |
300 | sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); | |
301 | spin_unlock(&sun4i_pwm->ctrl_lock); | |
302 | ||
303 | clk_disable_unprepare(sun4i_pwm->clk); | |
304 | ||
305 | return 0; | |
306 | } | |
307 | ||
09853ce7 | 308 | static const struct pwm_ops sun4i_pwm_ops = { |
c32c5c50 | 309 | .apply = sun4i_pwm_apply, |
93e0dfb2 | 310 | .get_state = sun4i_pwm_get_state, |
09853ce7 AB |
311 | .owner = THIS_MODULE, |
312 | }; | |
313 | ||
314 | static const struct sun4i_pwm_data sun4i_pwm_data_a10 = { | |
315 | .has_prescaler_bypass = false, | |
316 | .has_rdy = false, | |
f6649f7a HG |
317 | .npwm = 2, |
318 | }; | |
319 | ||
320 | static const struct sun4i_pwm_data sun4i_pwm_data_a10s = { | |
321 | .has_prescaler_bypass = true, | |
322 | .has_rdy = true, | |
323 | .npwm = 2, | |
324 | }; | |
325 | ||
326 | static const struct sun4i_pwm_data sun4i_pwm_data_a13 = { | |
327 | .has_prescaler_bypass = true, | |
328 | .has_rdy = true, | |
329 | .npwm = 1, | |
09853ce7 AB |
330 | }; |
331 | ||
332 | static const struct sun4i_pwm_data sun4i_pwm_data_a20 = { | |
333 | .has_prescaler_bypass = true, | |
334 | .has_rdy = true, | |
f6649f7a | 335 | .npwm = 2, |
09853ce7 AB |
336 | }; |
337 | ||
42ddcf4f MK |
338 | static const struct sun4i_pwm_data sun4i_pwm_data_h3 = { |
339 | .has_prescaler_bypass = true, | |
340 | .has_rdy = true, | |
341 | .npwm = 1, | |
342 | }; | |
343 | ||
09853ce7 AB |
344 | static const struct of_device_id sun4i_pwm_dt_ids[] = { |
345 | { | |
346 | .compatible = "allwinner,sun4i-a10-pwm", | |
347 | .data = &sun4i_pwm_data_a10, | |
f6649f7a HG |
348 | }, { |
349 | .compatible = "allwinner,sun5i-a10s-pwm", | |
350 | .data = &sun4i_pwm_data_a10s, | |
351 | }, { | |
352 | .compatible = "allwinner,sun5i-a13-pwm", | |
353 | .data = &sun4i_pwm_data_a13, | |
09853ce7 AB |
354 | }, { |
355 | .compatible = "allwinner,sun7i-a20-pwm", | |
356 | .data = &sun4i_pwm_data_a20, | |
42ddcf4f MK |
357 | }, { |
358 | .compatible = "allwinner,sun8i-h3-pwm", | |
359 | .data = &sun4i_pwm_data_h3, | |
09853ce7 AB |
360 | }, { |
361 | /* sentinel */ | |
362 | }, | |
363 | }; | |
364 | MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids); | |
365 | ||
366 | static int sun4i_pwm_probe(struct platform_device *pdev) | |
367 | { | |
368 | struct sun4i_pwm_chip *pwm; | |
369 | struct resource *res; | |
93e0dfb2 | 370 | int ret; |
09853ce7 AB |
371 | |
372 | pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); | |
373 | if (!pwm) | |
374 | return -ENOMEM; | |
375 | ||
df4f6e8c CL |
376 | pwm->data = of_device_get_match_data(&pdev->dev); |
377 | if (!pwm->data) | |
378 | return -ENODEV; | |
379 | ||
09853ce7 AB |
380 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
381 | pwm->base = devm_ioremap_resource(&pdev->dev, res); | |
382 | if (IS_ERR(pwm->base)) | |
383 | return PTR_ERR(pwm->base); | |
384 | ||
385 | pwm->clk = devm_clk_get(&pdev->dev, NULL); | |
386 | if (IS_ERR(pwm->clk)) | |
387 | return PTR_ERR(pwm->clk); | |
388 | ||
389 | pwm->chip.dev = &pdev->dev; | |
390 | pwm->chip.ops = &sun4i_pwm_ops; | |
391 | pwm->chip.base = -1; | |
f6649f7a | 392 | pwm->chip.npwm = pwm->data->npwm; |
09853ce7 AB |
393 | pwm->chip.of_xlate = of_pwm_xlate_with_flags; |
394 | pwm->chip.of_pwm_n_cells = 3; | |
09853ce7 AB |
395 | |
396 | spin_lock_init(&pwm->ctrl_lock); | |
397 | ||
398 | ret = pwmchip_add(&pwm->chip); | |
399 | if (ret < 0) { | |
400 | dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); | |
401 | return ret; | |
402 | } | |
403 | ||
404 | platform_set_drvdata(pdev, pwm); | |
405 | ||
09853ce7 | 406 | return 0; |
09853ce7 AB |
407 | } |
408 | ||
409 | static int sun4i_pwm_remove(struct platform_device *pdev) | |
410 | { | |
411 | struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); | |
412 | ||
413 | return pwmchip_remove(&pwm->chip); | |
414 | } | |
415 | ||
416 | static struct platform_driver sun4i_pwm_driver = { | |
417 | .driver = { | |
418 | .name = "sun4i-pwm", | |
419 | .of_match_table = sun4i_pwm_dt_ids, | |
420 | }, | |
421 | .probe = sun4i_pwm_probe, | |
422 | .remove = sun4i_pwm_remove, | |
423 | }; | |
424 | module_platform_driver(sun4i_pwm_driver); | |
425 | ||
426 | MODULE_ALIAS("platform:sun4i-pwm"); | |
427 | MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>"); | |
428 | MODULE_DESCRIPTION("Allwinner sun4i PWM driver"); | |
429 | MODULE_LICENSE("GPL v2"); |