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pwm: stm32: Fix for settings using period > UINT32_MAX
[linux-block.git] / drivers / pwm / pwm-stm32.c
CommitLineData
d7a131d3 1// SPDX-License-Identifier: GPL-2.0
7edf7369
BG		 2/*
3 * Copyright (C) STMicroelectronics 2016
4 *
5 * Author: Gerald Baeza <gerald.baeza@st.com>
6 *
7edf7369
BG		 7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
9 */
10
ab3a8978 11#include <linux/bitfield.h>
7edf7369
BG		 12#include <linux/mfd/stm32-timers.h>
13#include <linux/module.h>
14#include <linux/of.h>
2d3aa06b 15#include <linux/pinctrl/consumer.h>
7edf7369
BG		 16#include <linux/platform_device.h>
17#include <linux/pwm.h>
18
19#define CCMR_CHANNEL_SHIFT 8
20#define CCMR_CHANNEL_MASK 0xFF
21#define MAX_BREAKINPUT 2
22
0f9d2ecb
FG		 23struct stm32_breakinput {
24 u32 index;
25 u32 level;
26 u32 filter;
27};
28
7edf7369 29struct stm32_pwm {
4eb67a20 30 struct mutex lock; /* protect pwm config/enable */
7edf7369
BG		 31 struct clk *clk;
32 struct regmap *regmap;
33 u32 max_arr;
34 bool have_complementary_output;
0f9d2ecb
FG		 35 struct stm32_breakinput breakinputs[MAX_BREAKINPUT];
36 unsigned int num_breakinputs;
53e38fe7 37 u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */
7edf7369
BG		 38};
39
7edf7369
BG		 40static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
41{
174821b7 42 return pwmchip_get_drvdata(chip);
7edf7369
BG		 43}
44
45static u32 active_channels(struct stm32_pwm *dev)
46{
47 u32 ccer;
48
49 regmap_read(dev->regmap, TIM_CCER, &ccer);
50
51 return ccer & TIM_CCER_CCXE;
52}
53
53e38fe7
FG		 54#define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P)
55#define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E)
56#define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P)
57#define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E)
58
59/*
60 * Capture using PWM input mode:
61 * ___ ___
62 * TI[1, 2, 3 or 4]: ........._| |________|
63 * ^0 ^1 ^2
64 * . . .
65 * . . XXXXX
66 * . . XXXXX |
67 * . XXXXX . |
68 * XXXXX . . |
69 * COUNTER: ______XXXXX . . . |_XXX
70 * start^ . . . ^stop
71 * . . . .
72 * v v . v
73 * v
74 * CCR1/CCR3: tx..........t0...........t2
75 * CCR2/CCR4: tx..............t1.........
76 *
77 * DMA burst transfer: | |
78 * v v
79 * DMA buffer: { t0, tx } { t2, t1 }
80 * DMA done: ^
81 *
82 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
83 * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care)
84 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
85 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
86 * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1)
87 *
88 * DMA done, compute:
89 * - Period = t2 - t0
90 * - Duty cycle = t1 - t0
91 */
fbde1289 92static int stm32_pwm_raw_capture(struct pwm_chip *chip, struct pwm_device *pwm,
53e38fe7
FG		 93 unsigned long tmo_ms, u32 *raw_prd,
94 u32 *raw_dty)
95{
fbde1289
UKK		 96 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
97 struct device *parent = pwmchip_parent(chip)->parent;
53e38fe7
FG		 98 enum stm32_timers_dmas dma_id;
99 u32 ccen, ccr;
100 int ret;
101
102 /* Ensure registers have been updated, enable counter and capture */
632ae5d7
UKK		 103 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
104 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
53e38fe7
FG		 105
106 /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */
107 dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3;
108 ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E;
109 ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3;
632ae5d7 110 regmap_set_bits(priv->regmap, TIM_CCER, ccen);
53e38fe7
FG		 111
112 /*
113 * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both
114 * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event.
115 * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 }
116 * or { CCR3, CCR4 }, { CCR3, CCR4 }
117 */
118 ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2,
119 2, tmo_ms);
120 if (ret)
121 goto stop;
122
123 /* Period: t2 - t0 (take care of counter overflow) */
124 if (priv->capture[0] <= priv->capture[2])
125 *raw_prd = priv->capture[2] - priv->capture[0];
126 else
127 *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2];
128
129 /* Duty cycle capture requires at least two capture units */
130 if (pwm->chip->npwm < 2)
131 *raw_dty = 0;
132 else if (priv->capture[0] <= priv->capture[3])
133 *raw_dty = priv->capture[3] - priv->capture[0];
134 else
135 *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3];
136
137 if (*raw_dty > *raw_prd) {
138 /*
139 * Race beetween PWM input and DMA: it may happen
140 * falling edge triggers new capture on TI2/4 before DMA
141 * had a chance to read CCR2/4. It means capture[1]
142 * contains period + duty_cycle. So, subtract period.
143 */
144 *raw_dty -= *raw_prd;
145 }
146
147stop:
632ae5d7
UKK		 148 regmap_clear_bits(priv->regmap, TIM_CCER, ccen);
149 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
53e38fe7
FG		 150
151 return ret;
152}
153
154static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
155 struct pwm_capture *result, unsigned long tmo_ms)
156{
157 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
158 unsigned long long prd, div, dty;
159 unsigned long rate;
ab3a8978 160 unsigned int psc = 0, icpsc, scale;
a3b51be3 161 u32 raw_prd = 0, raw_dty = 0;
53e38fe7
FG		 162 int ret = 0;
163
164 mutex_lock(&priv->lock);
165
166 if (active_channels(priv)) {
167 ret = -EBUSY;
168 goto unlock;
169 }
170
171 ret = clk_enable(priv->clk);
172 if (ret) {
fbde1289 173 dev_err(pwmchip_parent(chip), "failed to enable counter clock\n");
53e38fe7
FG		 174 goto unlock;
175 }
176
177 rate = clk_get_rate(priv->clk);
178 if (!rate) {
179 ret = -EINVAL;
180 goto clk_dis;
181 }
182
183 /* prescaler: fit timeout window provided by upper layer */
184 div = (unsigned long long)rate * (unsigned long long)tmo_ms;
185 do_div(div, MSEC_PER_SEC);
186 prd = div;
187 while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) {
188 psc++;
189 div = prd;
190 do_div(div, psc + 1);
191 }
192 regmap_write(priv->regmap, TIM_ARR, priv->max_arr);
193 regmap_write(priv->regmap, TIM_PSC, psc);
194
d0a4564b
OM		 195 /* Reset input selector to its default input and disable slave mode */
196 regmap_write(priv->regmap, TIM_TISEL, 0x0);
197 regmap_write(priv->regmap, TIM_SMCR, 0x0);
198
53e38fe7
FG		 199 /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */
200 regmap_update_bits(priv->regmap,
201 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
202 TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ?
203 TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 :
204 TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1);
205
206 /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */
207 regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ?
208 TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ?
209 TIM_CCER_CC2P : TIM_CCER_CC4P);
210
fbde1289 211 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty);
53e38fe7
FG		 212 if (ret)
213 goto stop;
214
d66ffb91
FG		 215 /*
216 * Got a capture. Try to improve accuracy at high rates:
217 * - decrease counter clock prescaler, scale up to max rate.
ab3a8978 218 * - use input prescaler, capture once every /2 /4 or /8 edges.
d66ffb91
FG		 219 */
220 if (raw_prd) {
221 u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */
222
223 scale = max_arr / min(max_arr, raw_prd);
224 } else {
225 scale = priv->max_arr; /* bellow resolution, use max scale */
226 }
227
228 if (psc && scale > 1) {
229 /* 2nd measure with new scale */
230 psc /= scale;
231 regmap_write(priv->regmap, TIM_PSC, psc);
fbde1289 232 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd,
d66ffb91
FG		 233 &raw_dty);
234 if (ret)
235 goto stop;
236 }
237
ab3a8978 238 /* Compute intermediate period not to exceed timeout at low rates */
53e38fe7 239 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
ab3a8978
FG		 240 do_div(prd, rate);
241
242 for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) {
243 /* input prescaler: also keep arbitrary margin */
244 if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1))
245 break;
246 if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2))
247 break;
248 }
249
250 if (!icpsc)
251 goto done;
252
253 /* Last chance to improve period accuracy, using input prescaler */
254 regmap_update_bits(priv->regmap,
255 pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,
256 TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC,
257 FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) |
258 FIELD_PREP(TIM_CCMR_IC2PSC, icpsc));
259
fbde1289 260 ret = stm32_pwm_raw_capture(chip, pwm, tmo_ms, &raw_prd, &raw_dty);
ab3a8978
FG		 261 if (ret)
262 goto stop;
263
264 if (raw_dty >= (raw_prd >> icpsc)) {
265 /*
266 * We may fall here using input prescaler, when input
267 * capture starts on high side (before falling edge).
268 * Example with icpsc to capture on each 4 events:
269 *
270 * start 1st capture 2nd capture
271 * v v v
272 * ___ _____ _____ _____ _____ ____
273 * TI1..4 |__| |__| |__| |__| |__|
274 * v v . . . . . v v
275 * icpsc1/3: . 0 . 1 . 2 . 3 . 0
276 * icpsc2/4: 0 1 2 3 0
277 * v v v v
278 * CCR1/3 ......t0..............................t2
279 * CCR2/4 ..t1..............................t1'...
280 * . . .
281 * Capture0: .<----------------------------->.
282 * Capture1: .<-------------------------->. .
283 * . . .
284 * Period: .<------> . .
285 * Low side: .<>.
286 *
287 * Result:
288 * - Period = Capture0 / icpsc
289 * - Duty = Period - Low side = Period - (Capture0 - Capture1)
290 */
291 raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty);
292 }
293
294done:
295 prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC;
296 result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc);
53e38fe7
FG		 297 dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;
298 result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
299stop:
300 regmap_write(priv->regmap, TIM_CCER, 0);
301 regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0);
302 regmap_write(priv->regmap, TIM_PSC, 0);
303clk_dis:
304 clk_disable(priv->clk);
305unlock:
306 mutex_unlock(&priv->lock);
307
308 return ret;
309}
310
c0504f59 311static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch,
d44d6356 312 u64 duty_ns, u64 period_ns)
7edf7369
BG		 313{
314 unsigned long long prd, div, dty;
315 unsigned int prescaler = 0;
316 u32 ccmr, mask, shift;
317
d44d6356
UKK		 318 /*
319 * .probe() asserted that clk_get_rate() is not bigger than 1 GHz, so
320 * this won't overflow.
321 */
322 div = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk),
323 NSEC_PER_SEC);
7edf7369
BG		 324 prd = div;
325
326 while (div > priv->max_arr) {
327 prescaler++;
328 div = prd;
329 do_div(div, prescaler + 1);
330 }
331
332 prd = div;
333
334 if (prescaler > MAX_TIM_PSC)
335 return -EINVAL;
336
337 /*
338 * All channels share the same prescaler and counter so when two
339 * channels are active at the same time we can't change them
340 */
341 if (active_channels(priv) & ~(1 << ch * 4)) {
342 u32 psc, arr;
343
344 regmap_read(priv->regmap, TIM_PSC, &psc);
345 regmap_read(priv->regmap, TIM_ARR, &arr);
346
347 if ((psc != prescaler) || (arr != prd - 1))
348 return -EBUSY;
349 }
350
351 regmap_write(priv->regmap, TIM_PSC, prescaler);
352 regmap_write(priv->regmap, TIM_ARR, prd - 1);
632ae5d7 353 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
7edf7369
BG		 354
355 /* Calculate the duty cycles */
d44d6356
UKK		 356 dty = mul_u64_u64_div_u64(duty_ns, clk_get_rate(priv->clk),
357 (u64)NSEC_PER_SEC * (prescaler + 1));
7edf7369 358
e495f472 359 regmap_write(priv->regmap, TIM_CCR1 + 4 * ch, dty);
7edf7369
BG		 360
361 /* Configure output mode */
362 shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
363 ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
364 mask = CCMR_CHANNEL_MASK << shift;
365
366 if (ch < 2)
367 regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
368 else
369 regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
370
632ae5d7 371 regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE);
7edf7369
BG		 372
373 return 0;
374}
375
c0504f59 376static int stm32_pwm_set_polarity(struct stm32_pwm *priv, unsigned int ch,
7edf7369
BG		 377 enum pwm_polarity polarity)
378{
379 u32 mask;
380
381 mask = TIM_CCER_CC1P << (ch * 4);
382 if (priv->have_complementary_output)
383 mask |= TIM_CCER_CC1NP << (ch * 4);
384
385 regmap_update_bits(priv->regmap, TIM_CCER, mask,
386 polarity == PWM_POLARITY_NORMAL ? 0 : mask);
387
388 return 0;
389}
390
c0504f59 391static int stm32_pwm_enable(struct stm32_pwm *priv, unsigned int ch)
7edf7369
BG		 392{
393 u32 mask;
394 int ret;
395
396 ret = clk_enable(priv->clk);
397 if (ret)
398 return ret;
399
400 /* Enable channel */
401 mask = TIM_CCER_CC1E << (ch * 4);
402 if (priv->have_complementary_output)
403 mask |= TIM_CCER_CC1NE << (ch * 4);
404
632ae5d7 405 regmap_set_bits(priv->regmap, TIM_CCER, mask);
7edf7369
BG		 406
407 /* Make sure that registers are updated */
632ae5d7 408 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
7edf7369
BG		 409
410 /* Enable controller */
632ae5d7 411 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
7edf7369
BG		 412
413 return 0;
414}
415
c0504f59 416static void stm32_pwm_disable(struct stm32_pwm *priv, unsigned int ch)
7edf7369
BG		 417{
418 u32 mask;
419
420 /* Disable channel */
421 mask = TIM_CCER_CC1E << (ch * 4);
422 if (priv->have_complementary_output)
423 mask |= TIM_CCER_CC1NE << (ch * 4);
424
632ae5d7 425 regmap_clear_bits(priv->regmap, TIM_CCER, mask);
7edf7369
BG		 426
427 /* When all channels are disabled, we can disable the controller */
428 if (!active_channels(priv))
632ae5d7 429 regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
7edf7369
BG		 430
431 clk_disable(priv->clk);
432}
433
434static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
71523d18 435 const struct pwm_state *state)
7edf7369
BG		 436{
437 bool enabled;
438 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
439 int ret;
440
441 enabled = pwm->state.enabled;
442
443 if (enabled && !state->enabled) {
444 stm32_pwm_disable(priv, pwm->hwpwm);
445 return 0;
446 }
447
448 if (state->polarity != pwm->state.polarity)
449 stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
450
451 ret = stm32_pwm_config(priv, pwm->hwpwm,
452 state->duty_cycle, state->period);
453 if (ret)
454 return ret;
455
456 if (!enabled && state->enabled)
457 ret = stm32_pwm_enable(priv, pwm->hwpwm);
458
459 return ret;
460}
461
4eb67a20 462static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
71523d18 463 const struct pwm_state *state)
4eb67a20
FG		 464{
465 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
466 int ret;
467
468 /* protect common prescaler for all active channels */
469 mutex_lock(&priv->lock);
470 ret = stm32_pwm_apply(chip, pwm, state);
471 mutex_unlock(&priv->lock);
472
473 return ret;
474}
475
e56ec7b7
PZ		 476static int stm32_pwm_get_state(struct pwm_chip *chip,
477 struct pwm_device *pwm, struct pwm_state *state)
478{
479 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
480 int ch = pwm->hwpwm;
481 unsigned long rate;
482 u32 ccer, psc, arr, ccr;
483 u64 dty, prd;
484 int ret;
485
486 mutex_lock(&priv->lock);
487
488 ret = regmap_read(priv->regmap, TIM_CCER, &ccer);
489 if (ret)
490 goto out;
491
492 state->enabled = ccer & (TIM_CCER_CC1E << (ch * 4));
493 state->polarity = (ccer & (TIM_CCER_CC1P << (ch * 4))) ?
494 PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL;
495 ret = regmap_read(priv->regmap, TIM_PSC, &psc);
496 if (ret)
497 goto out;
498 ret = regmap_read(priv->regmap, TIM_ARR, &arr);
499 if (ret)
500 goto out;
501 ret = regmap_read(priv->regmap, TIM_CCR1 + 4 * ch, &ccr);
502 if (ret)
503 goto out;
504
505 rate = clk_get_rate(priv->clk);
506
507 prd = (u64)NSEC_PER_SEC * (psc + 1) * (arr + 1);
508 state->period = DIV_ROUND_UP_ULL(prd, rate);
509 dty = (u64)NSEC_PER_SEC * (psc + 1) * ccr;
510 state->duty_cycle = DIV_ROUND_UP_ULL(dty, rate);
511
512out:
513 mutex_unlock(&priv->lock);
514 return ret;
515}
516
7edf7369 517static const struct pwm_ops stm32pwm_ops = {
4eb67a20 518 .apply = stm32_pwm_apply_locked,
e56ec7b7 519 .get_state = stm32_pwm_get_state,
414c52b7 520 .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
7edf7369
BG		 521};
522
523static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
9e1b4999 524 const struct stm32_breakinput *bi)
7edf7369 525{
9e1b4999
TR		 526 u32 shift = TIM_BDTR_BKF_SHIFT(bi->index);
527 u32 bke = TIM_BDTR_BKE(bi->index);
528 u32 bkp = TIM_BDTR_BKP(bi->index);
529 u32 bkf = TIM_BDTR_BKF(bi->index);
8e536225
TR		 530 u32 mask = bkf | bkp | bke;
531 u32 bdtr;
7edf7369 532
9e1b4999 533 bdtr = (bi->filter & TIM_BDTR_BKF_MASK) << shift | bke;
7edf7369 534
9e1b4999 535 if (bi->level)
8e536225 536 bdtr |= bkp;
7edf7369
BG		 537
538 regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
539
540 regmap_read(priv->regmap, TIM_BDTR, &bdtr);
541
542 return (bdtr & bke) ? 0 : -EINVAL;
543}
544
0f9d2ecb
FG		 545static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv)
546{
547 unsigned int i;
548 int ret;
549
550 for (i = 0; i < priv->num_breakinputs; i++) {
9e1b4999 551 ret = stm32_pwm_set_breakinput(priv, &priv->breakinputs[i]);
0f9d2ecb
FG		 552 if (ret < 0)
553 return ret;
554 }
555
556 return 0;
557}
558
559static int stm32_pwm_probe_breakinputs(struct stm32_pwm *priv,
7edf7369
BG		 560 struct device_node *np)
561{
0f9d2ecb 562 int nb, ret, array_size;
8dfa620e 563 unsigned int i;
7edf7369
BG		 564
565 nb = of_property_count_elems_of_size(np, "st,breakinput",
566 sizeof(struct stm32_breakinput));
567
568 /*
569 * Because "st,breakinput" parameter is optional do not make probe
570 * failed if it doesn't exist.
571 */
572 if (nb <= 0)
573 return 0;
574
575 if (nb > MAX_BREAKINPUT)
576 return -EINVAL;
577
0f9d2ecb 578 priv->num_breakinputs = nb;
7edf7369
BG		 579 array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
580 ret = of_property_read_u32_array(np, "st,breakinput",
0f9d2ecb 581 (u32 *)priv->breakinputs, array_size);
7edf7369
BG		 582 if (ret)
583 return ret;
584
8dfa620e
TR		 585 for (i = 0; i < priv->num_breakinputs; i++) {
586 if (priv->breakinputs[i].index > 1 ||
587 priv->breakinputs[i].level > 1 ||
588 priv->breakinputs[i].filter > 15)
589 return -EINVAL;
590 }
591
0f9d2ecb 592 return stm32_pwm_apply_breakinputs(priv);
7edf7369
BG		 593}
594
595static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
596{
597 u32 ccer;
598
599 /*
600 * If complementary bit doesn't exist writing 1 will have no
601 * effect so we can detect it.
602 */
632ae5d7 603 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
7edf7369 604 regmap_read(priv->regmap, TIM_CCER, &ccer);
632ae5d7 605 regmap_clear_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE);
7edf7369
BG		 606
607 priv->have_complementary_output = (ccer != 0);
608}
609
e315bf70 610static unsigned int stm32_pwm_detect_channels(struct regmap *regmap,
19f1016e 611 unsigned int *num_enabled)
7edf7369 612{
19f1016e 613 u32 ccer, ccer_backup;
7edf7369
BG		 614
615 /*
616 * If channels enable bits don't exist writing 1 will have no
617 * effect so we can detect and count them.
618 */
e315bf70
UKK		 619 regmap_read(regmap, TIM_CCER, &ccer_backup);
620 regmap_set_bits(regmap, TIM_CCER, TIM_CCER_CCXE);
621 regmap_read(regmap, TIM_CCER, &ccer);
622 regmap_write(regmap, TIM_CCER, ccer_backup);
19f1016e
PZ		 623
624 *num_enabled = hweight32(ccer_backup & TIM_CCER_CCXE);
7edf7369 625
41fa8f57 626 return hweight32(ccer & TIM_CCER_CCXE);
7edf7369
BG		 627}
628
629static int stm32_pwm_probe(struct platform_device *pdev)
630{
631 struct device *dev = &pdev->dev;
632 struct device_node *np = dev->of_node;
633 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
f2943071 634 struct pwm_chip *chip;
7edf7369 635 struct stm32_pwm *priv;
174821b7 636 unsigned int npwm, num_enabled;
19f1016e 637 unsigned int i;
7edf7369
BG		 638 int ret;
639
174821b7
UKK		 640 npwm = stm32_pwm_detect_channels(ddata->regmap, &num_enabled);
641
642 chip = devm_pwmchip_alloc(dev, npwm, sizeof(*priv));
643 if (IS_ERR(chip))
644 return PTR_ERR(chip);
645 priv = to_stm32_pwm_dev(chip);
7edf7369 646
4eb67a20 647 mutex_init(&priv->lock);
7edf7369
BG		 648 priv->regmap = ddata->regmap;
649 priv->clk = ddata->clk;
650 priv->max_arr = ddata->max_arr;
651
652 if (!priv->regmap || !priv->clk)
80bd81cb
UKK		 653 return dev_err_probe(dev, -EINVAL, "Failed to get %s\n",
654 priv->regmap ? "clk" : "regmap");
7edf7369 655
0f9d2ecb 656 ret = stm32_pwm_probe_breakinputs(priv, np);
7edf7369 657 if (ret)
80bd81cb
UKK		 658 return dev_err_probe(dev, ret,
659 "Failed to configure breakinputs\n");
7edf7369
BG		 660
661 stm32_pwm_detect_complementary(priv);
662
d44d6356
UKK		 663 ret = devm_clk_rate_exclusive_get(dev, priv->clk);
664 if (ret)
665 return dev_err_probe(dev, ret, "Failed to lock clock\n");
666
667 /*
668 * With the clk running with not more than 1 GHz the calculations in
669 * .apply() won't overflow.
670 */
671 if (clk_get_rate(priv->clk) > 1000000000)
672 return dev_err_probe(dev, -EINVAL, "Failed to lock clock\n");
673
f2943071 674 chip->ops = &stm32pwm_ops;
19f1016e
PZ		 675
676 /* Initialize clock refcount to number of enabled PWM channels. */
677 for (i = 0; i < num_enabled; i++)
678 clk_enable(priv->clk);
7edf7369 679
f2943071 680 ret = devm_pwmchip_add(dev, chip);
7edf7369 681 if (ret < 0)
80bd81cb
UKK		 682 return dev_err_probe(dev, ret,
683 "Failed to register pwmchip\n");
7edf7369 684
f2943071 685 platform_set_drvdata(pdev, chip);
7edf7369
BG		 686
687 return 0;
688}
689
3d672776 690static int stm32_pwm_suspend(struct device *dev)
2d3aa06b 691{
f2943071
UKK		 692 struct pwm_chip *chip = dev_get_drvdata(dev);
693 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
2d3aa06b
FG		 694 unsigned int i;
695 u32 ccer, mask;
696
697 /* Look for active channels */
698 ccer = active_channels(priv);
699
f2943071 700 for (i = 0; i < chip->npwm; i++) {
2d3aa06b
FG		 701 mask = TIM_CCER_CC1E << (i * 4);
702 if (ccer & mask) {
703 dev_err(dev, "PWM %u still in use by consumer %s\n",
f2943071 704 i, chip->pwms[i].label);
2d3aa06b
FG		 705 return -EBUSY;
706 }
707 }
708
709 return pinctrl_pm_select_sleep_state(dev);
710}
711
3d672776 712static int stm32_pwm_resume(struct device *dev)
2d3aa06b 713{
f2943071
UKK		 714 struct pwm_chip *chip = dev_get_drvdata(dev);
715 struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
2d3aa06b
FG		 716 int ret;
717
718 ret = pinctrl_pm_select_default_state(dev);
719 if (ret)
720 return ret;
721
722 /* restore breakinput registers that may have been lost in low power */
723 return stm32_pwm_apply_breakinputs(priv);
724}
725
3d672776 726static DEFINE_SIMPLE_DEV_PM_OPS(stm32_pwm_pm_ops, stm32_pwm_suspend, stm32_pwm_resume);
2d3aa06b 727
7edf7369
BG		 728static const struct of_device_id stm32_pwm_of_match[] = {
729 { .compatible = "st,stm32-pwm", },
730 { /* end node */ },
731};
732MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
733
734static struct platform_driver stm32_pwm_driver = {
735 .probe = stm32_pwm_probe,
7edf7369
BG		 736 .driver = {
737 .name = "stm32-pwm",
738 .of_match_table = stm32_pwm_of_match,
3d672776 739 .pm = pm_ptr(&stm32_pwm_pm_ops),
7edf7369
BG		 740 },
741};
742module_platform_driver(stm32_pwm_driver);
743
744MODULE_ALIAS("platform:stm32-pwm");
745MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
746MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)