[linux-2.6-block.git] / drivers / pwm / pwm-stm32.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) STMicroelectronics 2016
 *
 * Author: Gerald Baeza <gerald.baeza@st.com>
 *
 * Inspired by timer-stm32.c from Maxime Coquelin
 *             pwm-atmel.c from Bo Shen
 */

#include <linux/mfd/stm32-timers.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>

#define CCMR_CHANNEL_SHIFT 8
#define CCMR_CHANNEL_MASK  0xFF
#define MAX_BREAKINPUT 2

struct stm32_pwm {
	struct pwm_chip chip;
	struct mutex lock; /* protect pwm config/enable */
	struct clk *clk;
	struct regmap *regmap;
	u32 max_arr;
	bool have_complementary_output;
};

struct stm32_breakinput {
	u32 index;
	u32 level;
	u32 filter;
};

static inline struct stm32_pwm *to_stm32_pwm_dev(struct pwm_chip *chip)
{
	return container_of(chip, struct stm32_pwm, chip);
}

static u32 active_channels(struct stm32_pwm *dev)
{
	u32 ccer;

	regmap_read(dev->regmap, TIM_CCER, &ccer);

	return ccer & TIM_CCER_CCXE;
}

static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
{
	switch (ch) {
	case 0:
		return regmap_write(dev->regmap, TIM_CCR1, value);
	case 1:
		return regmap_write(dev->regmap, TIM_CCR2, value);
	case 2:
		return regmap_write(dev->regmap, TIM_CCR3, value);
	case 3:
		return regmap_write(dev->regmap, TIM_CCR4, value);
	}
	return -EINVAL;
}

static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
			    int duty_ns, int period_ns)
{
	unsigned long long prd, div, dty;
	unsigned int prescaler = 0;
	u32 ccmr, mask, shift;

	/* Period and prescaler values depends on clock rate */
	div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;

	do_div(div, NSEC_PER_SEC);
	prd = div;

	while (div > priv->max_arr) {
		prescaler++;
		div = prd;
		do_div(div, prescaler + 1);
	}

	prd = div;

	if (prescaler > MAX_TIM_PSC)
		return -EINVAL;

	/*
	 * All channels share the same prescaler and counter so when two
	 * channels are active at the same time we can't change them
	 */
	if (active_channels(priv) & ~(1 << ch * 4)) {
		u32 psc, arr;

		regmap_read(priv->regmap, TIM_PSC, &psc);
		regmap_read(priv->regmap, TIM_ARR, &arr);

		if ((psc != prescaler) || (arr != prd - 1))
			return -EBUSY;
	}

	regmap_write(priv->regmap, TIM_PSC, prescaler);
	regmap_write(priv->regmap, TIM_ARR, prd - 1);
	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);

	/* Calculate the duty cycles */
	dty = prd * duty_ns;
	do_div(dty, period_ns);

	write_ccrx(priv, ch, dty);

	/* Configure output mode */
	shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
	ccmr = (TIM_CCMR_PE | TIM_CCMR_M1) << shift;
	mask = CCMR_CHANNEL_MASK << shift;

	if (ch < 2)
		regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
	else
		regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);

	regmap_update_bits(priv->regmap, TIM_BDTR,
			   TIM_BDTR_MOE | TIM_BDTR_AOE,
			   TIM_BDTR_MOE | TIM_BDTR_AOE);

	return 0;
}

static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
				  enum pwm_polarity polarity)
{
	u32 mask;

	mask = TIM_CCER_CC1P << (ch * 4);
	if (priv->have_complementary_output)
		mask |= TIM_CCER_CC1NP << (ch * 4);

	regmap_update_bits(priv->regmap, TIM_CCER, mask,
			   polarity == PWM_POLARITY_NORMAL ? 0 : mask);

	return 0;
}

static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
{
	u32 mask;
	int ret;

	ret = clk_enable(priv->clk);
	if (ret)
		return ret;

	/* Enable channel */
	mask = TIM_CCER_CC1E << (ch * 4);
	if (priv->have_complementary_output)
		mask |= TIM_CCER_CC1NE << (ch * 4);

	regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);

	/* Make sure that registers are updated */
	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);

	/* Enable controller */
	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);

	return 0;
}

static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
{
	u32 mask;

	/* Disable channel */
	mask = TIM_CCER_CC1E << (ch * 4);
	if (priv->have_complementary_output)
		mask |= TIM_CCER_CC1NE << (ch * 4);

	regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);

	/* When all channels are disabled, we can disable the controller */
	if (!active_channels(priv))
		regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);

	clk_disable(priv->clk);
}

static int stm32_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			   struct pwm_state *state)
{
	bool enabled;
	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
	int ret;

	enabled = pwm->state.enabled;

	if (enabled && !state->enabled) {
		stm32_pwm_disable(priv, pwm->hwpwm);
		return 0;
	}

	if (state->polarity != pwm->state.polarity)
		stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);

	ret = stm32_pwm_config(priv, pwm->hwpwm,
			       state->duty_cycle, state->period);
	if (ret)
		return ret;

	if (!enabled && state->enabled)
		ret = stm32_pwm_enable(priv, pwm->hwpwm);

	return ret;
}

static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm,
				  struct pwm_state *state)
{
	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
	int ret;

	/* protect common prescaler for all active channels */
	mutex_lock(&priv->lock);
	ret = stm32_pwm_apply(chip, pwm, state);
	mutex_unlock(&priv->lock);

	return ret;
}

static const struct pwm_ops stm32pwm_ops = {
	.owner = THIS_MODULE,
	.apply = stm32_pwm_apply_locked,
};

static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
				    int index, int level, int filter)
{
	u32 bke = (index == 0) ? TIM_BDTR_BKE : TIM_BDTR_BK2E;
	int shift = (index == 0) ? TIM_BDTR_BKF_SHIFT : TIM_BDTR_BK2F_SHIFT;
	u32 mask = (index == 0) ? TIM_BDTR_BKE | TIM_BDTR_BKP | TIM_BDTR_BKF
				: TIM_BDTR_BK2E | TIM_BDTR_BK2P | TIM_BDTR_BK2F;
	u32 bdtr = bke;

	/*
	 * The both bits could be set since only one will be wrote
	 * due to mask value.
	 */
	if (level)
		bdtr |= TIM_BDTR_BKP | TIM_BDTR_BK2P;

	bdtr |= (filter & TIM_BDTR_BKF_MASK) << shift;

	regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);

	regmap_read(priv->regmap, TIM_BDTR, &bdtr);

	return (bdtr & bke) ? 0 : -EINVAL;
}

static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv,
				       struct device_node *np)
{
	struct stm32_breakinput breakinput[MAX_BREAKINPUT];
	int nb, ret, i, array_size;

	nb = of_property_count_elems_of_size(np, "st,breakinput",
					     sizeof(struct stm32_breakinput));

	/*
	 * Because "st,breakinput" parameter is optional do not make probe
	 * failed if it doesn't exist.
	 */
	if (nb <= 0)
		return 0;

	if (nb > MAX_BREAKINPUT)
		return -EINVAL;

	array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
	ret = of_property_read_u32_array(np, "st,breakinput",
					 (u32 *)breakinput, array_size);
	if (ret)
		return ret;

	for (i = 0; i < nb && !ret; i++) {
		ret = stm32_pwm_set_breakinput(priv,
					       breakinput[i].index,
					       breakinput[i].level,
					       breakinput[i].filter);
	}

	return ret;
}

static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
{
	u32 ccer;

	/*
	 * If complementary bit doesn't exist writing 1 will have no
	 * effect so we can detect it.
	 */
	regmap_update_bits(priv->regmap,
			   TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
	regmap_read(priv->regmap, TIM_CCER, &ccer);
	regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);

	priv->have_complementary_output = (ccer != 0);
}

static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
{
	u32 ccer;
	int npwm = 0;

	/*
	 * If channels enable bits don't exist writing 1 will have no
	 * effect so we can detect and count them.
	 */
	regmap_update_bits(priv->regmap,
			   TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
	regmap_read(priv->regmap, TIM_CCER, &ccer);
	regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);

	if (ccer & TIM_CCER_CC1E)
		npwm++;

	if (ccer & TIM_CCER_CC2E)
		npwm++;

	if (ccer & TIM_CCER_CC3E)
		npwm++;

	if (ccer & TIM_CCER_CC4E)
		npwm++;

	return npwm;
}

static int stm32_pwm_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
	struct stm32_pwm *priv;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	mutex_init(&priv->lock);
	priv->regmap = ddata->regmap;
	priv->clk = ddata->clk;
	priv->max_arr = ddata->max_arr;

	if (!priv->regmap || !priv->clk)
		return -EINVAL;

	ret = stm32_pwm_apply_breakinputs(priv, np);
	if (ret)
		return ret;

	stm32_pwm_detect_complementary(priv);

	priv->chip.base = -1;
	priv->chip.dev = dev;
	priv->chip.ops = &stm32pwm_ops;
	priv->chip.npwm = stm32_pwm_detect_channels(priv);

	ret = pwmchip_add(&priv->chip);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, priv);

	return 0;
}

static int stm32_pwm_remove(struct platform_device *pdev)
{
	struct stm32_pwm *priv = platform_get_drvdata(pdev);
	unsigned int i;

	for (i = 0; i < priv->chip.npwm; i++)
		pwm_disable(&priv->chip.pwms[i]);

	pwmchip_remove(&priv->chip);

	return 0;
}

static const struct of_device_id stm32_pwm_of_match[] = {
	{ .compatible = "st,stm32-pwm",	},
	{ /* end node */ },
};
MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);

static struct platform_driver stm32_pwm_driver = {
	.probe	= stm32_pwm_probe,
	.remove	= stm32_pwm_remove,
	.driver	= {
		.name = "stm32-pwm",
		.of_match_table = stm32_pwm_of_match,
	},
};
module_platform_driver(stm32_pwm_driver);

MODULE_ALIAS("platform:stm32-pwm");
MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d7a131d3	1	// SPDX-License-Identifier: GPL-2.0
7edf7369 BG	2	/*
	3	* Copyright (C) STMicroelectronics 2016
	4	*
	5	* Author: Gerald Baeza <gerald.baeza@st.com>
	6	*
7edf7369 BG	7	* Inspired by timer-stm32.c from Maxime Coquelin
	8	* pwm-atmel.c from Bo Shen
	9	*/
	10
	11	#include <linux/mfd/stm32-timers.h>
	12	#include <linux/module.h>
	13	#include <linux/of.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/pwm.h>
	16
	17	#define CCMR_CHANNEL_SHIFT 8
	18	#define CCMR_CHANNEL_MASK 0xFF
	19	#define MAX_BREAKINPUT 2
	20
	21	struct stm32_pwm {
	22	struct pwm_chip chip;
4eb67a20	23	struct mutex lock; /* protect pwm config/enable */
7edf7369 BG	24	struct clk *clk;
	25	struct regmap *regmap;
	26	u32 max_arr;
	27	bool have_complementary_output;
	28	};
	29
	30	struct stm32_breakinput {
	31	u32 index;
	32	u32 level;
	33	u32 filter;
	34	};
	35
	36	static inline struct stm32_pwm to_stm32_pwm_dev(struct pwm_chip chip)
	37	{
	38	return container_of(chip, struct stm32_pwm, chip);
	39	}
	40
	41	static u32 active_channels(struct stm32_pwm *dev)
	42	{
	43	u32 ccer;
	44
	45	regmap_read(dev->regmap, TIM_CCER, &ccer);
	46
	47	return ccer & TIM_CCER_CCXE;
	48	}
	49
	50	static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value)
	51	{
	52	switch (ch) {
	53	case 0:
	54	return regmap_write(dev->regmap, TIM_CCR1, value);
	55	case 1:
	56	return regmap_write(dev->regmap, TIM_CCR2, value);
	57	case 2:
	58	return regmap_write(dev->regmap, TIM_CCR3, value);
	59	case 3:
	60	return regmap_write(dev->regmap, TIM_CCR4, value);
	61	}
	62	return -EINVAL;
	63	}
	64
	65	static int stm32_pwm_config(struct stm32_pwm *priv, int ch,
	66	int duty_ns, int period_ns)
	67	{
	68	unsigned long long prd, div, dty;
	69	unsigned int prescaler = 0;
	70	u32 ccmr, mask, shift;
	71
	72	/* Period and prescaler values depends on clock rate */
	73	div = (unsigned long long)clk_get_rate(priv->clk) * period_ns;
	74
	75	do_div(div, NSEC_PER_SEC);
	76	prd = div;
	77
	78	while (div > priv->max_arr) {
	79	prescaler++;
	80	div = prd;
	81	do_div(div, prescaler + 1);
	82	}
	83
	84	prd = div;
	85
	86	if (prescaler > MAX_TIM_PSC)
	87	return -EINVAL;
88
89	/*
90	* All channels share the same prescaler and counter so when two
91	* channels are active at the same time we can't change them
92	*/
93	if (active_channels(priv) & ~(1 << ch * 4)) {
94	u32 psc, arr;
95
96	regmap_read(priv->regmap, TIM_PSC, &psc);
97	regmap_read(priv->regmap, TIM_ARR, &arr);
98
99	if ((psc != prescaler) \|\| (arr != prd - 1))
100	return -EBUSY;
101	}
102
103	regmap_write(priv->regmap, TIM_PSC, prescaler);
104	regmap_write(priv->regmap, TIM_ARR, prd - 1);
105	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
106
107	/* Calculate the duty cycles */
108	dty = prd * duty_ns;
109	do_div(dty, period_ns);
110
111	write_ccrx(priv, ch, dty);
112
113	/* Configure output mode */
114	shift = (ch & 0x1) * CCMR_CHANNEL_SHIFT;
115	ccmr = (TIM_CCMR_PE \| TIM_CCMR_M1) << shift;
116	mask = CCMR_CHANNEL_MASK << shift;
117
118	if (ch < 2)
119	regmap_update_bits(priv->regmap, TIM_CCMR1, mask, ccmr);
120	else
121	regmap_update_bits(priv->regmap, TIM_CCMR2, mask, ccmr);
122
123	regmap_update_bits(priv->regmap, TIM_BDTR,
124	TIM_BDTR_MOE \| TIM_BDTR_AOE,
125	TIM_BDTR_MOE \| TIM_BDTR_AOE);
126
127	return 0;
128	}
129
130	static int stm32_pwm_set_polarity(struct stm32_pwm *priv, int ch,
131	enum pwm_polarity polarity)
132	{
133	u32 mask;
134
135	mask = TIM_CCER_CC1P << (ch * 4);
136	if (priv->have_complementary_output)
137	mask \|= TIM_CCER_CC1NP << (ch * 4);
138
139	regmap_update_bits(priv->regmap, TIM_CCER, mask,
140	polarity == PWM_POLARITY_NORMAL ? 0 : mask);
141
142	return 0;
143	}
144
145	static int stm32_pwm_enable(struct stm32_pwm *priv, int ch)
146	{
147	u32 mask;
148	int ret;
149
150	ret = clk_enable(priv->clk);
151	if (ret)
152	return ret;
153
154	/* Enable channel */
155	mask = TIM_CCER_CC1E << (ch * 4);
156	if (priv->have_complementary_output)
157	mask \|= TIM_CCER_CC1NE << (ch * 4);
158
159	regmap_update_bits(priv->regmap, TIM_CCER, mask, mask);
160
161	/* Make sure that registers are updated */
162	regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
163
164	/* Enable controller */
165	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
166
167	return 0;
168	}
169
170	static void stm32_pwm_disable(struct stm32_pwm *priv, int ch)
171	{
172	u32 mask;
173
174	/* Disable channel */
175	mask = TIM_CCER_CC1E << (ch * 4);
176	if (priv->have_complementary_output)
177	mask \|= TIM_CCER_CC1NE << (ch * 4);
178
179	regmap_update_bits(priv->regmap, TIM_CCER, mask, 0);
180
181	/* When all channels are disabled, we can disable the controller */
182	if (!active_channels(priv))
183	regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
184
185	clk_disable(priv->clk);
186	}
187
188	static int stm32_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
189	struct pwm_state *state)
190	{
191	bool enabled;
192	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
193	int ret;
194
195	enabled = pwm->state.enabled;
196
197	if (enabled && !state->enabled) {
198	stm32_pwm_disable(priv, pwm->hwpwm);
199	return 0;
200	}
201
202	if (state->polarity != pwm->state.polarity)
203	stm32_pwm_set_polarity(priv, pwm->hwpwm, state->polarity);
204
205	ret = stm32_pwm_config(priv, pwm->hwpwm,
206	state->duty_cycle, state->period);
207	if (ret)
208	return ret;
209
210	if (!enabled && state->enabled)
211	ret = stm32_pwm_enable(priv, pwm->hwpwm);
212
213	return ret;
214	}
215
4eb67a20 FG	216	static int stm32_pwm_apply_locked(struct pwm_chip chip, struct pwm_device pwm,
	217	struct pwm_state *state)
	218	{
	219	struct stm32_pwm *priv = to_stm32_pwm_dev(chip);
	220	int ret;
	221
	222	/* protect common prescaler for all active channels */
	223	mutex_lock(&priv->lock);
	224	ret = stm32_pwm_apply(chip, pwm, state);
	225	mutex_unlock(&priv->lock);
	226
	227	return ret;
	228	}
	229
7edf7369 BG	230	static const struct pwm_ops stm32pwm_ops = {
7edf7369 BG	231	.owner = THIS_MODULE,
4eb67a20	232	.apply = stm32_pwm_apply_locked,
7edf7369 BG	233	};
	234
	235	static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,
	236	int index, int level, int filter)
	237	{
	238	u32 bke = (index == 0) ? TIM_BDTR_BKE : TIM_BDTR_BK2E;
	239	int shift = (index == 0) ? TIM_BDTR_BKF_SHIFT : TIM_BDTR_BK2F_SHIFT;
	240	u32 mask = (index == 0) ? TIM_BDTR_BKE \| TIM_BDTR_BKP \| TIM_BDTR_BKF
	241	: TIM_BDTR_BK2E \| TIM_BDTR_BK2P \| TIM_BDTR_BK2F;
	242	u32 bdtr = bke;
	243
	244	/*
	245	* The both bits could be set since only one will be wrote
	246	* due to mask value.
	247	*/
	248	if (level)
	249	bdtr \|= TIM_BDTR_BKP \| TIM_BDTR_BK2P;
	250
	251	bdtr \|= (filter & TIM_BDTR_BKF_MASK) << shift;
	252
	253	regmap_update_bits(priv->regmap, TIM_BDTR, mask, bdtr);
	254
	255	regmap_read(priv->regmap, TIM_BDTR, &bdtr);
	256
	257	return (bdtr & bke) ? 0 : -EINVAL;
	258	}
	259
	260	static int stm32_pwm_apply_breakinputs(struct stm32_pwm *priv,
	261	struct device_node *np)
	262	{
	263	struct stm32_breakinput breakinput[MAX_BREAKINPUT];
	264	int nb, ret, i, array_size;
	265
	266	nb = of_property_count_elems_of_size(np, "st,breakinput",
	267	sizeof(struct stm32_breakinput));
	268
	269	/*
	270	* Because "st,breakinput" parameter is optional do not make probe
	271	* failed if it doesn't exist.
	272	*/
	273	if (nb <= 0)
	274	return 0;
	275
	276	if (nb > MAX_BREAKINPUT)
	277	return -EINVAL;
	278
	279	array_size = nb * sizeof(struct stm32_breakinput) / sizeof(u32);
	280	ret = of_property_read_u32_array(np, "st,breakinput",
	281	(u32 *)breakinput, array_size);
	282	if (ret)
	283	return ret;
	284
	285	for (i = 0; i < nb && !ret; i++) {
	286	ret = stm32_pwm_set_breakinput(priv,
	287	breakinput[i].index,
	288	breakinput[i].level,
	289	breakinput[i].filter);
	290	}
	291
	292	return ret;
	293	}
	294
	295	static void stm32_pwm_detect_complementary(struct stm32_pwm *priv)
	296	{
297	u32 ccer;
298
299	/*
300	* If complementary bit doesn't exist writing 1 will have no
301	* effect so we can detect it.
302	*/
303	regmap_update_bits(priv->regmap,
304	TIM_CCER, TIM_CCER_CC1NE, TIM_CCER_CC1NE);
305	regmap_read(priv->regmap, TIM_CCER, &ccer);
306	regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE, 0);
307
308	priv->have_complementary_output = (ccer != 0);
309	}
310
311	static int stm32_pwm_detect_channels(struct stm32_pwm *priv)
312	{
313	u32 ccer;
314	int npwm = 0;
315
316	/*
317	* If channels enable bits don't exist writing 1 will have no
318	* effect so we can detect and count them.
319	*/
320	regmap_update_bits(priv->regmap,
321	TIM_CCER, TIM_CCER_CCXE, TIM_CCER_CCXE);
322	regmap_read(priv->regmap, TIM_CCER, &ccer);
323	regmap_update_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE, 0);
324
325	if (ccer & TIM_CCER_CC1E)
326	npwm++;
327
328	if (ccer & TIM_CCER_CC2E)
329	npwm++;
330
331	if (ccer & TIM_CCER_CC3E)
332	npwm++;
333
334	if (ccer & TIM_CCER_CC4E)
335	npwm++;
336
337	return npwm;
338	}
339
340	static int stm32_pwm_probe(struct platform_device *pdev)
341	{
342	struct device *dev = &pdev->dev;
343	struct device_node *np = dev->of_node;
344	struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
345	struct stm32_pwm *priv;
346	int ret;
347
348	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
349	if (!priv)
350	return -ENOMEM;
351
4eb67a20	352	mutex_init(&priv->lock);
7edf7369 BG	353	priv->regmap = ddata->regmap;
	354	priv->clk = ddata->clk;
	355	priv->max_arr = ddata->max_arr;
	356
	357	if (!priv->regmap \|\| !priv->clk)
	358	return -EINVAL;
	359
	360	ret = stm32_pwm_apply_breakinputs(priv, np);
	361	if (ret)
	362	return ret;
	363
	364	stm32_pwm_detect_complementary(priv);
	365
	366	priv->chip.base = -1;
	367	priv->chip.dev = dev;
	368	priv->chip.ops = &stm32pwm_ops;
	369	priv->chip.npwm = stm32_pwm_detect_channels(priv);
	370
	371	ret = pwmchip_add(&priv->chip);
	372	if (ret < 0)
	373	return ret;
	374
	375	platform_set_drvdata(pdev, priv);
	376
	377	return 0;
	378	}
	379
	380	static int stm32_pwm_remove(struct platform_device *pdev)
	381	{
	382	struct stm32_pwm *priv = platform_get_drvdata(pdev);
	383	unsigned int i;
	384
	385	for (i = 0; i < priv->chip.npwm; i++)
	386	pwm_disable(&priv->chip.pwms[i]);
	387
	388	pwmchip_remove(&priv->chip);
	389
	390	return 0;
	391	}
	392
	393	static const struct of_device_id stm32_pwm_of_match[] = {
	394	{ .compatible = "st,stm32-pwm", },
	395	{ /* end node */ },
	396	};
	397	MODULE_DEVICE_TABLE(of, stm32_pwm_of_match);
	398
	399	static struct platform_driver stm32_pwm_driver = {
	400	.probe = stm32_pwm_probe,
	401	.remove = stm32_pwm_remove,
	402	.driver = {
	403	.name = "stm32-pwm",
	404	.of_match_table = stm32_pwm_of_match,
	405	},
	406	};
	407	module_platform_driver(stm32_pwm_driver);
	408
	409	MODULE_ALIAS("platform:stm32-pwm");
	410	MODULE_DESCRIPTION("STMicroelectronics STM32 PWM driver");
	411	MODULE_LICENSE("GPL v2");