Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
378fe115 | 2 | /* |
7d8a600c LJ |
3 | * PWM device driver for ST SoCs |
4 | * | |
5 | * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited | |
378fe115 | 6 | * |
7d8a600c LJ |
7 | * Author: Ajit Pal Singh <ajitpal.singh@st.com> |
8 | * Lee Jones <lee.jones@linaro.org> | |
378fe115 LJ |
9 | */ |
10 | ||
378fe115 | 11 | #include <linux/clk.h> |
3f0925b5 | 12 | #include <linux/interrupt.h> |
378fe115 LJ |
13 | #include <linux/math64.h> |
14 | #include <linux/mfd/syscon.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/pwm.h> | |
19 | #include <linux/regmap.h> | |
3f0925b5 | 20 | #include <linux/sched.h> |
378fe115 LJ |
21 | #include <linux/slab.h> |
22 | #include <linux/time.h> | |
3f0925b5 | 23 | #include <linux/wait.h> |
378fe115 | 24 | |
c5f94ae6 | 25 | #define PWM_OUT_VAL(x) (0x00 + (4 * (x))) /* Device's Duty Cycle register */ |
f66d78fa LJ |
26 | #define PWM_CPT_VAL(x) (0x10 + (4 * (x))) /* Capture value */ |
27 | #define PWM_CPT_EDGE(x) (0x30 + (4 * (x))) /* Edge to capture on */ | |
c5f94ae6 LJ |
28 | |
29 | #define STI_PWM_CTRL 0x50 /* Control/Config register */ | |
30 | #define STI_INT_EN 0x54 /* Interrupt Enable/Disable register */ | |
f66d78fa | 31 | #define STI_INT_STA 0x58 /* Interrupt Status register */ |
7d8a600c LJ |
32 | #define PWM_INT_ACK 0x5c |
33 | #define PWM_PRESCALE_LOW_MASK 0x0f | |
34 | #define PWM_PRESCALE_HIGH_MASK 0xf0 | |
35 | #define PWM_CPT_EDGE_MASK 0x03 | |
36 | #define PWM_INT_ACK_MASK 0x1ff | |
f66d78fa | 37 | |
7d8a600c LJ |
38 | #define STI_MAX_CPT_DEVS 4 |
39 | #define CPT_DC_MAX 0xff | |
378fe115 LJ |
40 | |
41 | /* Regfield IDs */ | |
42 | enum { | |
c5f94ae6 | 43 | /* Bits in PWM_CTRL*/ |
bf9cc80b APS |
44 | PWMCLK_PRESCALE_LOW, |
45 | PWMCLK_PRESCALE_HIGH, | |
f66d78fa | 46 | CPTCLK_PRESCALE, |
c5f94ae6 LJ |
47 | |
48 | PWM_OUT_EN, | |
f66d78fa | 49 | PWM_CPT_EN, |
c5f94ae6 LJ |
50 | |
51 | PWM_CPT_INT_EN, | |
f66d78fa | 52 | PWM_CPT_INT_STAT, |
378fe115 LJ |
53 | |
54 | /* Keep last */ | |
55 | MAX_REGFIELDS | |
56 | }; | |
57 | ||
7d8a600c LJ |
58 | /* |
59 | * Each capture input can be programmed to detect rising-edge, falling-edge, | |
60 | * either edge or neither egde. | |
f66d78fa LJ |
61 | */ |
62 | enum sti_cpt_edge { | |
63 | CPT_EDGE_DISABLED, | |
64 | CPT_EDGE_RISING, | |
65 | CPT_EDGE_FALLING, | |
66 | CPT_EDGE_BOTH, | |
67 | }; | |
68 | ||
3f0925b5 LJ |
69 | struct sti_cpt_ddata { |
70 | u32 snapshot[3]; | |
71 | unsigned int index; | |
72 | struct mutex lock; | |
73 | wait_queue_head_t wait; | |
74 | }; | |
75 | ||
378fe115 LJ |
76 | struct sti_pwm_chip { |
77 | struct device *dev; | |
c5f94ae6 | 78 | struct clk *pwm_clk; |
d66a928d | 79 | struct clk *cpt_clk; |
378fe115 | 80 | struct regmap *regmap; |
9e287e0c UKK |
81 | unsigned int pwm_num_devs; |
82 | unsigned int cpt_num_devs; | |
83 | unsigned int max_pwm_cnt; | |
84 | unsigned int max_prescale; | |
85 | struct sti_cpt_ddata *ddata; | |
bf9cc80b APS |
86 | struct regmap_field *prescale_low; |
87 | struct regmap_field *prescale_high; | |
c5f94ae6 | 88 | struct regmap_field *pwm_out_en; |
25eb5380 | 89 | struct regmap_field *pwm_cpt_en; |
c5f94ae6 | 90 | struct regmap_field *pwm_cpt_int_en; |
25eb5380 | 91 | struct regmap_field *pwm_cpt_int_stat; |
5165166e | 92 | struct pwm_device *cur; |
cd264b6a | 93 | unsigned long configured; |
6ad6b838 APS |
94 | unsigned int en_count; |
95 | struct mutex sti_pwm_lock; /* To sync between enable/disable calls */ | |
378fe115 LJ |
96 | void __iomem *mmio; |
97 | }; | |
98 | ||
99 | static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = { | |
7d8a600c LJ |
100 | [PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3), |
101 | [PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14), | |
102 | [CPTCLK_PRESCALE] = REG_FIELD(STI_PWM_CTRL, 4, 8), | |
103 | [PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9), | |
104 | [PWM_CPT_EN] = REG_FIELD(STI_PWM_CTRL, 10, 10), | |
105 | [PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4), | |
106 | [PWM_CPT_INT_STAT] = REG_FIELD(STI_INT_STA, 1, 4), | |
378fe115 LJ |
107 | }; |
108 | ||
109 | static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip) | |
110 | { | |
3f7dc7d8 | 111 | return pwmchip_get_drvdata(chip); |
378fe115 LJ |
112 | } |
113 | ||
114 | /* | |
3aacd3e1 | 115 | * Calculate the prescaler value corresponding to the period. |
378fe115 | 116 | */ |
3aacd3e1 APS |
117 | static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period, |
118 | unsigned int *prescale) | |
378fe115 | 119 | { |
d81738b7 | 120 | unsigned long clk_rate; |
7d8a600c | 121 | unsigned long value; |
3aacd3e1 | 122 | unsigned int ps; |
378fe115 | 123 | |
d81738b7 LJ |
124 | clk_rate = clk_get_rate(pc->pwm_clk); |
125 | if (!clk_rate) { | |
126 | dev_err(pc->dev, "failed to get clock rate\n"); | |
127 | return -EINVAL; | |
128 | } | |
129 | ||
378fe115 | 130 | /* |
7d8a600c | 131 | * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_cnt + 1)) - 1 |
378fe115 | 132 | */ |
7d8a600c | 133 | value = NSEC_PER_SEC / clk_rate; |
9e287e0c | 134 | value *= pc->max_pwm_cnt + 1; |
378fe115 | 135 | |
7d8a600c | 136 | if (period % value) |
3aacd3e1 | 137 | return -EINVAL; |
7d8a600c LJ |
138 | |
139 | ps = period / value - 1; | |
9e287e0c | 140 | if (ps > pc->max_prescale) |
7d8a600c LJ |
141 | return -EINVAL; |
142 | ||
3aacd3e1 APS |
143 | *prescale = ps; |
144 | ||
145 | return 0; | |
378fe115 LJ |
146 | } |
147 | ||
378fe115 | 148 | /* |
7d8a600c LJ |
149 | * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles. The |
150 | * only way to change the period (apart from changing the PWM input clock) is | |
151 | * to change the PWM clock prescaler. | |
152 | * | |
153 | * The prescaler is of 8 bits, so 256 prescaler values and hence 256 possible | |
154 | * period values are supported (for a particular clock rate). The requested | |
155 | * period will be applied only if it matches one of these 256 values. | |
378fe115 LJ |
156 | */ |
157 | static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |
7d8a600c | 158 | int duty_ns, int period_ns) |
378fe115 LJ |
159 | { |
160 | struct sti_pwm_chip *pc = to_sti_pwmchip(chip); | |
7d8a600c | 161 | unsigned int ncfg, value, prescale = 0; |
5165166e | 162 | struct pwm_device *cur = pc->cur; |
378fe115 | 163 | struct device *dev = pc->dev; |
5165166e | 164 | bool period_same = false; |
7d8a600c | 165 | int ret; |
5165166e | 166 | |
cd264b6a | 167 | ncfg = hweight_long(pc->configured); |
5165166e APS |
168 | if (ncfg) |
169 | period_same = (period_ns == pwm_get_period(cur)); | |
170 | ||
7d8a600c LJ |
171 | /* |
172 | * Allow configuration changes if one of the following conditions | |
173 | * satisfy. | |
09022e61 | 174 | * 1. No devices have been configured. |
7d8a600c LJ |
175 | * 2. Only one device has been configured and the new request is for |
176 | * the same device. | |
177 | * 3. Only one device has been configured and the new request is for | |
178 | * a new device and period of the new device is same as the current | |
179 | * configured period. | |
09022e61 | 180 | * 4. More than one devices are configured and period of the new |
5165166e | 181 | * requestis the same as the current period. |
378fe115 | 182 | */ |
5165166e APS |
183 | if (!ncfg || |
184 | ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) || | |
185 | ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) || | |
186 | ((ncfg > 1) && period_same)) { | |
187 | /* Enable clock before writing to PWM registers. */ | |
c5f94ae6 | 188 | ret = clk_enable(pc->pwm_clk); |
5165166e APS |
189 | if (ret) |
190 | return ret; | |
191 | ||
d66a928d LJ |
192 | ret = clk_enable(pc->cpt_clk); |
193 | if (ret) | |
194 | return ret; | |
195 | ||
5165166e | 196 | if (!period_same) { |
3aacd3e1 APS |
197 | ret = sti_pwm_get_prescale(pc, period_ns, &prescale); |
198 | if (ret) | |
5165166e | 199 | goto clk_dis; |
5165166e | 200 | |
7d8a600c LJ |
201 | value = prescale & PWM_PRESCALE_LOW_MASK; |
202 | ||
203 | ret = regmap_field_write(pc->prescale_low, value); | |
5165166e APS |
204 | if (ret) |
205 | goto clk_dis; | |
206 | ||
7d8a600c LJ |
207 | value = (prescale & PWM_PRESCALE_HIGH_MASK) >> 4; |
208 | ||
209 | ret = regmap_field_write(pc->prescale_high, value); | |
5165166e APS |
210 | if (ret) |
211 | goto clk_dis; | |
212 | } | |
213 | ||
214 | /* | |
215 | * When PWMVal == 0, PWM pulse = 1 local clock cycle. | |
216 | * When PWMVal == max_pwm_count, | |
217 | * PWM pulse = (max_pwm_count + 1) local cycles, | |
218 | * that is continuous pulse: signal never goes low. | |
219 | */ | |
9e287e0c | 220 | value = pc->max_pwm_cnt * duty_ns / period_ns; |
5165166e | 221 | |
7d8a600c | 222 | ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value); |
5165166e APS |
223 | if (ret) |
224 | goto clk_dis; | |
225 | ||
c5f94ae6 | 226 | ret = regmap_field_write(pc->pwm_cpt_int_en, 0); |
5165166e | 227 | |
cd264b6a | 228 | set_bit(pwm->hwpwm, &pc->configured); |
5165166e APS |
229 | pc->cur = pwm; |
230 | ||
7d8a600c LJ |
231 | dev_dbg(dev, "prescale:%u, period:%i, duty:%i, value:%u\n", |
232 | prescale, period_ns, duty_ns, value); | |
5165166e | 233 | } else { |
378fe115 LJ |
234 | return -EINVAL; |
235 | } | |
236 | ||
378fe115 | 237 | clk_dis: |
c5f94ae6 | 238 | clk_disable(pc->pwm_clk); |
d66a928d | 239 | clk_disable(pc->cpt_clk); |
378fe115 LJ |
240 | return ret; |
241 | } | |
242 | ||
243 | static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
244 | { | |
245 | struct sti_pwm_chip *pc = to_sti_pwmchip(chip); | |
246 | struct device *dev = pc->dev; | |
6ad6b838 | 247 | int ret = 0; |
378fe115 | 248 | |
6ad6b838 | 249 | /* |
7d8a600c LJ |
250 | * Since we have a common enable for all PWM devices, do not enable if |
251 | * already enabled. | |
6ad6b838 APS |
252 | */ |
253 | mutex_lock(&pc->sti_pwm_lock); | |
7d8a600c | 254 | |
6ad6b838 | 255 | if (!pc->en_count) { |
c5f94ae6 | 256 | ret = clk_enable(pc->pwm_clk); |
6ad6b838 APS |
257 | if (ret) |
258 | goto out; | |
378fe115 | 259 | |
d66a928d LJ |
260 | ret = clk_enable(pc->cpt_clk); |
261 | if (ret) | |
262 | goto out; | |
263 | ||
c5f94ae6 | 264 | ret = regmap_field_write(pc->pwm_out_en, 1); |
6ad6b838 | 265 | if (ret) { |
7d8a600c LJ |
266 | dev_err(dev, "failed to enable PWM device %u: %d\n", |
267 | pwm->hwpwm, ret); | |
6ad6b838 APS |
268 | goto out; |
269 | } | |
270 | } | |
7d8a600c | 271 | |
6ad6b838 | 272 | pc->en_count++; |
7d8a600c | 273 | |
6ad6b838 APS |
274 | out: |
275 | mutex_unlock(&pc->sti_pwm_lock); | |
378fe115 LJ |
276 | return ret; |
277 | } | |
278 | ||
279 | static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
280 | { | |
281 | struct sti_pwm_chip *pc = to_sti_pwmchip(chip); | |
378fe115 | 282 | |
6ad6b838 | 283 | mutex_lock(&pc->sti_pwm_lock); |
7d8a600c | 284 | |
6ad6b838 APS |
285 | if (--pc->en_count) { |
286 | mutex_unlock(&pc->sti_pwm_lock); | |
287 | return; | |
288 | } | |
7d8a600c | 289 | |
c5f94ae6 | 290 | regmap_field_write(pc->pwm_out_en, 0); |
378fe115 | 291 | |
c5f94ae6 | 292 | clk_disable(pc->pwm_clk); |
d66a928d | 293 | clk_disable(pc->cpt_clk); |
7d8a600c | 294 | |
6ad6b838 | 295 | mutex_unlock(&pc->sti_pwm_lock); |
378fe115 LJ |
296 | } |
297 | ||
cd264b6a APS |
298 | static void sti_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
299 | { | |
300 | struct sti_pwm_chip *pc = to_sti_pwmchip(chip); | |
301 | ||
302 | clear_bit(pwm->hwpwm, &pc->configured); | |
303 | } | |
304 | ||
c97267ae LJ |
305 | static int sti_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, |
306 | struct pwm_capture *result, unsigned long timeout) | |
307 | { | |
308 | struct sti_pwm_chip *pc = to_sti_pwmchip(chip); | |
9e287e0c | 309 | struct sti_cpt_ddata *ddata = &pc->ddata[pwm->hwpwm]; |
c97267ae LJ |
310 | struct device *dev = pc->dev; |
311 | unsigned int effective_ticks; | |
312 | unsigned long long high, low; | |
313 | int ret; | |
314 | ||
9e287e0c | 315 | if (pwm->hwpwm >= pc->cpt_num_devs) { |
c97267ae LJ |
316 | dev_err(dev, "device %u is not valid\n", pwm->hwpwm); |
317 | return -EINVAL; | |
318 | } | |
319 | ||
320 | mutex_lock(&ddata->lock); | |
321 | ddata->index = 0; | |
322 | ||
323 | /* Prepare capture measurement */ | |
324 | regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING); | |
325 | regmap_field_write(pc->pwm_cpt_int_en, BIT(pwm->hwpwm)); | |
326 | ||
327 | /* Enable capture */ | |
328 | ret = regmap_field_write(pc->pwm_cpt_en, 1); | |
329 | if (ret) { | |
330 | dev_err(dev, "failed to enable PWM capture %u: %d\n", | |
331 | pwm->hwpwm, ret); | |
332 | goto out; | |
333 | } | |
334 | ||
335 | ret = wait_event_interruptible_timeout(ddata->wait, ddata->index > 1, | |
336 | msecs_to_jiffies(timeout)); | |
337 | ||
338 | regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_DISABLED); | |
339 | ||
340 | if (ret == -ERESTARTSYS) | |
341 | goto out; | |
342 | ||
343 | switch (ddata->index) { | |
344 | case 0: | |
345 | case 1: | |
346 | /* | |
347 | * Getting here could mean: | |
348 | * - input signal is constant of less than 1 Hz | |
349 | * - there is no input signal at all | |
350 | * | |
351 | * In such case the frequency is rounded down to 0 | |
352 | */ | |
353 | result->period = 0; | |
354 | result->duty_cycle = 0; | |
355 | ||
356 | break; | |
357 | ||
358 | case 2: | |
359 | /* We have everying we need */ | |
360 | high = ddata->snapshot[1] - ddata->snapshot[0]; | |
361 | low = ddata->snapshot[2] - ddata->snapshot[1]; | |
362 | ||
363 | effective_ticks = clk_get_rate(pc->cpt_clk); | |
364 | ||
365 | result->period = (high + low) * NSEC_PER_SEC; | |
366 | result->period /= effective_ticks; | |
367 | ||
368 | result->duty_cycle = high * NSEC_PER_SEC; | |
369 | result->duty_cycle /= effective_ticks; | |
370 | ||
371 | break; | |
372 | ||
373 | default: | |
374 | dev_err(dev, "internal error\n"); | |
375 | break; | |
376 | } | |
377 | ||
378 | out: | |
379 | /* Disable capture */ | |
380 | regmap_field_write(pc->pwm_cpt_en, 0); | |
381 | ||
382 | mutex_unlock(&ddata->lock); | |
383 | return ret; | |
384 | } | |
385 | ||
b2e60b32 UKK |
386 | static int sti_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
387 | const struct pwm_state *state) | |
388 | { | |
5f623835 | 389 | struct sti_pwm_chip *pc = to_sti_pwmchip(chip); |
5f623835 | 390 | struct device *dev = pc->dev; |
b2e60b32 UKK |
391 | int err; |
392 | ||
9e287e0c | 393 | if (pwm->hwpwm >= pc->pwm_num_devs) { |
5f623835 UKK |
394 | dev_err(dev, "device %u is not valid for pwm mode\n", |
395 | pwm->hwpwm); | |
396 | return -EINVAL; | |
397 | } | |
398 | ||
b2e60b32 UKK |
399 | if (state->polarity != PWM_POLARITY_NORMAL) |
400 | return -EINVAL; | |
401 | ||
402 | if (!state->enabled) { | |
403 | if (pwm->state.enabled) | |
404 | sti_pwm_disable(chip, pwm); | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
80943bbd | 409 | err = sti_pwm_config(chip, pwm, state->duty_cycle, state->period); |
b2e60b32 UKK |
410 | if (err) |
411 | return err; | |
412 | ||
413 | if (!pwm->state.enabled) | |
414 | err = sti_pwm_enable(chip, pwm); | |
415 | ||
416 | return err; | |
417 | } | |
418 | ||
378fe115 | 419 | static const struct pwm_ops sti_pwm_ops = { |
c97267ae | 420 | .capture = sti_pwm_capture, |
b2e60b32 | 421 | .apply = sti_pwm_apply, |
cd264b6a | 422 | .free = sti_pwm_free, |
378fe115 LJ |
423 | }; |
424 | ||
25eb5380 LJ |
425 | static irqreturn_t sti_pwm_interrupt(int irq, void *data) |
426 | { | |
427 | struct sti_pwm_chip *pc = data; | |
428 | struct device *dev = pc->dev; | |
429 | struct sti_cpt_ddata *ddata; | |
430 | int devicenum; | |
431 | unsigned int cpt_int_stat; | |
432 | unsigned int reg; | |
433 | int ret = IRQ_NONE; | |
434 | ||
435 | ret = regmap_field_read(pc->pwm_cpt_int_stat, &cpt_int_stat); | |
436 | if (ret) | |
437 | return ret; | |
438 | ||
439 | while (cpt_int_stat) { | |
440 | devicenum = ffs(cpt_int_stat) - 1; | |
441 | ||
9e287e0c | 442 | ddata = &pc->ddata[devicenum]; |
25eb5380 LJ |
443 | |
444 | /* | |
445 | * Capture input: | |
446 | * _______ _______ | |
447 | * | | | | | |
448 | * __| |_________________| |________ | |
449 | * ^0 ^1 ^2 | |
450 | * | |
7d8a600c LJ |
451 | * Capture start by the first available rising edge. When a |
452 | * capture event occurs, capture value (CPT_VALx) is stored, | |
453 | * index incremented, capture edge changed. | |
25eb5380 | 454 | * |
7d8a600c LJ |
455 | * After the capture, if the index > 1, we have collected the |
456 | * necessary data so we signal the thread waiting for it and | |
457 | * disable the capture by setting capture edge to none | |
25eb5380 LJ |
458 | */ |
459 | ||
460 | regmap_read(pc->regmap, | |
461 | PWM_CPT_VAL(devicenum), | |
462 | &ddata->snapshot[ddata->index]); | |
463 | ||
464 | switch (ddata->index) { | |
465 | case 0: | |
466 | case 1: | |
467 | regmap_read(pc->regmap, PWM_CPT_EDGE(devicenum), ®); | |
468 | reg ^= PWM_CPT_EDGE_MASK; | |
469 | regmap_write(pc->regmap, PWM_CPT_EDGE(devicenum), reg); | |
470 | ||
471 | ddata->index++; | |
472 | break; | |
7d8a600c | 473 | |
25eb5380 LJ |
474 | case 2: |
475 | regmap_write(pc->regmap, | |
476 | PWM_CPT_EDGE(devicenum), | |
477 | CPT_EDGE_DISABLED); | |
478 | wake_up(&ddata->wait); | |
479 | break; | |
7d8a600c | 480 | |
25eb5380 LJ |
481 | default: |
482 | dev_err(dev, "Internal error\n"); | |
483 | } | |
484 | ||
485 | cpt_int_stat &= ~BIT_MASK(devicenum); | |
486 | ||
487 | ret = IRQ_HANDLED; | |
488 | } | |
489 | ||
490 | /* Just ACK everything */ | |
491 | regmap_write(pc->regmap, PWM_INT_ACK, PWM_INT_ACK_MASK); | |
492 | ||
493 | return ret; | |
494 | } | |
495 | ||
3025c9c6 | 496 | static int sti_pwm_probe_regmap(struct sti_pwm_chip *pc) |
378fe115 LJ |
497 | { |
498 | struct device *dev = pc->dev; | |
378fe115 | 499 | |
bf9cc80b | 500 | pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap, |
354bf751 | 501 | sti_pwm_regfields[PWMCLK_PRESCALE_LOW]); |
bf9cc80b APS |
502 | if (IS_ERR(pc->prescale_low)) |
503 | return PTR_ERR(pc->prescale_low); | |
504 | ||
505 | pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap, | |
354bf751 | 506 | sti_pwm_regfields[PWMCLK_PRESCALE_HIGH]); |
bf9cc80b APS |
507 | if (IS_ERR(pc->prescale_high)) |
508 | return PTR_ERR(pc->prescale_high); | |
378fe115 | 509 | |
c5f94ae6 | 510 | pc->pwm_out_en = devm_regmap_field_alloc(dev, pc->regmap, |
354bf751 | 511 | sti_pwm_regfields[PWM_OUT_EN]); |
c5f94ae6 LJ |
512 | if (IS_ERR(pc->pwm_out_en)) |
513 | return PTR_ERR(pc->pwm_out_en); | |
514 | ||
c97267ae | 515 | pc->pwm_cpt_en = devm_regmap_field_alloc(dev, pc->regmap, |
354bf751 | 516 | sti_pwm_regfields[PWM_CPT_EN]); |
c97267ae LJ |
517 | if (IS_ERR(pc->pwm_cpt_en)) |
518 | return PTR_ERR(pc->pwm_cpt_en); | |
519 | ||
c5f94ae6 | 520 | pc->pwm_cpt_int_en = devm_regmap_field_alloc(dev, pc->regmap, |
354bf751 | 521 | sti_pwm_regfields[PWM_CPT_INT_EN]); |
c5f94ae6 LJ |
522 | if (IS_ERR(pc->pwm_cpt_int_en)) |
523 | return PTR_ERR(pc->pwm_cpt_int_en); | |
378fe115 | 524 | |
25eb5380 | 525 | pc->pwm_cpt_int_stat = devm_regmap_field_alloc(dev, pc->regmap, |
354bf751 | 526 | sti_pwm_regfields[PWM_CPT_INT_STAT]); |
25eb5380 LJ |
527 | if (PTR_ERR_OR_ZERO(pc->pwm_cpt_int_stat)) |
528 | return PTR_ERR(pc->pwm_cpt_int_stat); | |
529 | ||
378fe115 LJ |
530 | return 0; |
531 | } | |
532 | ||
533 | static const struct regmap_config sti_pwm_regmap_config = { | |
534 | .reg_bits = 32, | |
535 | .val_bits = 32, | |
536 | .reg_stride = 4, | |
537 | }; | |
538 | ||
539 | static int sti_pwm_probe(struct platform_device *pdev) | |
540 | { | |
541 | struct device *dev = &pdev->dev; | |
3f7dc7d8 UKK |
542 | struct device_node *np = dev->of_node; |
543 | u32 num_devs; | |
544 | unsigned int pwm_num_devs = 0; | |
545 | unsigned int cpt_num_devs = 0; | |
54272761 | 546 | struct pwm_chip *chip; |
378fe115 | 547 | struct sti_pwm_chip *pc; |
3f0925b5 | 548 | unsigned int i; |
25eb5380 | 549 | int irq, ret; |
378fe115 | 550 | |
3f7dc7d8 UKK |
551 | ret = of_property_read_u32(np, "st,pwm-num-chan", &num_devs); |
552 | if (!ret) | |
553 | pwm_num_devs = num_devs; | |
554 | ||
555 | ret = of_property_read_u32(np, "st,capture-num-chan", &num_devs); | |
556 | if (!ret) | |
557 | cpt_num_devs = num_devs; | |
558 | ||
3025c9c6 UKK |
559 | if (!pwm_num_devs && !cpt_num_devs) |
560 | return dev_err_probe(dev, -EINVAL, "No channels configured\n"); | |
3f7dc7d8 UKK |
561 | |
562 | chip = devm_pwmchip_alloc(dev, max(pwm_num_devs, cpt_num_devs), sizeof(*pc)); | |
563 | if (IS_ERR(chip)) | |
564 | return PTR_ERR(chip); | |
565 | pc = to_sti_pwmchip(chip); | |
378fe115 | 566 | |
728cd3e6 | 567 | pc->mmio = devm_platform_ioremap_resource(pdev, 0); |
378fe115 LJ |
568 | if (IS_ERR(pc->mmio)) |
569 | return PTR_ERR(pc->mmio); | |
570 | ||
571 | pc->regmap = devm_regmap_init_mmio(dev, pc->mmio, | |
572 | &sti_pwm_regmap_config); | |
573 | if (IS_ERR(pc->regmap)) | |
3025c9c6 UKK |
574 | return dev_err_probe(dev, PTR_ERR(pc->regmap), |
575 | "Failed to initialize regmap\n"); | |
378fe115 | 576 | |
25eb5380 | 577 | irq = platform_get_irq(pdev, 0); |
fb5a35db | 578 | if (irq < 0) |
25eb5380 | 579 | return irq; |
25eb5380 LJ |
580 | |
581 | ret = devm_request_irq(&pdev->dev, irq, sti_pwm_interrupt, 0, | |
582 | pdev->name, pc); | |
3025c9c6 UKK |
583 | if (ret < 0) |
584 | dev_err_probe(&pdev->dev, ret, "Failed to request IRQ\n"); | |
25eb5380 | 585 | |
378fe115 LJ |
586 | /* |
587 | * Setup PWM data with default values: some values could be replaced | |
588 | * with specific ones provided from Device Tree. | |
589 | */ | |
9e287e0c UKK |
590 | pc->max_prescale = 0xff; |
591 | pc->max_pwm_cnt = 255; | |
592 | pc->pwm_num_devs = pwm_num_devs; | |
593 | pc->cpt_num_devs = cpt_num_devs; | |
378fe115 | 594 | |
378fe115 | 595 | pc->dev = dev; |
6ad6b838 APS |
596 | pc->en_count = 0; |
597 | mutex_init(&pc->sti_pwm_lock); | |
378fe115 | 598 | |
3025c9c6 | 599 | ret = sti_pwm_probe_regmap(pc); |
378fe115 | 600 | if (ret) |
3025c9c6 | 601 | return dev_err_probe(dev, ret, "Failed to initialize regmap fields\n"); |
378fe115 | 602 | |
9e287e0c | 603 | if (pc->pwm_num_devs) { |
5bb0b194 | 604 | pc->pwm_clk = devm_clk_get_prepared(dev, "pwm"); |
3025c9c6 UKK |
605 | if (IS_ERR(pc->pwm_clk)) |
606 | return dev_err_probe(dev, PTR_ERR(pc->pwm_clk), | |
607 | "failed to get PWM clock\n"); | |
378fe115 LJ |
608 | } |
609 | ||
9e287e0c | 610 | if (pc->cpt_num_devs) { |
5bb0b194 | 611 | pc->cpt_clk = devm_clk_get_prepared(dev, "capture"); |
3025c9c6 UKK |
612 | if (IS_ERR(pc->cpt_clk)) |
613 | return dev_err_probe(dev, PTR_ERR(pc->cpt_clk), | |
614 | "failed to get PWM capture clock\n"); | |
d66a928d | 615 | |
c0143f68 UKK |
616 | pc->ddata = devm_kcalloc(dev, pc->cpt_num_devs, |
617 | sizeof(*pc->ddata), GFP_KERNEL); | |
9e287e0c | 618 | if (!pc->ddata) |
2d6812b4 | 619 | return -ENOMEM; |
d66a928d LJ |
620 | } |
621 | ||
54272761 | 622 | chip->ops = &sti_pwm_ops; |
378fe115 | 623 | |
9e287e0c UKK |
624 | for (i = 0; i < pc->cpt_num_devs; i++) { |
625 | struct sti_cpt_ddata *ddata = &pc->ddata[i]; | |
3f0925b5 LJ |
626 | |
627 | init_waitqueue_head(&ddata->wait); | |
628 | mutex_init(&ddata->lock); | |
2d6812b4 | 629 | } |
3f0925b5 | 630 | |
3025c9c6 UKK |
631 | ret = devm_pwmchip_add(dev, chip); |
632 | if (ret) | |
633 | return dev_err_probe(dev, ret, "Failed to register pwm chip\n"); | |
634 | ||
635 | return 0; | |
378fe115 LJ |
636 | } |
637 | ||
638 | static const struct of_device_id sti_pwm_of_match[] = { | |
639 | { .compatible = "st,sti-pwm", }, | |
640 | { /* sentinel */ } | |
641 | }; | |
642 | MODULE_DEVICE_TABLE(of, sti_pwm_of_match); | |
643 | ||
644 | static struct platform_driver sti_pwm_driver = { | |
645 | .driver = { | |
646 | .name = "sti-pwm", | |
647 | .of_match_table = sti_pwm_of_match, | |
648 | }, | |
649 | .probe = sti_pwm_probe, | |
378fe115 LJ |
650 | }; |
651 | module_platform_driver(sti_pwm_driver); | |
652 | ||
653 | MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>"); | |
654 | MODULE_DESCRIPTION("STMicroelectronics ST PWM driver"); | |
655 | MODULE_LICENSE("GPL"); |