pwm: sti: It's now valid for number of PWM channels to be zero
[linux-block.git] / drivers / pwm / pwm-sti.c
CommitLineData
378fe115
LJ
1/*
2 * PWM device driver for ST SoCs.
3 * Author: Ajit Pal Singh <ajitpal.singh@st.com>
4 *
5 * Copyright (C) 2013-2014 STMicroelectronics (R&D) Limited
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
378fe115 13#include <linux/clk.h>
3f0925b5 14#include <linux/interrupt.h>
378fe115
LJ
15#include <linux/math64.h>
16#include <linux/mfd/syscon.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/pwm.h>
21#include <linux/regmap.h>
3f0925b5 22#include <linux/sched.h>
378fe115
LJ
23#include <linux/slab.h>
24#include <linux/time.h>
3f0925b5 25#include <linux/wait.h>
378fe115 26
c5f94ae6 27#define PWM_OUT_VAL(x) (0x00 + (4 * (x))) /* Device's Duty Cycle register */
f66d78fa
LJ
28#define PWM_CPT_VAL(x) (0x10 + (4 * (x))) /* Capture value */
29#define PWM_CPT_EDGE(x) (0x30 + (4 * (x))) /* Edge to capture on */
c5f94ae6
LJ
30
31#define STI_PWM_CTRL 0x50 /* Control/Config register */
32#define STI_INT_EN 0x54 /* Interrupt Enable/Disable register */
f66d78fa
LJ
33#define STI_INT_STA 0x58 /* Interrupt Status register */
34#define PWM_INT_ACK 0x5c
bf9cc80b
APS
35#define PWM_PRESCALE_LOW_MASK 0x0f
36#define PWM_PRESCALE_HIGH_MASK 0xf0
f66d78fa
LJ
37#define PWM_CPT_EDGE_MASK 0x03
38#define PWM_INT_ACK_MASK 0x1ff
39
40#define STI_MAX_CPT_DEVS 4
41#define CPT_DC_MAX 0xff
378fe115
LJ
42
43/* Regfield IDs */
44enum {
c5f94ae6 45 /* Bits in PWM_CTRL*/
bf9cc80b
APS
46 PWMCLK_PRESCALE_LOW,
47 PWMCLK_PRESCALE_HIGH,
f66d78fa 48 CPTCLK_PRESCALE,
c5f94ae6
LJ
49
50 PWM_OUT_EN,
f66d78fa 51 PWM_CPT_EN,
c5f94ae6
LJ
52
53 PWM_CPT_INT_EN,
f66d78fa 54 PWM_CPT_INT_STAT,
378fe115
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55
56 /* Keep last */
57 MAX_REGFIELDS
58};
59
f66d78fa
LJ
60/* Each capture input can be programmed to detect rising-edge, falling-edge,
61 * either edge or neither egde
62 */
63enum sti_cpt_edge {
64 CPT_EDGE_DISABLED,
65 CPT_EDGE_RISING,
66 CPT_EDGE_FALLING,
67 CPT_EDGE_BOTH,
68};
69
3f0925b5
LJ
70struct sti_cpt_ddata {
71 u32 snapshot[3];
72 unsigned int index;
73 struct mutex lock;
74 wait_queue_head_t wait;
75};
76
378fe115
LJ
77struct sti_pwm_compat_data {
78 const struct reg_field *reg_fields;
3f0925b5
LJ
79 unsigned int pwm_num_devs;
80 unsigned int cpt_num_devs;
378fe115
LJ
81 unsigned int max_pwm_cnt;
82 unsigned int max_prescale;
83};
84
85struct sti_pwm_chip {
86 struct device *dev;
c5f94ae6 87 struct clk *pwm_clk;
d66a928d 88 struct clk *cpt_clk;
378fe115
LJ
89 struct regmap *regmap;
90 struct sti_pwm_compat_data *cdata;
bf9cc80b
APS
91 struct regmap_field *prescale_low;
92 struct regmap_field *prescale_high;
c5f94ae6 93 struct regmap_field *pwm_out_en;
25eb5380 94 struct regmap_field *pwm_cpt_en;
c5f94ae6 95 struct regmap_field *pwm_cpt_int_en;
25eb5380 96 struct regmap_field *pwm_cpt_int_stat;
378fe115 97 struct pwm_chip chip;
5165166e 98 struct pwm_device *cur;
cd264b6a 99 unsigned long configured;
6ad6b838
APS
100 unsigned int en_count;
101 struct mutex sti_pwm_lock; /* To sync between enable/disable calls */
378fe115
LJ
102 void __iomem *mmio;
103};
104
105static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = {
c5f94ae6
LJ
106 [PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3),
107 [PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14),
f66d78fa 108 [CPTCLK_PRESCALE] = REG_FIELD(STI_PWM_CTRL, 4, 8),
c5f94ae6 109 [PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9),
f66d78fa 110 [PWM_CPT_EN] = REG_FIELD(STI_PWM_CTRL, 10, 10),
c5f94ae6 111 [PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4),
f66d78fa 112 [PWM_CPT_INT_STAT] = REG_FIELD(STI_INT_STA, 1, 4),
378fe115
LJ
113};
114
115static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip)
116{
117 return container_of(chip, struct sti_pwm_chip, chip);
118}
119
120/*
3aacd3e1 121 * Calculate the prescaler value corresponding to the period.
378fe115 122 */
3aacd3e1
APS
123static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period,
124 unsigned int *prescale)
378fe115
LJ
125{
126 struct sti_pwm_compat_data *cdata = pc->cdata;
d81738b7 127 unsigned long clk_rate;
378fe115 128 unsigned long val;
3aacd3e1 129 unsigned int ps;
378fe115 130
d81738b7
LJ
131 clk_rate = clk_get_rate(pc->pwm_clk);
132 if (!clk_rate) {
133 dev_err(pc->dev, "failed to get clock rate\n");
134 return -EINVAL;
135 }
136
378fe115 137 /*
3aacd3e1 138 * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_count + 1)) - 1
378fe115 139 */
d81738b7 140 val = NSEC_PER_SEC / clk_rate;
378fe115
LJ
141 val *= cdata->max_pwm_cnt + 1;
142
3aacd3e1
APS
143 if (period % val) {
144 return -EINVAL;
145 } else {
146 ps = period / val - 1;
147 if (ps > cdata->max_prescale)
148 return -EINVAL;
378fe115 149 }
3aacd3e1
APS
150 *prescale = ps;
151
152 return 0;
378fe115
LJ
153}
154
378fe115
LJ
155/*
156 * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles.
157 * The only way to change the period (apart from changing the PWM input clock)
158 * is to change the PWM clock prescaler.
bf9cc80b
APS
159 * The prescaler is of 8 bits, so 256 prescaler values and hence
160 * 256 possible period values are supported (for a particular clock rate).
378fe115 161 * The requested period will be applied only if it matches one of these
bf9cc80b 162 * 256 values.
378fe115
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163 */
164static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
165 int duty_ns, int period_ns)
166{
167 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
168 struct sti_pwm_compat_data *cdata = pc->cdata;
5165166e 169 struct pwm_device *cur = pc->cur;
378fe115 170 struct device *dev = pc->dev;
5165166e 171 unsigned int prescale = 0, pwmvalx;
378fe115 172 int ret;
5165166e
APS
173 unsigned int ncfg;
174 bool period_same = false;
175
cd264b6a 176 ncfg = hweight_long(pc->configured);
5165166e
APS
177 if (ncfg)
178 period_same = (period_ns == pwm_get_period(cur));
179
180 /* Allow configuration changes if one of the
181 * following conditions satisfy.
09022e61
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182 * 1. No devices have been configured.
183 * 2. Only one device has been configured and the new request
184 * is for the same device.
185 * 3. Only one device has been configured and the new request is
186 * for a new device and period of the new device is same as
5165166e 187 * the current configured period.
09022e61 188 * 4. More than one devices are configured and period of the new
5165166e 189 * requestis the same as the current period.
378fe115 190 */
5165166e
APS
191 if (!ncfg ||
192 ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) ||
193 ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) ||
194 ((ncfg > 1) && period_same)) {
195 /* Enable clock before writing to PWM registers. */
c5f94ae6 196 ret = clk_enable(pc->pwm_clk);
5165166e
APS
197 if (ret)
198 return ret;
199
d66a928d
LJ
200 ret = clk_enable(pc->cpt_clk);
201 if (ret)
202 return ret;
203
5165166e 204 if (!period_same) {
3aacd3e1
APS
205 ret = sti_pwm_get_prescale(pc, period_ns, &prescale);
206 if (ret)
5165166e 207 goto clk_dis;
5165166e
APS
208
209 ret =
210 regmap_field_write(pc->prescale_low,
211 prescale & PWM_PRESCALE_LOW_MASK);
212 if (ret)
213 goto clk_dis;
214
215 ret =
216 regmap_field_write(pc->prescale_high,
217 (prescale & PWM_PRESCALE_HIGH_MASK) >> 4);
218 if (ret)
219 goto clk_dis;
220 }
221
222 /*
223 * When PWMVal == 0, PWM pulse = 1 local clock cycle.
224 * When PWMVal == max_pwm_count,
225 * PWM pulse = (max_pwm_count + 1) local cycles,
226 * that is continuous pulse: signal never goes low.
227 */
228 pwmvalx = cdata->max_pwm_cnt * duty_ns / period_ns;
229
c5f94ae6
LJ
230 ret = regmap_write(pc->regmap,
231 PWM_OUT_VAL(pwm->hwpwm), pwmvalx);
5165166e
APS
232 if (ret)
233 goto clk_dis;
234
c5f94ae6 235 ret = regmap_field_write(pc->pwm_cpt_int_en, 0);
5165166e 236
cd264b6a 237 set_bit(pwm->hwpwm, &pc->configured);
5165166e
APS
238 pc->cur = pwm;
239
240 dev_dbg(dev, "prescale:%u, period:%i, duty:%i, pwmvalx:%u\n",
241 prescale, period_ns, duty_ns, pwmvalx);
242 } else {
378fe115
LJ
243 return -EINVAL;
244 }
245
378fe115 246clk_dis:
c5f94ae6 247 clk_disable(pc->pwm_clk);
d66a928d 248 clk_disable(pc->cpt_clk);
378fe115
LJ
249 return ret;
250}
251
252static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
253{
254 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
255 struct device *dev = pc->dev;
6ad6b838 256 int ret = 0;
378fe115 257
6ad6b838 258 /*
09022e61 259 * Since we have a common enable for all PWM devices,
6ad6b838
APS
260 * do not enable if already enabled.
261 */
262 mutex_lock(&pc->sti_pwm_lock);
263 if (!pc->en_count) {
c5f94ae6 264 ret = clk_enable(pc->pwm_clk);
6ad6b838
APS
265 if (ret)
266 goto out;
378fe115 267
d66a928d
LJ
268 ret = clk_enable(pc->cpt_clk);
269 if (ret)
270 goto out;
271
c5f94ae6 272 ret = regmap_field_write(pc->pwm_out_en, 1);
6ad6b838
APS
273 if (ret) {
274 dev_err(dev, "failed to enable PWM device:%d\n",
275 pwm->hwpwm);
276 goto out;
277 }
278 }
279 pc->en_count++;
280out:
281 mutex_unlock(&pc->sti_pwm_lock);
378fe115
LJ
282 return ret;
283}
284
285static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
286{
287 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
378fe115 288
6ad6b838
APS
289 mutex_lock(&pc->sti_pwm_lock);
290 if (--pc->en_count) {
291 mutex_unlock(&pc->sti_pwm_lock);
292 return;
293 }
c5f94ae6 294 regmap_field_write(pc->pwm_out_en, 0);
378fe115 295
c5f94ae6 296 clk_disable(pc->pwm_clk);
d66a928d 297 clk_disable(pc->cpt_clk);
6ad6b838 298 mutex_unlock(&pc->sti_pwm_lock);
378fe115
LJ
299}
300
cd264b6a
APS
301static void sti_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
302{
303 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
304
305 clear_bit(pwm->hwpwm, &pc->configured);
306}
307
c97267ae
LJ
308static int sti_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
309 struct pwm_capture *result, unsigned long timeout)
310{
311 struct sti_pwm_chip *pc = to_sti_pwmchip(chip);
312 struct sti_pwm_compat_data *cdata = pc->cdata;
313 struct sti_cpt_ddata *ddata = pwm_get_chip_data(pwm);
314 struct device *dev = pc->dev;
315 unsigned int effective_ticks;
316 unsigned long long high, low;
317 int ret;
318
319 if (pwm->hwpwm >= cdata->cpt_num_devs) {
320 dev_err(dev, "device %u is not valid\n", pwm->hwpwm);
321 return -EINVAL;
322 }
323
324 mutex_lock(&ddata->lock);
325 ddata->index = 0;
326
327 /* Prepare capture measurement */
328 regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING);
329 regmap_field_write(pc->pwm_cpt_int_en, BIT(pwm->hwpwm));
330
331 /* Enable capture */
332 ret = regmap_field_write(pc->pwm_cpt_en, 1);
333 if (ret) {
334 dev_err(dev, "failed to enable PWM capture %u: %d\n",
335 pwm->hwpwm, ret);
336 goto out;
337 }
338
339 ret = wait_event_interruptible_timeout(ddata->wait, ddata->index > 1,
340 msecs_to_jiffies(timeout));
341
342 regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_DISABLED);
343
344 if (ret == -ERESTARTSYS)
345 goto out;
346
347 switch (ddata->index) {
348 case 0:
349 case 1:
350 /*
351 * Getting here could mean:
352 * - input signal is constant of less than 1 Hz
353 * - there is no input signal at all
354 *
355 * In such case the frequency is rounded down to 0
356 */
357 result->period = 0;
358 result->duty_cycle = 0;
359
360 break;
361
362 case 2:
363 /* We have everying we need */
364 high = ddata->snapshot[1] - ddata->snapshot[0];
365 low = ddata->snapshot[2] - ddata->snapshot[1];
366
367 effective_ticks = clk_get_rate(pc->cpt_clk);
368
369 result->period = (high + low) * NSEC_PER_SEC;
370 result->period /= effective_ticks;
371
372 result->duty_cycle = high * NSEC_PER_SEC;
373 result->duty_cycle /= effective_ticks;
374
375 break;
376
377 default:
378 dev_err(dev, "internal error\n");
379 break;
380 }
381
382out:
383 /* Disable capture */
384 regmap_field_write(pc->pwm_cpt_en, 0);
385
386 mutex_unlock(&ddata->lock);
387 return ret;
388}
389
378fe115 390static const struct pwm_ops sti_pwm_ops = {
c97267ae 391 .capture = sti_pwm_capture,
378fe115
LJ
392 .config = sti_pwm_config,
393 .enable = sti_pwm_enable,
394 .disable = sti_pwm_disable,
cd264b6a 395 .free = sti_pwm_free,
378fe115
LJ
396 .owner = THIS_MODULE,
397};
398
25eb5380
LJ
399static irqreturn_t sti_pwm_interrupt(int irq, void *data)
400{
401 struct sti_pwm_chip *pc = data;
402 struct device *dev = pc->dev;
403 struct sti_cpt_ddata *ddata;
404 int devicenum;
405 unsigned int cpt_int_stat;
406 unsigned int reg;
407 int ret = IRQ_NONE;
408
409 ret = regmap_field_read(pc->pwm_cpt_int_stat, &cpt_int_stat);
410 if (ret)
411 return ret;
412
413 while (cpt_int_stat) {
414 devicenum = ffs(cpt_int_stat) - 1;
415
416 ddata = pwm_get_chip_data(&pc->chip.pwms[devicenum]);
417
418 /*
419 * Capture input:
420 * _______ _______
421 * | | | |
422 * __| |_________________| |________
423 * ^0 ^1 ^2
424 *
425 * Capture start by the first available rising edge
426 * When a capture event occurs, capture value (CPT_VALx)
427 * is stored, index incremented, capture edge changed.
428 *
429 * After the capture, if the index > 1, we have collected
430 * the necessary data so we signal the thread waiting for it
431 * and disable the capture by setting capture edge to none
432 *
433 */
434
435 regmap_read(pc->regmap,
436 PWM_CPT_VAL(devicenum),
437 &ddata->snapshot[ddata->index]);
438
439 switch (ddata->index) {
440 case 0:
441 case 1:
442 regmap_read(pc->regmap, PWM_CPT_EDGE(devicenum), &reg);
443 reg ^= PWM_CPT_EDGE_MASK;
444 regmap_write(pc->regmap, PWM_CPT_EDGE(devicenum), reg);
445
446 ddata->index++;
447 break;
448 case 2:
449 regmap_write(pc->regmap,
450 PWM_CPT_EDGE(devicenum),
451 CPT_EDGE_DISABLED);
452 wake_up(&ddata->wait);
453 break;
454 default:
455 dev_err(dev, "Internal error\n");
456 }
457
458 cpt_int_stat &= ~BIT_MASK(devicenum);
459
460 ret = IRQ_HANDLED;
461 }
462
463 /* Just ACK everything */
464 regmap_write(pc->regmap, PWM_INT_ACK, PWM_INT_ACK_MASK);
465
466 return ret;
467}
468
378fe115
LJ
469static int sti_pwm_probe_dt(struct sti_pwm_chip *pc)
470{
471 struct device *dev = pc->dev;
472 const struct reg_field *reg_fields;
473 struct device_node *np = dev->of_node;
474 struct sti_pwm_compat_data *cdata = pc->cdata;
09022e61 475 u32 num_devs;
3f0925b5 476 int ret;
378fe115 477
3f0925b5
LJ
478 ret = of_property_read_u32(np, "st,pwm-num-chan", &num_devs);
479 if (!ret)
480 cdata->pwm_num_devs = num_devs;
481
482 ret = of_property_read_u32(np, "st,capture-num-chan", &num_devs);
483 if (!ret)
484 cdata->cpt_num_devs = num_devs;
378fe115 485
85a834c4
LJ
486 if (!cdata->pwm_num_devs && !cdata->cpt_num_devs) {
487 dev_err(dev, "No channels configured\n");
488 return -EINVAL;
489 }
490
378fe115
LJ
491 reg_fields = cdata->reg_fields;
492
bf9cc80b
APS
493 pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap,
494 reg_fields[PWMCLK_PRESCALE_LOW]);
495 if (IS_ERR(pc->prescale_low))
496 return PTR_ERR(pc->prescale_low);
497
498 pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap,
499 reg_fields[PWMCLK_PRESCALE_HIGH]);
500 if (IS_ERR(pc->prescale_high))
501 return PTR_ERR(pc->prescale_high);
378fe115 502
378fe115 503
c5f94ae6
LJ
504 pc->pwm_out_en = devm_regmap_field_alloc(dev, pc->regmap,
505 reg_fields[PWM_OUT_EN]);
506 if (IS_ERR(pc->pwm_out_en))
507 return PTR_ERR(pc->pwm_out_en);
508
c97267ae
LJ
509 pc->pwm_cpt_en = devm_regmap_field_alloc(dev, pc->regmap,
510 reg_fields[PWM_CPT_EN]);
511 if (IS_ERR(pc->pwm_cpt_en))
512 return PTR_ERR(pc->pwm_cpt_en);
513
c5f94ae6
LJ
514 pc->pwm_cpt_int_en = devm_regmap_field_alloc(dev, pc->regmap,
515 reg_fields[PWM_CPT_INT_EN]);
516 if (IS_ERR(pc->pwm_cpt_int_en))
517 return PTR_ERR(pc->pwm_cpt_int_en);
378fe115 518
25eb5380
LJ
519 pc->pwm_cpt_int_stat = devm_regmap_field_alloc(dev, pc->regmap,
520 reg_fields[PWM_CPT_INT_STAT]);
521 if (PTR_ERR_OR_ZERO(pc->pwm_cpt_int_stat))
522 return PTR_ERR(pc->pwm_cpt_int_stat);
523
378fe115
LJ
524 return 0;
525}
526
527static const struct regmap_config sti_pwm_regmap_config = {
528 .reg_bits = 32,
529 .val_bits = 32,
530 .reg_stride = 4,
531};
532
533static int sti_pwm_probe(struct platform_device *pdev)
534{
535 struct device *dev = &pdev->dev;
536 struct sti_pwm_compat_data *cdata;
537 struct sti_pwm_chip *pc;
538 struct resource *res;
3f0925b5 539 unsigned int i;
25eb5380 540 int irq, ret;
378fe115
LJ
541
542 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
543 if (!pc)
544 return -ENOMEM;
545
546 cdata = devm_kzalloc(dev, sizeof(*cdata), GFP_KERNEL);
547 if (!cdata)
548 return -ENOMEM;
549
550 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
551
552 pc->mmio = devm_ioremap_resource(dev, res);
553 if (IS_ERR(pc->mmio))
554 return PTR_ERR(pc->mmio);
555
556 pc->regmap = devm_regmap_init_mmio(dev, pc->mmio,
557 &sti_pwm_regmap_config);
558 if (IS_ERR(pc->regmap))
559 return PTR_ERR(pc->regmap);
560
25eb5380
LJ
561 irq = platform_get_irq(pdev, 0);
562 if (irq < 0) {
563 dev_err(&pdev->dev, "Failed to obtain IRQ\n");
564 return irq;
565 }
566
567 ret = devm_request_irq(&pdev->dev, irq, sti_pwm_interrupt, 0,
568 pdev->name, pc);
569 if (ret < 0) {
570 dev_err(&pdev->dev, "Failed to request IRQ\n");
571 return ret;
572 }
573
378fe115
LJ
574 /*
575 * Setup PWM data with default values: some values could be replaced
576 * with specific ones provided from Device Tree.
577 */
578 cdata->reg_fields = &sti_pwm_regfields[0];
579 cdata->max_prescale = 0xff;
580 cdata->max_pwm_cnt = 255;
85a834c4 581 cdata->pwm_num_devs = 0;
3f0925b5 582 cdata->cpt_num_devs = 0;
378fe115
LJ
583
584 pc->cdata = cdata;
585 pc->dev = dev;
6ad6b838
APS
586 pc->en_count = 0;
587 mutex_init(&pc->sti_pwm_lock);
378fe115
LJ
588
589 ret = sti_pwm_probe_dt(pc);
590 if (ret)
591 return ret;
592
85a834c4
LJ
593 if (!cdata->pwm_num_devs)
594 goto skip_pwm;
595
c5f94ae6
LJ
596 pc->pwm_clk = of_clk_get_by_name(dev->of_node, "pwm");
597 if (IS_ERR(pc->pwm_clk)) {
378fe115 598 dev_err(dev, "failed to get PWM clock\n");
c5f94ae6 599 return PTR_ERR(pc->pwm_clk);
378fe115
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600 }
601
c5f94ae6 602 ret = clk_prepare(pc->pwm_clk);
378fe115
LJ
603 if (ret) {
604 dev_err(dev, "failed to prepare clock\n");
605 return ret;
606 }
607
85a834c4
LJ
608skip_pwm:
609 if (!cdata->cpt_num_devs)
610 goto skip_cpt;
611
d66a928d
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612 pc->cpt_clk = of_clk_get_by_name(dev->of_node, "capture");
613 if (IS_ERR(pc->cpt_clk)) {
614 dev_err(dev, "failed to get PWM capture clock\n");
615 return PTR_ERR(pc->cpt_clk);
616 }
617
618 ret = clk_prepare(pc->cpt_clk);
619 if (ret) {
620 dev_err(dev, "failed to prepare clock\n");
621 return ret;
622 }
623
85a834c4 624skip_cpt:
378fe115
LJ
625 pc->chip.dev = dev;
626 pc->chip.ops = &sti_pwm_ops;
627 pc->chip.base = -1;
3f0925b5 628 pc->chip.npwm = pc->cdata->pwm_num_devs;
378fe115
LJ
629 pc->chip.can_sleep = true;
630
631 ret = pwmchip_add(&pc->chip);
632 if (ret < 0) {
c5f94ae6 633 clk_unprepare(pc->pwm_clk);
d66a928d 634 clk_unprepare(pc->cpt_clk);
378fe115
LJ
635 return ret;
636 }
637
3f0925b5
LJ
638 for (i = 0; i < cdata->cpt_num_devs; i++) {
639 struct sti_cpt_ddata *ddata;
640
641 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
642 if (!ddata)
643 return -ENOMEM;
644
645 init_waitqueue_head(&ddata->wait);
646 mutex_init(&ddata->lock);
647
648 pwm_set_chip_data(&pc->chip.pwms[i], ddata);
649 }
650
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651 platform_set_drvdata(pdev, pc);
652
653 return 0;
654}
655
656static int sti_pwm_remove(struct platform_device *pdev)
657{
658 struct sti_pwm_chip *pc = platform_get_drvdata(pdev);
659 unsigned int i;
660
3f0925b5 661 for (i = 0; i < pc->cdata->pwm_num_devs; i++)
378fe115
LJ
662 pwm_disable(&pc->chip.pwms[i]);
663
c5f94ae6 664 clk_unprepare(pc->pwm_clk);
d66a928d 665 clk_unprepare(pc->cpt_clk);
378fe115
LJ
666
667 return pwmchip_remove(&pc->chip);
668}
669
670static const struct of_device_id sti_pwm_of_match[] = {
671 { .compatible = "st,sti-pwm", },
672 { /* sentinel */ }
673};
674MODULE_DEVICE_TABLE(of, sti_pwm_of_match);
675
676static struct platform_driver sti_pwm_driver = {
677 .driver = {
678 .name = "sti-pwm",
679 .of_match_table = sti_pwm_of_match,
680 },
681 .probe = sti_pwm_probe,
682 .remove = sti_pwm_remove,
683};
684module_platform_driver(sti_pwm_driver);
685
686MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>");
687MODULE_DESCRIPTION("STMicroelectronics ST PWM driver");
688MODULE_LICENSE("GPL");