Commit | Line | Data |
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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
378fe115 | 2 | /* |
7d8a600c LJ |
3 | * PWM device driver for ST SoCs |
4 | * | |
5 | * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited | |
378fe115 | 6 | * |
7d8a600c LJ |
7 | * Author: Ajit Pal Singh <ajitpal.singh@st.com> |
8 | * Lee Jones <lee.jones@linaro.org> | |
378fe115 LJ |
9 | */ |
10 | ||
378fe115 | 11 | #include <linux/clk.h> |
3f0925b5 | 12 | #include <linux/interrupt.h> |
378fe115 LJ |
13 | #include <linux/math64.h> |
14 | #include <linux/mfd/syscon.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/of.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/pwm.h> | |
19 | #include <linux/regmap.h> | |
3f0925b5 | 20 | #include <linux/sched.h> |
378fe115 LJ |
21 | #include <linux/slab.h> |
22 | #include <linux/time.h> | |
3f0925b5 | 23 | #include <linux/wait.h> |
378fe115 | 24 | |
c5f94ae6 | 25 | #define PWM_OUT_VAL(x) (0x00 + (4 * (x))) /* Device's Duty Cycle register */ |
f66d78fa LJ |
26 | #define PWM_CPT_VAL(x) (0x10 + (4 * (x))) /* Capture value */ |
27 | #define PWM_CPT_EDGE(x) (0x30 + (4 * (x))) /* Edge to capture on */ | |
c5f94ae6 LJ |
28 | |
29 | #define STI_PWM_CTRL 0x50 /* Control/Config register */ | |
30 | #define STI_INT_EN 0x54 /* Interrupt Enable/Disable register */ | |
f66d78fa | 31 | #define STI_INT_STA 0x58 /* Interrupt Status register */ |
7d8a600c LJ |
32 | #define PWM_INT_ACK 0x5c |
33 | #define PWM_PRESCALE_LOW_MASK 0x0f | |
34 | #define PWM_PRESCALE_HIGH_MASK 0xf0 | |
35 | #define PWM_CPT_EDGE_MASK 0x03 | |
36 | #define PWM_INT_ACK_MASK 0x1ff | |
f66d78fa | 37 | |
7d8a600c LJ |
38 | #define STI_MAX_CPT_DEVS 4 |
39 | #define CPT_DC_MAX 0xff | |
378fe115 LJ |
40 | |
41 | /* Regfield IDs */ | |
42 | enum { | |
c5f94ae6 | 43 | /* Bits in PWM_CTRL*/ |
bf9cc80b APS |
44 | PWMCLK_PRESCALE_LOW, |
45 | PWMCLK_PRESCALE_HIGH, | |
f66d78fa | 46 | CPTCLK_PRESCALE, |
c5f94ae6 LJ |
47 | |
48 | PWM_OUT_EN, | |
f66d78fa | 49 | PWM_CPT_EN, |
c5f94ae6 LJ |
50 | |
51 | PWM_CPT_INT_EN, | |
f66d78fa | 52 | PWM_CPT_INT_STAT, |
378fe115 LJ |
53 | |
54 | /* Keep last */ | |
55 | MAX_REGFIELDS | |
56 | }; | |
57 | ||
7d8a600c LJ |
58 | /* |
59 | * Each capture input can be programmed to detect rising-edge, falling-edge, | |
60 | * either edge or neither egde. | |
f66d78fa LJ |
61 | */ |
62 | enum sti_cpt_edge { | |
63 | CPT_EDGE_DISABLED, | |
64 | CPT_EDGE_RISING, | |
65 | CPT_EDGE_FALLING, | |
66 | CPT_EDGE_BOTH, | |
67 | }; | |
68 | ||
3f0925b5 LJ |
69 | struct sti_cpt_ddata { |
70 | u32 snapshot[3]; | |
71 | unsigned int index; | |
72 | struct mutex lock; | |
73 | wait_queue_head_t wait; | |
74 | }; | |
75 | ||
378fe115 | 76 | struct sti_pwm_compat_data { |
3f0925b5 LJ |
77 | unsigned int pwm_num_devs; |
78 | unsigned int cpt_num_devs; | |
378fe115 LJ |
79 | unsigned int max_pwm_cnt; |
80 | unsigned int max_prescale; | |
2d6812b4 | 81 | struct sti_cpt_ddata *ddata; |
378fe115 LJ |
82 | }; |
83 | ||
84 | struct sti_pwm_chip { | |
85 | struct device *dev; | |
c5f94ae6 | 86 | struct clk *pwm_clk; |
d66a928d | 87 | struct clk *cpt_clk; |
378fe115 LJ |
88 | struct regmap *regmap; |
89 | struct sti_pwm_compat_data *cdata; | |
bf9cc80b APS |
90 | struct regmap_field *prescale_low; |
91 | struct regmap_field *prescale_high; | |
c5f94ae6 | 92 | struct regmap_field *pwm_out_en; |
25eb5380 | 93 | struct regmap_field *pwm_cpt_en; |
c5f94ae6 | 94 | struct regmap_field *pwm_cpt_int_en; |
25eb5380 | 95 | struct regmap_field *pwm_cpt_int_stat; |
5165166e | 96 | struct pwm_device *cur; |
cd264b6a | 97 | unsigned long configured; |
6ad6b838 APS |
98 | unsigned int en_count; |
99 | struct mutex sti_pwm_lock; /* To sync between enable/disable calls */ | |
378fe115 LJ |
100 | void __iomem *mmio; |
101 | }; | |
102 | ||
103 | static const struct reg_field sti_pwm_regfields[MAX_REGFIELDS] = { | |
7d8a600c LJ |
104 | [PWMCLK_PRESCALE_LOW] = REG_FIELD(STI_PWM_CTRL, 0, 3), |
105 | [PWMCLK_PRESCALE_HIGH] = REG_FIELD(STI_PWM_CTRL, 11, 14), | |
106 | [CPTCLK_PRESCALE] = REG_FIELD(STI_PWM_CTRL, 4, 8), | |
107 | [PWM_OUT_EN] = REG_FIELD(STI_PWM_CTRL, 9, 9), | |
108 | [PWM_CPT_EN] = REG_FIELD(STI_PWM_CTRL, 10, 10), | |
109 | [PWM_CPT_INT_EN] = REG_FIELD(STI_INT_EN, 1, 4), | |
110 | [PWM_CPT_INT_STAT] = REG_FIELD(STI_INT_STA, 1, 4), | |
378fe115 LJ |
111 | }; |
112 | ||
113 | static inline struct sti_pwm_chip *to_sti_pwmchip(struct pwm_chip *chip) | |
114 | { | |
3f7dc7d8 | 115 | return pwmchip_get_drvdata(chip); |
378fe115 LJ |
116 | } |
117 | ||
118 | /* | |
3aacd3e1 | 119 | * Calculate the prescaler value corresponding to the period. |
378fe115 | 120 | */ |
3aacd3e1 APS |
121 | static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period, |
122 | unsigned int *prescale) | |
378fe115 LJ |
123 | { |
124 | struct sti_pwm_compat_data *cdata = pc->cdata; | |
d81738b7 | 125 | unsigned long clk_rate; |
7d8a600c | 126 | unsigned long value; |
3aacd3e1 | 127 | unsigned int ps; |
378fe115 | 128 | |
d81738b7 LJ |
129 | clk_rate = clk_get_rate(pc->pwm_clk); |
130 | if (!clk_rate) { | |
131 | dev_err(pc->dev, "failed to get clock rate\n"); | |
132 | return -EINVAL; | |
133 | } | |
134 | ||
378fe115 | 135 | /* |
7d8a600c | 136 | * prescale = ((period_ns * clk_rate) / (10^9 * (max_pwm_cnt + 1)) - 1 |
378fe115 | 137 | */ |
7d8a600c LJ |
138 | value = NSEC_PER_SEC / clk_rate; |
139 | value *= cdata->max_pwm_cnt + 1; | |
378fe115 | 140 | |
7d8a600c | 141 | if (period % value) |
3aacd3e1 | 142 | return -EINVAL; |
7d8a600c LJ |
143 | |
144 | ps = period / value - 1; | |
145 | if (ps > cdata->max_prescale) | |
146 | return -EINVAL; | |
147 | ||
3aacd3e1 APS |
148 | *prescale = ps; |
149 | ||
150 | return 0; | |
378fe115 LJ |
151 | } |
152 | ||
378fe115 | 153 | /* |
7d8a600c LJ |
154 | * For STiH4xx PWM IP, the PWM period is fixed to 256 local clock cycles. The |
155 | * only way to change the period (apart from changing the PWM input clock) is | |
156 | * to change the PWM clock prescaler. | |
157 | * | |
158 | * The prescaler is of 8 bits, so 256 prescaler values and hence 256 possible | |
159 | * period values are supported (for a particular clock rate). The requested | |
160 | * period will be applied only if it matches one of these 256 values. | |
378fe115 LJ |
161 | */ |
162 | static int sti_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |
7d8a600c | 163 | int duty_ns, int period_ns) |
378fe115 LJ |
164 | { |
165 | struct sti_pwm_chip *pc = to_sti_pwmchip(chip); | |
166 | struct sti_pwm_compat_data *cdata = pc->cdata; | |
7d8a600c | 167 | unsigned int ncfg, value, prescale = 0; |
5165166e | 168 | struct pwm_device *cur = pc->cur; |
378fe115 | 169 | struct device *dev = pc->dev; |
5165166e | 170 | bool period_same = false; |
7d8a600c | 171 | int ret; |
5165166e | 172 | |
cd264b6a | 173 | ncfg = hweight_long(pc->configured); |
5165166e APS |
174 | if (ncfg) |
175 | period_same = (period_ns == pwm_get_period(cur)); | |
176 | ||
7d8a600c LJ |
177 | /* |
178 | * Allow configuration changes if one of the following conditions | |
179 | * satisfy. | |
09022e61 | 180 | * 1. No devices have been configured. |
7d8a600c LJ |
181 | * 2. Only one device has been configured and the new request is for |
182 | * the same device. | |
183 | * 3. Only one device has been configured and the new request is for | |
184 | * a new device and period of the new device is same as the current | |
185 | * configured period. | |
09022e61 | 186 | * 4. More than one devices are configured and period of the new |
5165166e | 187 | * requestis the same as the current period. |
378fe115 | 188 | */ |
5165166e APS |
189 | if (!ncfg || |
190 | ((ncfg == 1) && (pwm->hwpwm == cur->hwpwm)) || | |
191 | ((ncfg == 1) && (pwm->hwpwm != cur->hwpwm) && period_same) || | |
192 | ((ncfg > 1) && period_same)) { | |
193 | /* Enable clock before writing to PWM registers. */ | |
c5f94ae6 | 194 | ret = clk_enable(pc->pwm_clk); |
5165166e APS |
195 | if (ret) |
196 | return ret; | |
197 | ||
d66a928d LJ |
198 | ret = clk_enable(pc->cpt_clk); |
199 | if (ret) | |
200 | return ret; | |
201 | ||
5165166e | 202 | if (!period_same) { |
3aacd3e1 APS |
203 | ret = sti_pwm_get_prescale(pc, period_ns, &prescale); |
204 | if (ret) | |
5165166e | 205 | goto clk_dis; |
5165166e | 206 | |
7d8a600c LJ |
207 | value = prescale & PWM_PRESCALE_LOW_MASK; |
208 | ||
209 | ret = regmap_field_write(pc->prescale_low, value); | |
5165166e APS |
210 | if (ret) |
211 | goto clk_dis; | |
212 | ||
7d8a600c LJ |
213 | value = (prescale & PWM_PRESCALE_HIGH_MASK) >> 4; |
214 | ||
215 | ret = regmap_field_write(pc->prescale_high, value); | |
5165166e APS |
216 | if (ret) |
217 | goto clk_dis; | |
218 | } | |
219 | ||
220 | /* | |
221 | * When PWMVal == 0, PWM pulse = 1 local clock cycle. | |
222 | * When PWMVal == max_pwm_count, | |
223 | * PWM pulse = (max_pwm_count + 1) local cycles, | |
224 | * that is continuous pulse: signal never goes low. | |
225 | */ | |
7d8a600c | 226 | value = cdata->max_pwm_cnt * duty_ns / period_ns; |
5165166e | 227 | |
7d8a600c | 228 | ret = regmap_write(pc->regmap, PWM_OUT_VAL(pwm->hwpwm), value); |
5165166e APS |
229 | if (ret) |
230 | goto clk_dis; | |
231 | ||
c5f94ae6 | 232 | ret = regmap_field_write(pc->pwm_cpt_int_en, 0); |
5165166e | 233 | |
cd264b6a | 234 | set_bit(pwm->hwpwm, &pc->configured); |
5165166e APS |
235 | pc->cur = pwm; |
236 | ||
7d8a600c LJ |
237 | dev_dbg(dev, "prescale:%u, period:%i, duty:%i, value:%u\n", |
238 | prescale, period_ns, duty_ns, value); | |
5165166e | 239 | } else { |
378fe115 LJ |
240 | return -EINVAL; |
241 | } | |
242 | ||
378fe115 | 243 | clk_dis: |
c5f94ae6 | 244 | clk_disable(pc->pwm_clk); |
d66a928d | 245 | clk_disable(pc->cpt_clk); |
378fe115 LJ |
246 | return ret; |
247 | } | |
248 | ||
249 | static int sti_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
250 | { | |
251 | struct sti_pwm_chip *pc = to_sti_pwmchip(chip); | |
252 | struct device *dev = pc->dev; | |
6ad6b838 | 253 | int ret = 0; |
378fe115 | 254 | |
6ad6b838 | 255 | /* |
7d8a600c LJ |
256 | * Since we have a common enable for all PWM devices, do not enable if |
257 | * already enabled. | |
6ad6b838 APS |
258 | */ |
259 | mutex_lock(&pc->sti_pwm_lock); | |
7d8a600c | 260 | |
6ad6b838 | 261 | if (!pc->en_count) { |
c5f94ae6 | 262 | ret = clk_enable(pc->pwm_clk); |
6ad6b838 APS |
263 | if (ret) |
264 | goto out; | |
378fe115 | 265 | |
d66a928d LJ |
266 | ret = clk_enable(pc->cpt_clk); |
267 | if (ret) | |
268 | goto out; | |
269 | ||
c5f94ae6 | 270 | ret = regmap_field_write(pc->pwm_out_en, 1); |
6ad6b838 | 271 | if (ret) { |
7d8a600c LJ |
272 | dev_err(dev, "failed to enable PWM device %u: %d\n", |
273 | pwm->hwpwm, ret); | |
6ad6b838 APS |
274 | goto out; |
275 | } | |
276 | } | |
7d8a600c | 277 | |
6ad6b838 | 278 | pc->en_count++; |
7d8a600c | 279 | |
6ad6b838 APS |
280 | out: |
281 | mutex_unlock(&pc->sti_pwm_lock); | |
378fe115 LJ |
282 | return ret; |
283 | } | |
284 | ||
285 | static void sti_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
286 | { | |
287 | struct sti_pwm_chip *pc = to_sti_pwmchip(chip); | |
378fe115 | 288 | |
6ad6b838 | 289 | mutex_lock(&pc->sti_pwm_lock); |
7d8a600c | 290 | |
6ad6b838 APS |
291 | if (--pc->en_count) { |
292 | mutex_unlock(&pc->sti_pwm_lock); | |
293 | return; | |
294 | } | |
7d8a600c | 295 | |
c5f94ae6 | 296 | regmap_field_write(pc->pwm_out_en, 0); |
378fe115 | 297 | |
c5f94ae6 | 298 | clk_disable(pc->pwm_clk); |
d66a928d | 299 | clk_disable(pc->cpt_clk); |
7d8a600c | 300 | |
6ad6b838 | 301 | mutex_unlock(&pc->sti_pwm_lock); |
378fe115 LJ |
302 | } |
303 | ||
cd264b6a APS |
304 | static void sti_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
305 | { | |
306 | struct sti_pwm_chip *pc = to_sti_pwmchip(chip); | |
307 | ||
308 | clear_bit(pwm->hwpwm, &pc->configured); | |
309 | } | |
310 | ||
c97267ae LJ |
311 | static int sti_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, |
312 | struct pwm_capture *result, unsigned long timeout) | |
313 | { | |
314 | struct sti_pwm_chip *pc = to_sti_pwmchip(chip); | |
315 | struct sti_pwm_compat_data *cdata = pc->cdata; | |
2d6812b4 | 316 | struct sti_cpt_ddata *ddata = &cdata->ddata[pwm->hwpwm]; |
c97267ae LJ |
317 | struct device *dev = pc->dev; |
318 | unsigned int effective_ticks; | |
319 | unsigned long long high, low; | |
320 | int ret; | |
321 | ||
322 | if (pwm->hwpwm >= cdata->cpt_num_devs) { | |
323 | dev_err(dev, "device %u is not valid\n", pwm->hwpwm); | |
324 | return -EINVAL; | |
325 | } | |
326 | ||
327 | mutex_lock(&ddata->lock); | |
328 | ddata->index = 0; | |
329 | ||
330 | /* Prepare capture measurement */ | |
331 | regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_RISING); | |
332 | regmap_field_write(pc->pwm_cpt_int_en, BIT(pwm->hwpwm)); | |
333 | ||
334 | /* Enable capture */ | |
335 | ret = regmap_field_write(pc->pwm_cpt_en, 1); | |
336 | if (ret) { | |
337 | dev_err(dev, "failed to enable PWM capture %u: %d\n", | |
338 | pwm->hwpwm, ret); | |
339 | goto out; | |
340 | } | |
341 | ||
342 | ret = wait_event_interruptible_timeout(ddata->wait, ddata->index > 1, | |
343 | msecs_to_jiffies(timeout)); | |
344 | ||
345 | regmap_write(pc->regmap, PWM_CPT_EDGE(pwm->hwpwm), CPT_EDGE_DISABLED); | |
346 | ||
347 | if (ret == -ERESTARTSYS) | |
348 | goto out; | |
349 | ||
350 | switch (ddata->index) { | |
351 | case 0: | |
352 | case 1: | |
353 | /* | |
354 | * Getting here could mean: | |
355 | * - input signal is constant of less than 1 Hz | |
356 | * - there is no input signal at all | |
357 | * | |
358 | * In such case the frequency is rounded down to 0 | |
359 | */ | |
360 | result->period = 0; | |
361 | result->duty_cycle = 0; | |
362 | ||
363 | break; | |
364 | ||
365 | case 2: | |
366 | /* We have everying we need */ | |
367 | high = ddata->snapshot[1] - ddata->snapshot[0]; | |
368 | low = ddata->snapshot[2] - ddata->snapshot[1]; | |
369 | ||
370 | effective_ticks = clk_get_rate(pc->cpt_clk); | |
371 | ||
372 | result->period = (high + low) * NSEC_PER_SEC; | |
373 | result->period /= effective_ticks; | |
374 | ||
375 | result->duty_cycle = high * NSEC_PER_SEC; | |
376 | result->duty_cycle /= effective_ticks; | |
377 | ||
378 | break; | |
379 | ||
380 | default: | |
381 | dev_err(dev, "internal error\n"); | |
382 | break; | |
383 | } | |
384 | ||
385 | out: | |
386 | /* Disable capture */ | |
387 | regmap_field_write(pc->pwm_cpt_en, 0); | |
388 | ||
389 | mutex_unlock(&ddata->lock); | |
390 | return ret; | |
391 | } | |
392 | ||
b2e60b32 UKK |
393 | static int sti_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
394 | const struct pwm_state *state) | |
395 | { | |
5f623835 UKK |
396 | struct sti_pwm_chip *pc = to_sti_pwmchip(chip); |
397 | struct sti_pwm_compat_data *cdata = pc->cdata; | |
398 | struct device *dev = pc->dev; | |
b2e60b32 UKK |
399 | int err; |
400 | ||
5f623835 UKK |
401 | if (pwm->hwpwm >= cdata->pwm_num_devs) { |
402 | dev_err(dev, "device %u is not valid for pwm mode\n", | |
403 | pwm->hwpwm); | |
404 | return -EINVAL; | |
405 | } | |
406 | ||
b2e60b32 UKK |
407 | if (state->polarity != PWM_POLARITY_NORMAL) |
408 | return -EINVAL; | |
409 | ||
410 | if (!state->enabled) { | |
411 | if (pwm->state.enabled) | |
412 | sti_pwm_disable(chip, pwm); | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
80943bbd | 417 | err = sti_pwm_config(chip, pwm, state->duty_cycle, state->period); |
b2e60b32 UKK |
418 | if (err) |
419 | return err; | |
420 | ||
421 | if (!pwm->state.enabled) | |
422 | err = sti_pwm_enable(chip, pwm); | |
423 | ||
424 | return err; | |
425 | } | |
426 | ||
378fe115 | 427 | static const struct pwm_ops sti_pwm_ops = { |
c97267ae | 428 | .capture = sti_pwm_capture, |
b2e60b32 | 429 | .apply = sti_pwm_apply, |
cd264b6a | 430 | .free = sti_pwm_free, |
378fe115 LJ |
431 | }; |
432 | ||
25eb5380 LJ |
433 | static irqreturn_t sti_pwm_interrupt(int irq, void *data) |
434 | { | |
435 | struct sti_pwm_chip *pc = data; | |
436 | struct device *dev = pc->dev; | |
437 | struct sti_cpt_ddata *ddata; | |
438 | int devicenum; | |
439 | unsigned int cpt_int_stat; | |
440 | unsigned int reg; | |
441 | int ret = IRQ_NONE; | |
442 | ||
443 | ret = regmap_field_read(pc->pwm_cpt_int_stat, &cpt_int_stat); | |
444 | if (ret) | |
445 | return ret; | |
446 | ||
447 | while (cpt_int_stat) { | |
448 | devicenum = ffs(cpt_int_stat) - 1; | |
449 | ||
2d6812b4 | 450 | ddata = &pc->cdata->ddata[devicenum]; |
25eb5380 LJ |
451 | |
452 | /* | |
453 | * Capture input: | |
454 | * _______ _______ | |
455 | * | | | | | |
456 | * __| |_________________| |________ | |
457 | * ^0 ^1 ^2 | |
458 | * | |
7d8a600c LJ |
459 | * Capture start by the first available rising edge. When a |
460 | * capture event occurs, capture value (CPT_VALx) is stored, | |
461 | * index incremented, capture edge changed. | |
25eb5380 | 462 | * |
7d8a600c LJ |
463 | * After the capture, if the index > 1, we have collected the |
464 | * necessary data so we signal the thread waiting for it and | |
465 | * disable the capture by setting capture edge to none | |
25eb5380 LJ |
466 | */ |
467 | ||
468 | regmap_read(pc->regmap, | |
469 | PWM_CPT_VAL(devicenum), | |
470 | &ddata->snapshot[ddata->index]); | |
471 | ||
472 | switch (ddata->index) { | |
473 | case 0: | |
474 | case 1: | |
475 | regmap_read(pc->regmap, PWM_CPT_EDGE(devicenum), ®); | |
476 | reg ^= PWM_CPT_EDGE_MASK; | |
477 | regmap_write(pc->regmap, PWM_CPT_EDGE(devicenum), reg); | |
478 | ||
479 | ddata->index++; | |
480 | break; | |
7d8a600c | 481 | |
25eb5380 LJ |
482 | case 2: |
483 | regmap_write(pc->regmap, | |
484 | PWM_CPT_EDGE(devicenum), | |
485 | CPT_EDGE_DISABLED); | |
486 | wake_up(&ddata->wait); | |
487 | break; | |
7d8a600c | 488 | |
25eb5380 LJ |
489 | default: |
490 | dev_err(dev, "Internal error\n"); | |
491 | } | |
492 | ||
493 | cpt_int_stat &= ~BIT_MASK(devicenum); | |
494 | ||
495 | ret = IRQ_HANDLED; | |
496 | } | |
497 | ||
498 | /* Just ACK everything */ | |
499 | regmap_write(pc->regmap, PWM_INT_ACK, PWM_INT_ACK_MASK); | |
500 | ||
501 | return ret; | |
502 | } | |
503 | ||
3025c9c6 | 504 | static int sti_pwm_probe_regmap(struct sti_pwm_chip *pc) |
378fe115 LJ |
505 | { |
506 | struct device *dev = pc->dev; | |
378fe115 | 507 | |
bf9cc80b | 508 | pc->prescale_low = devm_regmap_field_alloc(dev, pc->regmap, |
354bf751 | 509 | sti_pwm_regfields[PWMCLK_PRESCALE_LOW]); |
bf9cc80b APS |
510 | if (IS_ERR(pc->prescale_low)) |
511 | return PTR_ERR(pc->prescale_low); | |
512 | ||
513 | pc->prescale_high = devm_regmap_field_alloc(dev, pc->regmap, | |
354bf751 | 514 | sti_pwm_regfields[PWMCLK_PRESCALE_HIGH]); |
bf9cc80b APS |
515 | if (IS_ERR(pc->prescale_high)) |
516 | return PTR_ERR(pc->prescale_high); | |
378fe115 | 517 | |
c5f94ae6 | 518 | pc->pwm_out_en = devm_regmap_field_alloc(dev, pc->regmap, |
354bf751 | 519 | sti_pwm_regfields[PWM_OUT_EN]); |
c5f94ae6 LJ |
520 | if (IS_ERR(pc->pwm_out_en)) |
521 | return PTR_ERR(pc->pwm_out_en); | |
522 | ||
c97267ae | 523 | pc->pwm_cpt_en = devm_regmap_field_alloc(dev, pc->regmap, |
354bf751 | 524 | sti_pwm_regfields[PWM_CPT_EN]); |
c97267ae LJ |
525 | if (IS_ERR(pc->pwm_cpt_en)) |
526 | return PTR_ERR(pc->pwm_cpt_en); | |
527 | ||
c5f94ae6 | 528 | pc->pwm_cpt_int_en = devm_regmap_field_alloc(dev, pc->regmap, |
354bf751 | 529 | sti_pwm_regfields[PWM_CPT_INT_EN]); |
c5f94ae6 LJ |
530 | if (IS_ERR(pc->pwm_cpt_int_en)) |
531 | return PTR_ERR(pc->pwm_cpt_int_en); | |
378fe115 | 532 | |
25eb5380 | 533 | pc->pwm_cpt_int_stat = devm_regmap_field_alloc(dev, pc->regmap, |
354bf751 | 534 | sti_pwm_regfields[PWM_CPT_INT_STAT]); |
25eb5380 LJ |
535 | if (PTR_ERR_OR_ZERO(pc->pwm_cpt_int_stat)) |
536 | return PTR_ERR(pc->pwm_cpt_int_stat); | |
537 | ||
378fe115 LJ |
538 | return 0; |
539 | } | |
540 | ||
541 | static const struct regmap_config sti_pwm_regmap_config = { | |
542 | .reg_bits = 32, | |
543 | .val_bits = 32, | |
544 | .reg_stride = 4, | |
545 | }; | |
546 | ||
547 | static int sti_pwm_probe(struct platform_device *pdev) | |
548 | { | |
549 | struct device *dev = &pdev->dev; | |
3f7dc7d8 UKK |
550 | struct device_node *np = dev->of_node; |
551 | u32 num_devs; | |
552 | unsigned int pwm_num_devs = 0; | |
553 | unsigned int cpt_num_devs = 0; | |
378fe115 | 554 | struct sti_pwm_compat_data *cdata; |
54272761 | 555 | struct pwm_chip *chip; |
378fe115 | 556 | struct sti_pwm_chip *pc; |
3f0925b5 | 557 | unsigned int i; |
25eb5380 | 558 | int irq, ret; |
378fe115 | 559 | |
3f7dc7d8 UKK |
560 | ret = of_property_read_u32(np, "st,pwm-num-chan", &num_devs); |
561 | if (!ret) | |
562 | pwm_num_devs = num_devs; | |
563 | ||
564 | ret = of_property_read_u32(np, "st,capture-num-chan", &num_devs); | |
565 | if (!ret) | |
566 | cpt_num_devs = num_devs; | |
567 | ||
3025c9c6 UKK |
568 | if (!pwm_num_devs && !cpt_num_devs) |
569 | return dev_err_probe(dev, -EINVAL, "No channels configured\n"); | |
3f7dc7d8 UKK |
570 | |
571 | chip = devm_pwmchip_alloc(dev, max(pwm_num_devs, cpt_num_devs), sizeof(*pc)); | |
572 | if (IS_ERR(chip)) | |
573 | return PTR_ERR(chip); | |
574 | pc = to_sti_pwmchip(chip); | |
378fe115 LJ |
575 | |
576 | cdata = devm_kzalloc(dev, sizeof(*cdata), GFP_KERNEL); | |
577 | if (!cdata) | |
578 | return -ENOMEM; | |
579 | ||
728cd3e6 | 580 | pc->mmio = devm_platform_ioremap_resource(pdev, 0); |
378fe115 LJ |
581 | if (IS_ERR(pc->mmio)) |
582 | return PTR_ERR(pc->mmio); | |
583 | ||
584 | pc->regmap = devm_regmap_init_mmio(dev, pc->mmio, | |
585 | &sti_pwm_regmap_config); | |
586 | if (IS_ERR(pc->regmap)) | |
3025c9c6 UKK |
587 | return dev_err_probe(dev, PTR_ERR(pc->regmap), |
588 | "Failed to initialize regmap\n"); | |
378fe115 | 589 | |
25eb5380 | 590 | irq = platform_get_irq(pdev, 0); |
fb5a35db | 591 | if (irq < 0) |
25eb5380 | 592 | return irq; |
25eb5380 LJ |
593 | |
594 | ret = devm_request_irq(&pdev->dev, irq, sti_pwm_interrupt, 0, | |
595 | pdev->name, pc); | |
3025c9c6 UKK |
596 | if (ret < 0) |
597 | dev_err_probe(&pdev->dev, ret, "Failed to request IRQ\n"); | |
25eb5380 | 598 | |
378fe115 LJ |
599 | /* |
600 | * Setup PWM data with default values: some values could be replaced | |
601 | * with specific ones provided from Device Tree. | |
602 | */ | |
378fe115 | 603 | cdata->max_prescale = 0xff; |
7d8a600c | 604 | cdata->max_pwm_cnt = 255; |
3f7dc7d8 UKK |
605 | cdata->pwm_num_devs = pwm_num_devs; |
606 | cdata->cpt_num_devs = cpt_num_devs; | |
378fe115 LJ |
607 | |
608 | pc->cdata = cdata; | |
609 | pc->dev = dev; | |
6ad6b838 APS |
610 | pc->en_count = 0; |
611 | mutex_init(&pc->sti_pwm_lock); | |
378fe115 | 612 | |
3025c9c6 | 613 | ret = sti_pwm_probe_regmap(pc); |
378fe115 | 614 | if (ret) |
3025c9c6 | 615 | return dev_err_probe(dev, ret, "Failed to initialize regmap fields\n"); |
378fe115 | 616 | |
fd3ae02b | 617 | if (cdata->pwm_num_devs) { |
5bb0b194 | 618 | pc->pwm_clk = devm_clk_get_prepared(dev, "pwm"); |
3025c9c6 UKK |
619 | if (IS_ERR(pc->pwm_clk)) |
620 | return dev_err_probe(dev, PTR_ERR(pc->pwm_clk), | |
621 | "failed to get PWM clock\n"); | |
378fe115 LJ |
622 | } |
623 | ||
fd3ae02b | 624 | if (cdata->cpt_num_devs) { |
5bb0b194 | 625 | pc->cpt_clk = devm_clk_get_prepared(dev, "capture"); |
3025c9c6 UKK |
626 | if (IS_ERR(pc->cpt_clk)) |
627 | return dev_err_probe(dev, PTR_ERR(pc->cpt_clk), | |
628 | "failed to get PWM capture clock\n"); | |
d66a928d | 629 | |
2d6812b4 UKK |
630 | cdata->ddata = devm_kzalloc(dev, cdata->cpt_num_devs * sizeof(*cdata->ddata), GFP_KERNEL); |
631 | if (!cdata->ddata) | |
632 | return -ENOMEM; | |
d66a928d LJ |
633 | } |
634 | ||
54272761 | 635 | chip->ops = &sti_pwm_ops; |
378fe115 | 636 | |
3f0925b5 | 637 | for (i = 0; i < cdata->cpt_num_devs; i++) { |
2d6812b4 | 638 | struct sti_cpt_ddata *ddata = &cdata->ddata[i]; |
3f0925b5 LJ |
639 | |
640 | init_waitqueue_head(&ddata->wait); | |
641 | mutex_init(&ddata->lock); | |
2d6812b4 | 642 | } |
3f0925b5 | 643 | |
3025c9c6 UKK |
644 | ret = devm_pwmchip_add(dev, chip); |
645 | if (ret) | |
646 | return dev_err_probe(dev, ret, "Failed to register pwm chip\n"); | |
647 | ||
648 | return 0; | |
378fe115 LJ |
649 | } |
650 | ||
651 | static const struct of_device_id sti_pwm_of_match[] = { | |
652 | { .compatible = "st,sti-pwm", }, | |
653 | { /* sentinel */ } | |
654 | }; | |
655 | MODULE_DEVICE_TABLE(of, sti_pwm_of_match); | |
656 | ||
657 | static struct platform_driver sti_pwm_driver = { | |
658 | .driver = { | |
659 | .name = "sti-pwm", | |
660 | .of_match_table = sti_pwm_of_match, | |
661 | }, | |
662 | .probe = sti_pwm_probe, | |
378fe115 LJ |
663 | }; |
664 | module_platform_driver(sti_pwm_driver); | |
665 | ||
666 | MODULE_AUTHOR("Ajit Pal Singh <ajitpal.singh@st.com>"); | |
667 | MODULE_DESCRIPTION("STMicroelectronics ST PWM driver"); | |
668 | MODULE_LICENSE("GPL"); |