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ce20364b SH |
1 | /* |
2 | * ST Microelectronics SPEAr Pulse Width Modulator driver | |
3 | * | |
4 | * Copyright (C) 2012 ST Microelectronics | |
9cc23682 | 5 | * Shiraz Hashim <shiraz.linux.kernel@gmail.com> |
ce20364b SH |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/clk.h> | |
13 | #include <linux/err.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/ioport.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/math64.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/pwm.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/types.h> | |
24 | ||
25 | #define NUM_PWM 4 | |
26 | ||
27 | /* PWM registers and bits definitions */ | |
28 | #define PWMCR 0x00 /* Control Register */ | |
29 | #define PWMCR_PWM_ENABLE 0x1 | |
30 | #define PWMCR_PRESCALE_SHIFT 2 | |
31 | #define PWMCR_MIN_PRESCALE 0x00 | |
32 | #define PWMCR_MAX_PRESCALE 0x3FFF | |
33 | ||
34 | #define PWMDCR 0x04 /* Duty Cycle Register */ | |
35 | #define PWMDCR_MIN_DUTY 0x0001 | |
36 | #define PWMDCR_MAX_DUTY 0xFFFF | |
37 | ||
38 | #define PWMPCR 0x08 /* Period Register */ | |
39 | #define PWMPCR_MIN_PERIOD 0x0001 | |
40 | #define PWMPCR_MAX_PERIOD 0xFFFF | |
41 | ||
42 | /* Following only available on 13xx SoCs */ | |
43 | #define PWMMCR 0x3C /* Master Control Register */ | |
44 | #define PWMMCR_PWM_ENABLE 0x1 | |
45 | ||
46 | /** | |
47 | * struct spear_pwm_chip - struct representing pwm chip | |
48 | * | |
49 | * @mmio_base: base address of pwm chip | |
50 | * @clk: pointer to clk structure of pwm chip | |
51 | * @chip: linux pwm chip representation | |
ce20364b SH |
52 | */ |
53 | struct spear_pwm_chip { | |
54 | void __iomem *mmio_base; | |
55 | struct clk *clk; | |
56 | struct pwm_chip chip; | |
ce20364b SH |
57 | }; |
58 | ||
59 | static inline struct spear_pwm_chip *to_spear_pwm_chip(struct pwm_chip *chip) | |
60 | { | |
61 | return container_of(chip, struct spear_pwm_chip, chip); | |
62 | } | |
63 | ||
64 | static inline u32 spear_pwm_readl(struct spear_pwm_chip *chip, unsigned int num, | |
65 | unsigned long offset) | |
66 | { | |
67 | return readl_relaxed(chip->mmio_base + (num << 4) + offset); | |
68 | } | |
69 | ||
70 | static inline void spear_pwm_writel(struct spear_pwm_chip *chip, | |
71 | unsigned int num, unsigned long offset, | |
72 | unsigned long val) | |
73 | { | |
74 | writel_relaxed(val, chip->mmio_base + (num << 4) + offset); | |
75 | } | |
76 | ||
c9371360 AL |
77 | static int spear_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
78 | int duty_ns, int period_ns) | |
ce20364b SH |
79 | { |
80 | struct spear_pwm_chip *pc = to_spear_pwm_chip(chip); | |
81 | u64 val, div, clk_rate; | |
82 | unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc; | |
83 | int ret; | |
84 | ||
85 | /* | |
86 | * Find pv, dc and prescale to suit duty_ns and period_ns. This is done | |
87 | * according to formulas described below: | |
88 | * | |
89 | * period_ns = 10^9 * (PRESCALE + 1) * PV / PWM_CLK_RATE | |
90 | * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE | |
91 | * | |
92 | * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1)) | |
93 | * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1)) | |
94 | */ | |
95 | clk_rate = clk_get_rate(pc->clk); | |
96 | while (1) { | |
97 | div = 1000000000; | |
98 | div *= 1 + prescale; | |
99 | val = clk_rate * period_ns; | |
100 | pv = div64_u64(val, div); | |
101 | val = clk_rate * duty_ns; | |
102 | dc = div64_u64(val, div); | |
103 | ||
104 | /* if duty_ns and period_ns are not achievable then return */ | |
105 | if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY) | |
106 | return -EINVAL; | |
107 | ||
108 | /* | |
109 | * if pv and dc have crossed their upper limit, then increase | |
110 | * prescale and recalculate pv and dc. | |
111 | */ | |
112 | if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) { | |
113 | if (++prescale > PWMCR_MAX_PRESCALE) | |
114 | return -EINVAL; | |
115 | continue; | |
116 | } | |
117 | break; | |
118 | } | |
119 | ||
120 | /* | |
121 | * NOTE: the clock to PWM has to be enabled first before writing to the | |
122 | * registers. | |
123 | */ | |
124 | ret = clk_enable(pc->clk); | |
125 | if (ret) | |
126 | return ret; | |
127 | ||
128 | spear_pwm_writel(pc, pwm->hwpwm, PWMCR, | |
129 | prescale << PWMCR_PRESCALE_SHIFT); | |
130 | spear_pwm_writel(pc, pwm->hwpwm, PWMDCR, dc); | |
131 | spear_pwm_writel(pc, pwm->hwpwm, PWMPCR, pv); | |
132 | clk_disable(pc->clk); | |
133 | ||
134 | return 0; | |
135 | } | |
136 | ||
137 | static int spear_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
138 | { | |
139 | struct spear_pwm_chip *pc = to_spear_pwm_chip(chip); | |
140 | int rc = 0; | |
141 | u32 val; | |
142 | ||
143 | rc = clk_enable(pc->clk); | |
563861cd | 144 | if (rc) |
ce20364b SH |
145 | return rc; |
146 | ||
147 | val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); | |
148 | val |= PWMCR_PWM_ENABLE; | |
149 | spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); | |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
154 | static void spear_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
155 | { | |
156 | struct spear_pwm_chip *pc = to_spear_pwm_chip(chip); | |
157 | u32 val; | |
158 | ||
159 | val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR); | |
160 | val &= ~PWMCR_PWM_ENABLE; | |
161 | spear_pwm_writel(pc, pwm->hwpwm, PWMCR, val); | |
162 | ||
163 | clk_disable(pc->clk); | |
164 | } | |
165 | ||
166 | static const struct pwm_ops spear_pwm_ops = { | |
167 | .config = spear_pwm_config, | |
168 | .enable = spear_pwm_enable, | |
169 | .disable = spear_pwm_disable, | |
170 | .owner = THIS_MODULE, | |
171 | }; | |
172 | ||
173 | static int spear_pwm_probe(struct platform_device *pdev) | |
174 | { | |
175 | struct device_node *np = pdev->dev.of_node; | |
176 | struct spear_pwm_chip *pc; | |
ce20364b SH |
177 | int ret; |
178 | u32 val; | |
179 | ||
ce20364b | 180 | pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); |
9321fe9d | 181 | if (!pc) |
ce20364b | 182 | return -ENOMEM; |
ce20364b | 183 | |
21af4356 | 184 | pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); |
6d4294d1 TR |
185 | if (IS_ERR(pc->mmio_base)) |
186 | return PTR_ERR(pc->mmio_base); | |
ce20364b SH |
187 | |
188 | pc->clk = devm_clk_get(&pdev->dev, NULL); | |
189 | if (IS_ERR(pc->clk)) | |
190 | return PTR_ERR(pc->clk); | |
191 | ||
ce20364b SH |
192 | platform_set_drvdata(pdev, pc); |
193 | ||
194 | pc->chip.dev = &pdev->dev; | |
195 | pc->chip.ops = &spear_pwm_ops; | |
ce20364b SH |
196 | pc->chip.npwm = NUM_PWM; |
197 | ||
198 | ret = clk_prepare(pc->clk); | |
563861cd | 199 | if (ret) |
ce20364b SH |
200 | return ret; |
201 | ||
202 | if (of_device_is_compatible(np, "st,spear1340-pwm")) { | |
203 | ret = clk_enable(pc->clk); | |
563861cd | 204 | if (ret) { |
ce20364b SH |
205 | clk_unprepare(pc->clk); |
206 | return ret; | |
207 | } | |
208 | /* | |
209 | * Following enables PWM chip, channels would still be | |
210 | * enabled individually through their control register | |
211 | */ | |
212 | val = readl_relaxed(pc->mmio_base + PWMMCR); | |
213 | val |= PWMMCR_PWM_ENABLE; | |
214 | writel_relaxed(val, pc->mmio_base + PWMMCR); | |
215 | ||
216 | clk_disable(pc->clk); | |
217 | } | |
218 | ||
219 | ret = pwmchip_add(&pc->chip); | |
5b1e8e06 | 220 | if (ret < 0) { |
ce20364b SH |
221 | clk_unprepare(pc->clk); |
222 | dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); | |
223 | } | |
224 | ||
225 | return ret; | |
226 | } | |
227 | ||
228 | static int spear_pwm_remove(struct platform_device *pdev) | |
229 | { | |
230 | struct spear_pwm_chip *pc = platform_get_drvdata(pdev); | |
231 | int i; | |
232 | ||
233 | for (i = 0; i < NUM_PWM; i++) | |
234 | pwm_disable(&pc->chip.pwms[i]); | |
235 | ||
236 | /* clk was prepared in probe, hence unprepare it here */ | |
237 | clk_unprepare(pc->clk); | |
238 | return pwmchip_remove(&pc->chip); | |
239 | } | |
240 | ||
f1a8870a | 241 | static const struct of_device_id spear_pwm_of_match[] = { |
ce20364b SH |
242 | { .compatible = "st,spear320-pwm" }, |
243 | { .compatible = "st,spear1340-pwm" }, | |
244 | { } | |
245 | }; | |
246 | ||
247 | MODULE_DEVICE_TABLE(of, spear_pwm_of_match); | |
248 | ||
249 | static struct platform_driver spear_pwm_driver = { | |
250 | .driver = { | |
251 | .name = "spear-pwm", | |
252 | .of_match_table = spear_pwm_of_match, | |
253 | }, | |
254 | .probe = spear_pwm_probe, | |
255 | .remove = spear_pwm_remove, | |
256 | }; | |
257 | ||
258 | module_platform_driver(spear_pwm_driver); | |
259 | ||
260 | MODULE_LICENSE("GPL"); | |
9cc23682 | 261 | MODULE_AUTHOR("Shiraz Hashim <shiraz.linux.kernel@gmail.com>"); |
ce20364b SH |
262 | MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.com>"); |
263 | MODULE_ALIAS("platform:spear-pwm"); |