[linux-block.git] / drivers / pwm / pwm-sl28cpld.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * sl28cpld PWM driver
 *
 * Copyright (c) 2020 Michael Walle <michael@walle.cc>
 *
 * There is no public datasheet available for this PWM core. But it is easy
 * enough to be briefly explained. It consists of one 8-bit counter. The PWM
 * supports four distinct frequencies by selecting when to reset the counter.
 * With the prescaler setting you can select which bit of the counter is used
 * to reset it. This implies that the higher the frequency the less remaining
 * bits are available for the actual counter.
 *
 * Let cnt[7:0] be the counter, clocked at 32kHz:
 * +-----------+--------+--------------+-----------+---------------+
 * | prescaler |  reset | counter bits | frequency | period length |
 * +-----------+--------+--------------+-----------+---------------+
 * |         0 | cnt[7] |     cnt[6:0] |    250 Hz |    4000000 ns |
 * |         1 | cnt[6] |     cnt[5:0] |    500 Hz |    2000000 ns |
 * |         2 | cnt[5] |     cnt[4:0] |     1 kHz |    1000000 ns |
 * |         3 | cnt[4] |     cnt[3:0] |     2 kHz |     500000 ns |
 * +-----------+--------+--------------+-----------+---------------+
 *
 * Limitations:
 * - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
 * - The hardware cannot atomically set the prescaler and the counter value,
 *   which might lead to glitches and inconsistent states if a write fails.
 * - The counter is not reset if you switch the prescaler which leads
 *   to glitches, too.
 * - The duty cycle will switch immediately and not after a complete cycle.
 * - Depending on the actual implementation, disabling the PWM might have
 *   side effects. For example, if the output pin is shared with a GPIO pin
 *   it will automatically switch back to GPIO mode.
 */

#include <linux/bitfield.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/regmap.h>

/*
 * PWM timer block registers.
 */
#define SL28CPLD_PWM_CTRL			0x00
#define   SL28CPLD_PWM_CTRL_ENABLE		BIT(7)
#define   SL28CPLD_PWM_CTRL_PRESCALER_MASK	GENMASK(1, 0)
#define SL28CPLD_PWM_CYCLE			0x01
#define   SL28CPLD_PWM_CYCLE_MAX		GENMASK(6, 0)

#define SL28CPLD_PWM_CLK			32000 /* 32 kHz */
#define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler)	(1 << (7 - (prescaler)))
#define SL28CPLD_PWM_PERIOD(prescaler) \
	(NSEC_PER_SEC / SL28CPLD_PWM_CLK * SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler))

/*
 * We calculate the duty cycle like this:
 *   duty_cycle_ns = pwm_cycle_reg * max_period_ns / max_duty_cycle
 *
 * With
 *   max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC
 *   max_duty_cycle = 1 << (7 - prescaler)
 * this then simplifies to:
 *   duty_cycle_ns = pwm_cycle_reg / SL28CPLD_PWM_CLK * NSEC_PER_SEC
 *                 = NSEC_PER_SEC / SL28CPLD_PWM_CLK * pwm_cycle_reg
 *
 * NSEC_PER_SEC is a multiple of SL28CPLD_PWM_CLK, therefore we're not losing
 * precision by doing the divison first.
 */
#define SL28CPLD_PWM_TO_DUTY_CYCLE(reg) \
	(NSEC_PER_SEC / SL28CPLD_PWM_CLK * (reg))
#define SL28CPLD_PWM_FROM_DUTY_CYCLE(duty_cycle) \
	(DIV_ROUND_DOWN_ULL((duty_cycle), NSEC_PER_SEC / SL28CPLD_PWM_CLK))

#define sl28cpld_pwm_read(priv, reg, val) \
	regmap_read((priv)->regmap, (priv)->offset + (reg), (val))
#define sl28cpld_pwm_write(priv, reg, val) \
	regmap_write((priv)->regmap, (priv)->offset + (reg), (val))

struct sl28cpld_pwm {
	struct pwm_chip pwm_chip;
	struct regmap *regmap;
	u32 offset;
};
#define sl28cpld_pwm_from_chip(_chip) \
	container_of(_chip, struct sl28cpld_pwm, pwm_chip)

static int sl28cpld_pwm_get_state(struct pwm_chip *chip,
				  struct pwm_device *pwm,
				  struct pwm_state *state)
{
	struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
	unsigned int reg;
	int prescaler;

	sl28cpld_pwm_read(priv, SL28CPLD_PWM_CTRL, &reg);

	state->enabled = reg & SL28CPLD_PWM_CTRL_ENABLE;

	prescaler = FIELD_GET(SL28CPLD_PWM_CTRL_PRESCALER_MASK, reg);
	state->period = SL28CPLD_PWM_PERIOD(prescaler);

	sl28cpld_pwm_read(priv, SL28CPLD_PWM_CYCLE, &reg);
	state->duty_cycle = SL28CPLD_PWM_TO_DUTY_CYCLE(reg);
	state->polarity = PWM_POLARITY_NORMAL;

	/*
	 * Sanitize values for the PWM core. Depending on the prescaler it
	 * might happen that we calculate a duty_cycle greater than the actual
	 * period. This might happen if someone (e.g. the bootloader) sets an
	 * invalid combination of values. The behavior of the hardware is
	 * undefined in this case. But we need to report sane values back to
	 * the PWM core.
	 */
	state->duty_cycle = min(state->duty_cycle, state->period);

	return 0;
}

static int sl28cpld_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			      const struct pwm_state *state)
{
	struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
	unsigned int cycle, prescaler;
	bool write_duty_cycle_first;
	int ret;
	u8 ctrl;

	/* Polarity inversion is not supported */
	if (state->polarity != PWM_POLARITY_NORMAL)
		return -EINVAL;

	/*
	 * Calculate the prescaler. Pick the biggest period that isn't
	 * bigger than the requested period.
	 */
	prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period);
	prescaler = order_base_2(prescaler);

	if (prescaler > field_max(SL28CPLD_PWM_CTRL_PRESCALER_MASK))
		return -ERANGE;

	ctrl = FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, prescaler);
	if (state->enabled)
		ctrl |= SL28CPLD_PWM_CTRL_ENABLE;

	cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle);
	cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler));

	/*
	 * Work around the hardware limitation. See also above. Trap 100% duty
	 * cycle if the prescaler is 0. Set prescaler to 1 instead. We don't
	 * care about the frequency because its "all-one" in either case.
	 *
	 * We don't need to check the actual prescaler setting, because only
	 * if the prescaler is 0 we can have this particular value.
	 */
	if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) {
		ctrl &= ~SL28CPLD_PWM_CTRL_PRESCALER_MASK;
		ctrl |= FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, 1);
		cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1);
	}

	/*
	 * To avoid glitches when we switch the prescaler, we have to make sure
	 * we have a valid duty cycle for the new mode.
	 *
	 * Take the current prescaler (or the current period length) into
	 * account to decide whether we have to write the duty cycle or the new
	 * prescaler first. If the period length is decreasing we have to
	 * write the duty cycle first.
	 */
	write_duty_cycle_first = pwm->state.period > state->period;

	if (write_duty_cycle_first) {
		ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
		if (ret)
			return ret;
	}

	ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CTRL, ctrl);
	if (ret)
		return ret;

	if (!write_duty_cycle_first) {
		ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
		if (ret)
			return ret;
	}

	return 0;
}

static const struct pwm_ops sl28cpld_pwm_ops = {
	.apply = sl28cpld_pwm_apply,
	.get_state = sl28cpld_pwm_get_state,
	.owner = THIS_MODULE,
};

static int sl28cpld_pwm_probe(struct platform_device *pdev)
{
	struct sl28cpld_pwm *priv;
	struct pwm_chip *chip;
	int ret;

	if (!pdev->dev.parent) {
		dev_err(&pdev->dev, "no parent device\n");
		return -ENODEV;
	}

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
	if (!priv->regmap) {
		dev_err(&pdev->dev, "could not get parent regmap\n");
		return -ENODEV;
	}

	ret = device_property_read_u32(&pdev->dev, "reg", &priv->offset);
	if (ret) {
		dev_err(&pdev->dev, "no 'reg' property found (%pe)\n",
			ERR_PTR(ret));
		return -EINVAL;
	}

	/* Initialize the pwm_chip structure */
	chip = &priv->pwm_chip;
	chip->dev = &pdev->dev;
	chip->ops = &sl28cpld_pwm_ops;
	chip->npwm = 1;

	ret = devm_pwmchip_add(&pdev->dev, &priv->pwm_chip);
	if (ret) {
		dev_err(&pdev->dev, "failed to add PWM chip (%pe)",
			ERR_PTR(ret));
		return ret;
	}

	return 0;
}

static const struct of_device_id sl28cpld_pwm_of_match[] = {
	{ .compatible = "kontron,sl28cpld-pwm" },
	{}
};
MODULE_DEVICE_TABLE(of, sl28cpld_pwm_of_match);

static struct platform_driver sl28cpld_pwm_driver = {
	.probe = sl28cpld_pwm_probe,
	.driver = {
		.name = "sl28cpld-pwm",
		.of_match_table = sl28cpld_pwm_of_match,
	},
};
module_platform_driver(sl28cpld_pwm_driver);

MODULE_DESCRIPTION("sl28cpld PWM Driver");
MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
MODULE_LICENSE("GPL");
Commit	Line	Data
9db33d22 MW	1	// SPDX-License-Identifier: GPL-2.0-only
	2	/*
	3	* sl28cpld PWM driver
	4	*
	5	* Copyright (c) 2020 Michael Walle <michael@walle.cc>
	6	*
	7	* There is no public datasheet available for this PWM core. But it is easy
	8	* enough to be briefly explained. It consists of one 8-bit counter. The PWM
	9	* supports four distinct frequencies by selecting when to reset the counter.
	10	* With the prescaler setting you can select which bit of the counter is used
	11	* to reset it. This implies that the higher the frequency the less remaining
	12	* bits are available for the actual counter.
	13	*
	14	* Let cnt[7:0] be the counter, clocked at 32kHz:
	15	* +-----------+--------+--------------+-----------+---------------+
	16	* \| prescaler \| reset \| counter bits \| frequency \| period length \|
	17	* +-----------+--------+--------------+-----------+---------------+
	18	* \| 0 \| cnt[7] \| cnt[6:0] \| 250 Hz \| 4000000 ns \|
	19	* \| 1 \| cnt[6] \| cnt[5:0] \| 500 Hz \| 2000000 ns \|
	20	* \| 2 \| cnt[5] \| cnt[4:0] \| 1 kHz \| 1000000 ns \|
	21	* \| 3 \| cnt[4] \| cnt[3:0] \| 2 kHz \| 500000 ns \|
	22	* +-----------+--------+--------------+-----------+---------------+
	23	*
	24	* Limitations:
	25	* - The hardware cannot generate a 100% duty cycle if the prescaler is 0.
	26	* - The hardware cannot atomically set the prescaler and the counter value,
	27	* which might lead to glitches and inconsistent states if a write fails.
	28	* - The counter is not reset if you switch the prescaler which leads
	29	* to glitches, too.
	30	* - The duty cycle will switch immediately and not after a complete cycle.
	31	* - Depending on the actual implementation, disabling the PWM might have
	32	* side effects. For example, if the output pin is shared with a GPIO pin
	33	* it will automatically switch back to GPIO mode.
	34	*/
	35
	36	#include <linux/bitfield.h>
	37	#include <linux/kernel.h>
	38	#include <linux/mod_devicetable.h>
	39	#include <linux/module.h>
	40	#include <linux/platform_device.h>
	41	#include <linux/pwm.h>
	42	#include <linux/regmap.h>
	43
	44	/*
	45	* PWM timer block registers.
	46	*/
	47	#define SL28CPLD_PWM_CTRL 0x00
	48	#define SL28CPLD_PWM_CTRL_ENABLE BIT(7)
	49	#define SL28CPLD_PWM_CTRL_PRESCALER_MASK GENMASK(1, 0)
	50	#define SL28CPLD_PWM_CYCLE 0x01
	51	#define SL28CPLD_PWM_CYCLE_MAX GENMASK(6, 0)
	52
	53	#define SL28CPLD_PWM_CLK 32000 /* 32 kHz */
	54	#define SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler) (1 << (7 - (prescaler)))
	55	#define SL28CPLD_PWM_PERIOD(prescaler) \
	56	(NSEC_PER_SEC / SL28CPLD_PWM_CLK * SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler))
	57
	58	/*
	59	* We calculate the duty cycle like this:
	60	* duty_cycle_ns = pwm_cycle_reg * max_period_ns / max_duty_cycle
	61	*
	62	* With
	63	* max_period_ns = 1 << (7 - prescaler) / SL28CPLD_PWM_CLK * NSEC_PER_SEC
	64	* max_duty_cycle = 1 << (7 - prescaler)
65	* this then simplifies to:
66	* duty_cycle_ns = pwm_cycle_reg / SL28CPLD_PWM_CLK * NSEC_PER_SEC
67	* = NSEC_PER_SEC / SL28CPLD_PWM_CLK * pwm_cycle_reg
68	*
69	* NSEC_PER_SEC is a multiple of SL28CPLD_PWM_CLK, therefore we're not losing
70	* precision by doing the divison first.
71	*/
72	#define SL28CPLD_PWM_TO_DUTY_CYCLE(reg) \
73	(NSEC_PER_SEC / SL28CPLD_PWM_CLK * (reg))
74	#define SL28CPLD_PWM_FROM_DUTY_CYCLE(duty_cycle) \
75	(DIV_ROUND_DOWN_ULL((duty_cycle), NSEC_PER_SEC / SL28CPLD_PWM_CLK))
76
77	#define sl28cpld_pwm_read(priv, reg, val) \
78	regmap_read((priv)->regmap, (priv)->offset + (reg), (val))
79	#define sl28cpld_pwm_write(priv, reg, val) \
80	regmap_write((priv)->regmap, (priv)->offset + (reg), (val))
81
82	struct sl28cpld_pwm {
83	struct pwm_chip pwm_chip;
84	struct regmap *regmap;
85	u32 offset;
86	};
062c9cdf UKK	87	#define sl28cpld_pwm_from_chip(_chip) \
062c9cdf UKK	88	container_of(_chip, struct sl28cpld_pwm, pwm_chip)
9db33d22	89
6c452cff UKK	90	static int sl28cpld_pwm_get_state(struct pwm_chip *chip,
	91	struct pwm_device *pwm,
	92	struct pwm_state *state)
9db33d22	93	{
062c9cdf	94	struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
9db33d22 MW	95	unsigned int reg;
	96	int prescaler;
	97
	98	sl28cpld_pwm_read(priv, SL28CPLD_PWM_CTRL, &reg);
	99
	100	state->enabled = reg & SL28CPLD_PWM_CTRL_ENABLE;
	101
	102	prescaler = FIELD_GET(SL28CPLD_PWM_CTRL_PRESCALER_MASK, reg);
	103	state->period = SL28CPLD_PWM_PERIOD(prescaler);
	104
	105	sl28cpld_pwm_read(priv, SL28CPLD_PWM_CYCLE, &reg);
	106	state->duty_cycle = SL28CPLD_PWM_TO_DUTY_CYCLE(reg);
	107	state->polarity = PWM_POLARITY_NORMAL;
	108
	109	/*
	110	* Sanitize values for the PWM core. Depending on the prescaler it
	111	* might happen that we calculate a duty_cycle greater than the actual
	112	* period. This might happen if someone (e.g. the bootloader) sets an
	113	* invalid combination of values. The behavior of the hardware is
	114	* undefined in this case. But we need to report sane values back to
	115	* the PWM core.
	116	*/
	117	state->duty_cycle = min(state->duty_cycle, state->period);
6c452cff UKK	118
6c452cff UKK	119	return 0;
9db33d22 MW	120	}
	121
	122	static int sl28cpld_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	123	const struct pwm_state *state)
	124	{
062c9cdf	125	struct sl28cpld_pwm *priv = sl28cpld_pwm_from_chip(chip);
9db33d22 MW	126	unsigned int cycle, prescaler;
	127	bool write_duty_cycle_first;
	128	int ret;
	129	u8 ctrl;
	130
	131	/* Polarity inversion is not supported */
	132	if (state->polarity != PWM_POLARITY_NORMAL)
	133	return -EINVAL;
	134
	135	/*
	136	* Calculate the prescaler. Pick the biggest period that isn't
	137	* bigger than the requested period.
	138	*/
	139	prescaler = DIV_ROUND_UP_ULL(SL28CPLD_PWM_PERIOD(0), state->period);
	140	prescaler = order_base_2(prescaler);
	141
	142	if (prescaler > field_max(SL28CPLD_PWM_CTRL_PRESCALER_MASK))
	143	return -ERANGE;
	144
	145	ctrl = FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, prescaler);
	146	if (state->enabled)
	147	ctrl \|= SL28CPLD_PWM_CTRL_ENABLE;
	148
	149	cycle = SL28CPLD_PWM_FROM_DUTY_CYCLE(state->duty_cycle);
	150	cycle = min_t(unsigned int, cycle, SL28CPLD_PWM_MAX_DUTY_CYCLE(prescaler));
	151
	152	/*
	153	* Work around the hardware limitation. See also above. Trap 100% duty
	154	* cycle if the prescaler is 0. Set prescaler to 1 instead. We don't
	155	* care about the frequency because its "all-one" in either case.
	156	*
	157	* We don't need to check the actual prescaler setting, because only
	158	* if the prescaler is 0 we can have this particular value.
	159	*/
	160	if (cycle == SL28CPLD_PWM_MAX_DUTY_CYCLE(0)) {
	161	ctrl &= ~SL28CPLD_PWM_CTRL_PRESCALER_MASK;
	162	ctrl \|= FIELD_PREP(SL28CPLD_PWM_CTRL_PRESCALER_MASK, 1);
	163	cycle = SL28CPLD_PWM_MAX_DUTY_CYCLE(1);
	164	}
	165
	166	/*
	167	* To avoid glitches when we switch the prescaler, we have to make sure
	168	* we have a valid duty cycle for the new mode.
	169	*
	170	* Take the current prescaler (or the current period length) into
	171	* account to decide whether we have to write the duty cycle or the new
	172	* prescaler first. If the period length is decreasing we have to
	173	* write the duty cycle first.
	174	*/
	175	write_duty_cycle_first = pwm->state.period > state->period;
	176
	177	if (write_duty_cycle_first) {
	178	ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
	179	if (ret)
	180	return ret;
	181	}
	182
	183	ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CTRL, ctrl);
	184	if (ret)
	185	return ret;
	186
	187	if (!write_duty_cycle_first) {
	188	ret = sl28cpld_pwm_write(priv, SL28CPLD_PWM_CYCLE, cycle);
	189	if (ret)
190	return ret;
191	}
192
193	return 0;
194	}
195
196	static const struct pwm_ops sl28cpld_pwm_ops = {
197	.apply = sl28cpld_pwm_apply,
198	.get_state = sl28cpld_pwm_get_state,
199	.owner = THIS_MODULE,
200	};
201
202	static int sl28cpld_pwm_probe(struct platform_device *pdev)
203	{
204	struct sl28cpld_pwm *priv;
205	struct pwm_chip *chip;
206	int ret;
207
208	if (!pdev->dev.parent) {
209	dev_err(&pdev->dev, "no parent device\n");
210	return -ENODEV;
211	}
212
213	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
214	if (!priv)
215	return -ENOMEM;
216
217	priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
218	if (!priv->regmap) {
219	dev_err(&pdev->dev, "could not get parent regmap\n");
220	return -ENODEV;
221	}
222
223	ret = device_property_read_u32(&pdev->dev, "reg", &priv->offset);
224	if (ret) {
225	dev_err(&pdev->dev, "no 'reg' property found (%pe)\n",
226	ERR_PTR(ret));
227	return -EINVAL;
228	}
229
230	/* Initialize the pwm_chip structure */
231	chip = &priv->pwm_chip;
232	chip->dev = &pdev->dev;
233	chip->ops = &sl28cpld_pwm_ops;
9db33d22 MW	234	chip->npwm = 1;
9db33d22 MW	235
02dd2e41	236	ret = devm_pwmchip_add(&pdev->dev, &priv->pwm_chip);
9db33d22 MW	237	if (ret) {
	238	dev_err(&pdev->dev, "failed to add PWM chip (%pe)",
	239	ERR_PTR(ret));
	240	return ret;
	241	}
	242
9db33d22 MW	243	return 0;
	244	}
	245
9db33d22 MW	246	static const struct of_device_id sl28cpld_pwm_of_match[] = {
	247	{ .compatible = "kontron,sl28cpld-pwm" },
	248	{}
	249	};
	250	MODULE_DEVICE_TABLE(of, sl28cpld_pwm_of_match);
	251
	252	static struct platform_driver sl28cpld_pwm_driver = {
	253	.probe = sl28cpld_pwm_probe,
9db33d22 MW	254	.driver = {
	255	.name = "sl28cpld-pwm",
	256	.of_match_table = sl28cpld_pwm_of_match,
	257	},
	258	};
	259	module_platform_driver(sl28cpld_pwm_driver);
	260
	261	MODULE_DESCRIPTION("sl28cpld PWM Driver");
	262	MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
	263	MODULE_LICENSE("GPL");