Commit | Line | Data |
---|---|---|
11ad39ed TF |
1 | /* |
2 | * Copyright (c) 2007 Ben Dooks | |
3 | * Copyright (c) 2008 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> | |
5 | * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> | |
08a4d8ec | 6 | * Copyright (c) 2017 Samsung Electronics Co., Ltd. |
11ad39ed TF |
7 | * |
8 | * PWM driver for Samsung SoCs | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License. | |
13 | */ | |
14 | ||
15 | #include <linux/bitops.h> | |
16 | #include <linux/clk.h> | |
17 | #include <linux/export.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
c3bdfe1f | 22 | #include <linux/of.h> |
11ad39ed TF |
23 | #include <linux/platform_device.h> |
24 | #include <linux/pwm.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/time.h> | |
28 | ||
29 | /* For struct samsung_timer_variant and samsung_pwm_lock. */ | |
30 | #include <clocksource/samsung_pwm.h> | |
31 | ||
32 | #define REG_TCFG0 0x00 | |
33 | #define REG_TCFG1 0x04 | |
34 | #define REG_TCON 0x08 | |
35 | ||
36 | #define REG_TCNTB(chan) (0x0c + ((chan) * 0xc)) | |
37 | #define REG_TCMPB(chan) (0x10 + ((chan) * 0xc)) | |
38 | ||
39 | #define TCFG0_PRESCALER_MASK 0xff | |
40 | #define TCFG0_PRESCALER1_SHIFT 8 | |
41 | ||
42 | #define TCFG1_MUX_MASK 0xf | |
43 | #define TCFG1_SHIFT(chan) (4 * (chan)) | |
44 | ||
45 | /* | |
46 | * Each channel occupies 4 bits in TCON register, but there is a gap of 4 | |
47 | * bits (one channel) after channel 0, so channels have different numbering | |
48 | * when accessing TCON register. See to_tcon_channel() function. | |
49 | * | |
50 | * In addition, the location of autoreload bit for channel 4 (TCON channel 5) | |
51 | * in its set of bits is 2 as opposed to 3 for other channels. | |
52 | */ | |
53 | #define TCON_START(chan) BIT(4 * (chan) + 0) | |
54 | #define TCON_MANUALUPDATE(chan) BIT(4 * (chan) + 1) | |
55 | #define TCON_INVERT(chan) BIT(4 * (chan) + 2) | |
56 | #define _TCON_AUTORELOAD(chan) BIT(4 * (chan) + 3) | |
57 | #define _TCON_AUTORELOAD4(chan) BIT(4 * (chan) + 2) | |
58 | #define TCON_AUTORELOAD(chan) \ | |
59 | ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan)) | |
60 | ||
61 | /** | |
62 | * struct samsung_pwm_channel - private data of PWM channel | |
63 | * @period_ns: current period in nanoseconds programmed to the hardware | |
64 | * @duty_ns: current duty time in nanoseconds programmed to the hardware | |
65 | * @tin_ns: time of one timer tick in nanoseconds with current timer rate | |
66 | */ | |
67 | struct samsung_pwm_channel { | |
68 | u32 period_ns; | |
69 | u32 duty_ns; | |
70 | u32 tin_ns; | |
71 | }; | |
72 | ||
73 | /** | |
74 | * struct samsung_pwm_chip - private data of PWM chip | |
75 | * @chip: generic PWM chip | |
76 | * @variant: local copy of hardware variant data | |
77 | * @inverter_mask: inverter status for all channels - one bit per channel | |
08a4d8ec | 78 | * @disabled_mask: disabled status for all channels - one bit per channel |
11ad39ed TF |
79 | * @base: base address of mapped PWM registers |
80 | * @base_clk: base clock used to drive the timers | |
81 | * @tclk0: external clock 0 (can be ERR_PTR if not present) | |
82 | * @tclk1: external clock 1 (can be ERR_PTR if not present) | |
83 | */ | |
84 | struct samsung_pwm_chip { | |
85 | struct pwm_chip chip; | |
86 | struct samsung_pwm_variant variant; | |
87 | u8 inverter_mask; | |
08a4d8ec | 88 | u8 disabled_mask; |
11ad39ed TF |
89 | |
90 | void __iomem *base; | |
91 | struct clk *base_clk; | |
92 | struct clk *tclk0; | |
93 | struct clk *tclk1; | |
94 | }; | |
95 | ||
96 | #ifndef CONFIG_CLKSRC_SAMSUNG_PWM | |
97 | /* | |
98 | * PWM block is shared between pwm-samsung and samsung_pwm_timer drivers | |
99 | * and some registers need access synchronization. If both drivers are | |
100 | * compiled in, the spinlock is defined in the clocksource driver, | |
101 | * otherwise following definition is used. | |
102 | * | |
103 | * Currently we do not need any more complex synchronization method | |
104 | * because all the supported SoCs contain only one instance of the PWM | |
105 | * IP. Should this change, both drivers will need to be modified to | |
106 | * properly synchronize accesses to particular instances. | |
107 | */ | |
108 | static DEFINE_SPINLOCK(samsung_pwm_lock); | |
109 | #endif | |
110 | ||
111 | static inline | |
112 | struct samsung_pwm_chip *to_samsung_pwm_chip(struct pwm_chip *chip) | |
113 | { | |
114 | return container_of(chip, struct samsung_pwm_chip, chip); | |
115 | } | |
116 | ||
117 | static inline unsigned int to_tcon_channel(unsigned int channel) | |
118 | { | |
119 | /* TCON register has a gap of 4 bits (1 channel) after channel 0 */ | |
120 | return (channel == 0) ? 0 : (channel + 1); | |
121 | } | |
122 | ||
123 | static void pwm_samsung_set_divisor(struct samsung_pwm_chip *pwm, | |
124 | unsigned int channel, u8 divisor) | |
125 | { | |
126 | u8 shift = TCFG1_SHIFT(channel); | |
127 | unsigned long flags; | |
128 | u32 reg; | |
129 | u8 bits; | |
130 | ||
131 | bits = (fls(divisor) - 1) - pwm->variant.div_base; | |
132 | ||
133 | spin_lock_irqsave(&samsung_pwm_lock, flags); | |
134 | ||
135 | reg = readl(pwm->base + REG_TCFG1); | |
136 | reg &= ~(TCFG1_MUX_MASK << shift); | |
137 | reg |= bits << shift; | |
138 | writel(reg, pwm->base + REG_TCFG1); | |
139 | ||
140 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); | |
141 | } | |
142 | ||
143 | static int pwm_samsung_is_tdiv(struct samsung_pwm_chip *chip, unsigned int chan) | |
144 | { | |
145 | struct samsung_pwm_variant *variant = &chip->variant; | |
146 | u32 reg; | |
147 | ||
148 | reg = readl(chip->base + REG_TCFG1); | |
149 | reg >>= TCFG1_SHIFT(chan); | |
150 | reg &= TCFG1_MUX_MASK; | |
151 | ||
152 | return (BIT(reg) & variant->tclk_mask) == 0; | |
153 | } | |
154 | ||
155 | static unsigned long pwm_samsung_get_tin_rate(struct samsung_pwm_chip *chip, | |
156 | unsigned int chan) | |
157 | { | |
158 | unsigned long rate; | |
159 | u32 reg; | |
160 | ||
161 | rate = clk_get_rate(chip->base_clk); | |
162 | ||
163 | reg = readl(chip->base + REG_TCFG0); | |
164 | if (chan >= 2) | |
165 | reg >>= TCFG0_PRESCALER1_SHIFT; | |
166 | reg &= TCFG0_PRESCALER_MASK; | |
167 | ||
168 | return rate / (reg + 1); | |
169 | } | |
170 | ||
171 | static unsigned long pwm_samsung_calc_tin(struct samsung_pwm_chip *chip, | |
172 | unsigned int chan, unsigned long freq) | |
173 | { | |
174 | struct samsung_pwm_variant *variant = &chip->variant; | |
175 | unsigned long rate; | |
176 | struct clk *clk; | |
177 | u8 div; | |
178 | ||
179 | if (!pwm_samsung_is_tdiv(chip, chan)) { | |
180 | clk = (chan < 2) ? chip->tclk0 : chip->tclk1; | |
181 | if (!IS_ERR(clk)) { | |
182 | rate = clk_get_rate(clk); | |
183 | if (rate) | |
184 | return rate; | |
185 | } | |
186 | ||
187 | dev_warn(chip->chip.dev, | |
188 | "tclk of PWM %d is inoperational, using tdiv\n", chan); | |
189 | } | |
190 | ||
191 | rate = pwm_samsung_get_tin_rate(chip, chan); | |
192 | dev_dbg(chip->chip.dev, "tin parent at %lu\n", rate); | |
193 | ||
194 | /* | |
195 | * Compare minimum PWM frequency that can be achieved with possible | |
196 | * divider settings and choose the lowest divisor that can generate | |
197 | * frequencies lower than requested. | |
198 | */ | |
04d68dea SWK |
199 | if (variant->bits < 32) { |
200 | /* Only for s3c24xx */ | |
201 | for (div = variant->div_base; div < 4; ++div) | |
202 | if ((rate >> (variant->bits + div)) < freq) | |
203 | break; | |
204 | } else { | |
205 | /* | |
206 | * Other variants have enough counter bits to generate any | |
207 | * requested rate, so no need to check higher divisors. | |
208 | */ | |
209 | div = variant->div_base; | |
210 | } | |
11ad39ed TF |
211 | |
212 | pwm_samsung_set_divisor(chip, chan, BIT(div)); | |
213 | ||
214 | return rate >> div; | |
215 | } | |
216 | ||
217 | static int pwm_samsung_request(struct pwm_chip *chip, struct pwm_device *pwm) | |
218 | { | |
219 | struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); | |
220 | struct samsung_pwm_channel *our_chan; | |
221 | ||
222 | if (!(our_chip->variant.output_mask & BIT(pwm->hwpwm))) { | |
223 | dev_warn(chip->dev, | |
224 | "tried to request PWM channel %d without output\n", | |
225 | pwm->hwpwm); | |
226 | return -EINVAL; | |
227 | } | |
228 | ||
229 | our_chan = devm_kzalloc(chip->dev, sizeof(*our_chan), GFP_KERNEL); | |
230 | if (!our_chan) | |
231 | return -ENOMEM; | |
232 | ||
233 | pwm_set_chip_data(pwm, our_chan); | |
234 | ||
235 | return 0; | |
236 | } | |
237 | ||
238 | static void pwm_samsung_free(struct pwm_chip *chip, struct pwm_device *pwm) | |
239 | { | |
11ad39ed | 240 | devm_kfree(chip->dev, pwm_get_chip_data(pwm)); |
b577cdcf | 241 | pwm_set_chip_data(pwm, NULL); |
11ad39ed TF |
242 | } |
243 | ||
244 | static int pwm_samsung_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
245 | { | |
246 | struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); | |
247 | unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); | |
248 | unsigned long flags; | |
249 | u32 tcon; | |
250 | ||
251 | spin_lock_irqsave(&samsung_pwm_lock, flags); | |
252 | ||
253 | tcon = readl(our_chip->base + REG_TCON); | |
254 | ||
255 | tcon &= ~TCON_START(tcon_chan); | |
256 | tcon |= TCON_MANUALUPDATE(tcon_chan); | |
257 | writel(tcon, our_chip->base + REG_TCON); | |
258 | ||
259 | tcon &= ~TCON_MANUALUPDATE(tcon_chan); | |
260 | tcon |= TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan); | |
261 | writel(tcon, our_chip->base + REG_TCON); | |
262 | ||
08a4d8ec BZ |
263 | our_chip->disabled_mask &= ~BIT(pwm->hwpwm); |
264 | ||
11ad39ed TF |
265 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
266 | ||
267 | return 0; | |
268 | } | |
269 | ||
270 | static void pwm_samsung_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
271 | { | |
272 | struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); | |
273 | unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); | |
274 | unsigned long flags; | |
275 | u32 tcon; | |
276 | ||
277 | spin_lock_irqsave(&samsung_pwm_lock, flags); | |
278 | ||
279 | tcon = readl(our_chip->base + REG_TCON); | |
280 | tcon &= ~TCON_AUTORELOAD(tcon_chan); | |
281 | writel(tcon, our_chip->base + REG_TCON); | |
282 | ||
08a4d8ec BZ |
283 | our_chip->disabled_mask |= BIT(pwm->hwpwm); |
284 | ||
11ad39ed TF |
285 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); |
286 | } | |
287 | ||
4a1c683c SS |
288 | static void pwm_samsung_manual_update(struct samsung_pwm_chip *chip, |
289 | struct pwm_device *pwm) | |
290 | { | |
291 | unsigned int tcon_chan = to_tcon_channel(pwm->hwpwm); | |
292 | u32 tcon; | |
293 | unsigned long flags; | |
294 | ||
295 | spin_lock_irqsave(&samsung_pwm_lock, flags); | |
296 | ||
297 | tcon = readl(chip->base + REG_TCON); | |
298 | tcon |= TCON_MANUALUPDATE(tcon_chan); | |
299 | writel(tcon, chip->base + REG_TCON); | |
300 | ||
301 | tcon &= ~TCON_MANUALUPDATE(tcon_chan); | |
302 | writel(tcon, chip->base + REG_TCON); | |
303 | ||
304 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); | |
305 | } | |
306 | ||
08a4d8ec BZ |
307 | static int __pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, |
308 | int duty_ns, int period_ns, bool force_period) | |
11ad39ed TF |
309 | { |
310 | struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); | |
311 | struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm); | |
4a1c683c | 312 | u32 tin_ns = chan->tin_ns, tcnt, tcmp, oldtcmp; |
11ad39ed TF |
313 | |
314 | /* | |
315 | * We currently avoid using 64bit arithmetic by using the | |
316 | * fact that anything faster than 1Hz is easily representable | |
317 | * by 32bits. | |
318 | */ | |
319 | if (period_ns > NSEC_PER_SEC) | |
320 | return -ERANGE; | |
321 | ||
11ad39ed | 322 | tcnt = readl(our_chip->base + REG_TCNTB(pwm->hwpwm)); |
4a1c683c | 323 | oldtcmp = readl(our_chip->base + REG_TCMPB(pwm->hwpwm)); |
11ad39ed TF |
324 | |
325 | /* We need tick count for calculation, not last tick. */ | |
326 | ++tcnt; | |
327 | ||
328 | /* Check to see if we are changing the clock rate of the PWM. */ | |
08a4d8ec | 329 | if (chan->period_ns != period_ns || force_period) { |
11ad39ed TF |
330 | unsigned long tin_rate; |
331 | u32 period; | |
332 | ||
333 | period = NSEC_PER_SEC / period_ns; | |
334 | ||
335 | dev_dbg(our_chip->chip.dev, "duty_ns=%d, period_ns=%d (%u)\n", | |
336 | duty_ns, period_ns, period); | |
337 | ||
338 | tin_rate = pwm_samsung_calc_tin(our_chip, pwm->hwpwm, period); | |
339 | ||
340 | dev_dbg(our_chip->chip.dev, "tin_rate=%lu\n", tin_rate); | |
341 | ||
342 | tin_ns = NSEC_PER_SEC / tin_rate; | |
343 | tcnt = period_ns / tin_ns; | |
344 | } | |
345 | ||
346 | /* Period is too short. */ | |
347 | if (tcnt <= 1) | |
348 | return -ERANGE; | |
349 | ||
350 | /* Note that counters count down. */ | |
351 | tcmp = duty_ns / tin_ns; | |
352 | ||
353 | /* 0% duty is not available */ | |
354 | if (!tcmp) | |
355 | ++tcmp; | |
356 | ||
357 | tcmp = tcnt - tcmp; | |
358 | ||
359 | /* Decrement to get tick numbers, instead of tick counts. */ | |
360 | --tcnt; | |
361 | /* -1UL will give 100% duty. */ | |
362 | --tcmp; | |
363 | ||
364 | dev_dbg(our_chip->chip.dev, | |
365 | "tin_ns=%u, tcmp=%u/%u\n", tin_ns, tcmp, tcnt); | |
366 | ||
367 | /* Update PWM registers. */ | |
368 | writel(tcnt, our_chip->base + REG_TCNTB(pwm->hwpwm)); | |
369 | writel(tcmp, our_chip->base + REG_TCMPB(pwm->hwpwm)); | |
370 | ||
4a1c683c SS |
371 | /* |
372 | * In case the PWM is currently at 100% duty cycle, force a manual | |
373 | * update to prevent the signal staying high if the PWM is disabled | |
374 | * shortly afer this update (before it autoreloaded the new values). | |
375 | */ | |
376 | if (oldtcmp == (u32) -1) { | |
377 | dev_dbg(our_chip->chip.dev, "Forcing manual update"); | |
378 | pwm_samsung_manual_update(our_chip, pwm); | |
379 | } | |
380 | ||
11ad39ed TF |
381 | chan->period_ns = period_ns; |
382 | chan->tin_ns = tin_ns; | |
383 | chan->duty_ns = duty_ns; | |
384 | ||
385 | return 0; | |
386 | } | |
387 | ||
08a4d8ec BZ |
388 | static int pwm_samsung_config(struct pwm_chip *chip, struct pwm_device *pwm, |
389 | int duty_ns, int period_ns) | |
390 | { | |
391 | return __pwm_samsung_config(chip, pwm, duty_ns, period_ns, false); | |
392 | } | |
393 | ||
11ad39ed TF |
394 | static void pwm_samsung_set_invert(struct samsung_pwm_chip *chip, |
395 | unsigned int channel, bool invert) | |
396 | { | |
397 | unsigned int tcon_chan = to_tcon_channel(channel); | |
398 | unsigned long flags; | |
399 | u32 tcon; | |
400 | ||
401 | spin_lock_irqsave(&samsung_pwm_lock, flags); | |
402 | ||
403 | tcon = readl(chip->base + REG_TCON); | |
404 | ||
405 | if (invert) { | |
406 | chip->inverter_mask |= BIT(channel); | |
407 | tcon |= TCON_INVERT(tcon_chan); | |
408 | } else { | |
409 | chip->inverter_mask &= ~BIT(channel); | |
410 | tcon &= ~TCON_INVERT(tcon_chan); | |
411 | } | |
412 | ||
413 | writel(tcon, chip->base + REG_TCON); | |
414 | ||
415 | spin_unlock_irqrestore(&samsung_pwm_lock, flags); | |
416 | } | |
417 | ||
418 | static int pwm_samsung_set_polarity(struct pwm_chip *chip, | |
419 | struct pwm_device *pwm, | |
420 | enum pwm_polarity polarity) | |
421 | { | |
422 | struct samsung_pwm_chip *our_chip = to_samsung_pwm_chip(chip); | |
423 | bool invert = (polarity == PWM_POLARITY_NORMAL); | |
424 | ||
425 | /* Inverted means normal in the hardware. */ | |
426 | pwm_samsung_set_invert(our_chip, pwm->hwpwm, invert); | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
431 | static const struct pwm_ops pwm_samsung_ops = { | |
432 | .request = pwm_samsung_request, | |
433 | .free = pwm_samsung_free, | |
434 | .enable = pwm_samsung_enable, | |
435 | .disable = pwm_samsung_disable, | |
436 | .config = pwm_samsung_config, | |
437 | .set_polarity = pwm_samsung_set_polarity, | |
438 | .owner = THIS_MODULE, | |
439 | }; | |
440 | ||
441 | #ifdef CONFIG_OF | |
442 | static const struct samsung_pwm_variant s3c24xx_variant = { | |
443 | .bits = 16, | |
444 | .div_base = 1, | |
445 | .has_tint_cstat = false, | |
446 | .tclk_mask = BIT(4), | |
447 | }; | |
448 | ||
449 | static const struct samsung_pwm_variant s3c64xx_variant = { | |
450 | .bits = 32, | |
451 | .div_base = 0, | |
452 | .has_tint_cstat = true, | |
453 | .tclk_mask = BIT(7) | BIT(6) | BIT(5), | |
454 | }; | |
455 | ||
456 | static const struct samsung_pwm_variant s5p64x0_variant = { | |
457 | .bits = 32, | |
458 | .div_base = 0, | |
459 | .has_tint_cstat = true, | |
460 | .tclk_mask = 0, | |
461 | }; | |
462 | ||
463 | static const struct samsung_pwm_variant s5pc100_variant = { | |
464 | .bits = 32, | |
465 | .div_base = 0, | |
466 | .has_tint_cstat = true, | |
467 | .tclk_mask = BIT(5), | |
468 | }; | |
469 | ||
470 | static const struct of_device_id samsung_pwm_matches[] = { | |
471 | { .compatible = "samsung,s3c2410-pwm", .data = &s3c24xx_variant }, | |
472 | { .compatible = "samsung,s3c6400-pwm", .data = &s3c64xx_variant }, | |
473 | { .compatible = "samsung,s5p6440-pwm", .data = &s5p64x0_variant }, | |
474 | { .compatible = "samsung,s5pc100-pwm", .data = &s5pc100_variant }, | |
475 | { .compatible = "samsung,exynos4210-pwm", .data = &s5p64x0_variant }, | |
476 | {}, | |
477 | }; | |
cccb9454 | 478 | MODULE_DEVICE_TABLE(of, samsung_pwm_matches); |
11ad39ed TF |
479 | |
480 | static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip) | |
481 | { | |
482 | struct device_node *np = chip->chip.dev->of_node; | |
483 | const struct of_device_id *match; | |
484 | struct property *prop; | |
485 | const __be32 *cur; | |
486 | u32 val; | |
487 | ||
488 | match = of_match_node(samsung_pwm_matches, np); | |
489 | if (!match) | |
490 | return -ENODEV; | |
491 | ||
492 | memcpy(&chip->variant, match->data, sizeof(chip->variant)); | |
493 | ||
494 | of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) { | |
495 | if (val >= SAMSUNG_PWM_NUM) { | |
496 | dev_err(chip->chip.dev, | |
497 | "%s: invalid channel index in samsung,pwm-outputs property\n", | |
498 | __func__); | |
499 | continue; | |
500 | } | |
501 | chip->variant.output_mask |= BIT(val); | |
502 | } | |
503 | ||
504 | return 0; | |
505 | } | |
506 | #else | |
507 | static int pwm_samsung_parse_dt(struct samsung_pwm_chip *chip) | |
508 | { | |
509 | return -ENODEV; | |
510 | } | |
511 | #endif | |
512 | ||
513 | static int pwm_samsung_probe(struct platform_device *pdev) | |
514 | { | |
515 | struct device *dev = &pdev->dev; | |
516 | struct samsung_pwm_chip *chip; | |
517 | struct resource *res; | |
518 | unsigned int chan; | |
519 | int ret; | |
520 | ||
521 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); | |
522 | if (chip == NULL) | |
523 | return -ENOMEM; | |
524 | ||
525 | chip->chip.dev = &pdev->dev; | |
526 | chip->chip.ops = &pwm_samsung_ops; | |
527 | chip->chip.base = -1; | |
528 | chip->chip.npwm = SAMSUNG_PWM_NUM; | |
529 | chip->inverter_mask = BIT(SAMSUNG_PWM_NUM) - 1; | |
530 | ||
531 | if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { | |
532 | ret = pwm_samsung_parse_dt(chip); | |
533 | if (ret) | |
534 | return ret; | |
535 | ||
536 | chip->chip.of_xlate = of_pwm_xlate_with_flags; | |
537 | chip->chip.of_pwm_n_cells = 3; | |
538 | } else { | |
539 | if (!pdev->dev.platform_data) { | |
540 | dev_err(&pdev->dev, "no platform data specified\n"); | |
541 | return -EINVAL; | |
542 | } | |
543 | ||
544 | memcpy(&chip->variant, pdev->dev.platform_data, | |
545 | sizeof(chip->variant)); | |
546 | } | |
547 | ||
548 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
549 | chip->base = devm_ioremap_resource(&pdev->dev, res); | |
550 | if (IS_ERR(chip->base)) | |
551 | return PTR_ERR(chip->base); | |
552 | ||
553 | chip->base_clk = devm_clk_get(&pdev->dev, "timers"); | |
554 | if (IS_ERR(chip->base_clk)) { | |
555 | dev_err(dev, "failed to get timer base clk\n"); | |
556 | return PTR_ERR(chip->base_clk); | |
557 | } | |
558 | ||
559 | ret = clk_prepare_enable(chip->base_clk); | |
560 | if (ret < 0) { | |
561 | dev_err(dev, "failed to enable base clock\n"); | |
562 | return ret; | |
563 | } | |
564 | ||
565 | for (chan = 0; chan < SAMSUNG_PWM_NUM; ++chan) | |
566 | if (chip->variant.output_mask & BIT(chan)) | |
567 | pwm_samsung_set_invert(chip, chan, true); | |
568 | ||
569 | /* Following clocks are optional. */ | |
570 | chip->tclk0 = devm_clk_get(&pdev->dev, "pwm-tclk0"); | |
571 | chip->tclk1 = devm_clk_get(&pdev->dev, "pwm-tclk1"); | |
572 | ||
573 | platform_set_drvdata(pdev, chip); | |
574 | ||
575 | ret = pwmchip_add(&chip->chip); | |
576 | if (ret < 0) { | |
577 | dev_err(dev, "failed to register PWM chip\n"); | |
578 | clk_disable_unprepare(chip->base_clk); | |
579 | return ret; | |
580 | } | |
581 | ||
582 | dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n", | |
583 | clk_get_rate(chip->base_clk), | |
584 | !IS_ERR(chip->tclk0) ? clk_get_rate(chip->tclk0) : 0, | |
585 | !IS_ERR(chip->tclk1) ? clk_get_rate(chip->tclk1) : 0); | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static int pwm_samsung_remove(struct platform_device *pdev) | |
591 | { | |
592 | struct samsung_pwm_chip *chip = platform_get_drvdata(pdev); | |
593 | int ret; | |
594 | ||
595 | ret = pwmchip_remove(&chip->chip); | |
596 | if (ret < 0) | |
597 | return ret; | |
598 | ||
599 | clk_disable_unprepare(chip->base_clk); | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | #ifdef CONFIG_PM_SLEEP | |
08a4d8ec | 605 | static int pwm_samsung_resume(struct device *dev) |
11ad39ed | 606 | { |
08a4d8ec BZ |
607 | struct samsung_pwm_chip *our_chip = dev_get_drvdata(dev); |
608 | struct pwm_chip *chip = &our_chip->chip; | |
11ad39ed TF |
609 | unsigned int i; |
610 | ||
08a4d8ec BZ |
611 | for (i = 0; i < SAMSUNG_PWM_NUM; i++) { |
612 | struct pwm_device *pwm = &chip->pwms[i]; | |
11ad39ed TF |
613 | struct samsung_pwm_channel *chan = pwm_get_chip_data(pwm); |
614 | ||
615 | if (!chan) | |
616 | continue; | |
617 | ||
08a4d8ec BZ |
618 | if (our_chip->variant.output_mask & BIT(i)) |
619 | pwm_samsung_set_invert(our_chip, i, | |
620 | our_chip->inverter_mask & BIT(i)); | |
11ad39ed | 621 | |
08a4d8ec BZ |
622 | if (chan->period_ns) { |
623 | __pwm_samsung_config(chip, pwm, chan->duty_ns, | |
624 | chan->period_ns, true); | |
625 | /* needed to make PWM disable work on Odroid-XU3 */ | |
626 | pwm_samsung_manual_update(our_chip, pwm); | |
627 | } | |
11ad39ed | 628 | |
08a4d8ec BZ |
629 | if (our_chip->disabled_mask & BIT(i)) |
630 | pwm_samsung_disable(chip, pwm); | |
631 | else | |
632 | pwm_samsung_enable(chip, pwm); | |
11ad39ed TF |
633 | } |
634 | ||
635 | return 0; | |
636 | } | |
637 | #endif | |
638 | ||
08a4d8ec | 639 | static SIMPLE_DEV_PM_OPS(pwm_samsung_pm_ops, NULL, pwm_samsung_resume); |
11ad39ed TF |
640 | |
641 | static struct platform_driver pwm_samsung_driver = { | |
642 | .driver = { | |
643 | .name = "samsung-pwm", | |
11ad39ed TF |
644 | .pm = &pwm_samsung_pm_ops, |
645 | .of_match_table = of_match_ptr(samsung_pwm_matches), | |
646 | }, | |
647 | .probe = pwm_samsung_probe, | |
648 | .remove = pwm_samsung_remove, | |
649 | }; | |
650 | module_platform_driver(pwm_samsung_driver); | |
651 | ||
652 | MODULE_LICENSE("GPL"); | |
653 | MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>"); | |
654 | MODULE_ALIAS("platform:samsung-pwm"); |