[linux-2.6-block.git] / drivers / pwm / pwm-rockchip.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * PWM driver for Rockchip SoCs
 *
 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
 * Copyright (C) 2014 ROCKCHIP, Inc.
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/time.h>

#define PWM_CTRL_TIMER_EN	(1 << 0)
#define PWM_CTRL_OUTPUT_EN	(1 << 3)

#define PWM_ENABLE		(1 << 0)
#define PWM_CONTINUOUS		(1 << 1)
#define PWM_DUTY_POSITIVE	(1 << 3)
#define PWM_DUTY_NEGATIVE	(0 << 3)
#define PWM_INACTIVE_NEGATIVE	(0 << 4)
#define PWM_INACTIVE_POSITIVE	(1 << 4)
#define PWM_POLARITY_MASK	(PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
#define PWM_OUTPUT_LEFT		(0 << 5)
#define PWM_LOCK_EN		(1 << 6)
#define PWM_LP_DISABLE		(0 << 8)

struct rockchip_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	struct clk *pclk;
	const struct rockchip_pwm_data *data;
	void __iomem *base;
};

struct rockchip_pwm_regs {
	unsigned long duty;
	unsigned long period;
	unsigned long cntr;
	unsigned long ctrl;
};

struct rockchip_pwm_data {
	struct rockchip_pwm_regs regs;
	unsigned int prescaler;
	bool supports_polarity;
	bool supports_lock;
	u32 enable_conf;
};

static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
{
	return container_of(c, struct rockchip_pwm_chip, chip);
}

static void rockchip_pwm_get_state(struct pwm_chip *chip,
				   struct pwm_device *pwm,
				   struct pwm_state *state)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	u32 enable_conf = pc->data->enable_conf;
	unsigned long clk_rate;
	u64 tmp;
	u32 val;
	int ret;

	ret = clk_enable(pc->pclk);
	if (ret)
		return;

	clk_rate = clk_get_rate(pc->clk);

	tmp = readl_relaxed(pc->base + pc->data->regs.period);
	tmp *= pc->data->prescaler * NSEC_PER_SEC;
	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);

	tmp = readl_relaxed(pc->base + pc->data->regs.duty);
	tmp *= pc->data->prescaler * NSEC_PER_SEC;
	state->duty_cycle =  DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);

	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
	state->enabled = (val & enable_conf) == enable_conf;

	if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
		state->polarity = PWM_POLARITY_INVERSED;
	else
		state->polarity = PWM_POLARITY_NORMAL;

	clk_disable(pc->pclk);
}

static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			       const struct pwm_state *state)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	unsigned long period, duty;
	u64 clk_rate, div;
	u32 ctrl;

	clk_rate = clk_get_rate(pc->clk);

	/*
	 * Since period and duty cycle registers have a width of 32
	 * bits, every possible input period can be obtained using the
	 * default prescaler value for all practical clock rate values.
	 */
	div = clk_rate * state->period;
	period = DIV_ROUND_CLOSEST_ULL(div,
				       pc->data->prescaler * NSEC_PER_SEC);

	div = clk_rate * state->duty_cycle;
	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);

	/*
	 * Lock the period and duty of previous configuration, then
	 * change the duty and period, that would not be effective.
	 */
	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
	if (pc->data->supports_lock) {
		ctrl |= PWM_LOCK_EN;
		writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
	}

	writel(period, pc->base + pc->data->regs.period);
	writel(duty, pc->base + pc->data->regs.duty);

	if (pc->data->supports_polarity) {
		ctrl &= ~PWM_POLARITY_MASK;
		if (state->polarity == PWM_POLARITY_INVERSED)
			ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
		else
			ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
	}

	/*
	 * Unlock and set polarity at the same time,
	 * the configuration of duty, period and polarity
	 * would be effective together at next period.
	 */
	if (pc->data->supports_lock)
		ctrl &= ~PWM_LOCK_EN;

	writel(ctrl, pc->base + pc->data->regs.ctrl);
}

static int rockchip_pwm_enable(struct pwm_chip *chip,
			       struct pwm_device *pwm,
			       bool enable)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	u32 enable_conf = pc->data->enable_conf;
	int ret;
	u32 val;

	if (enable) {
		ret = clk_enable(pc->clk);
		if (ret)
			return ret;
	}

	val = readl_relaxed(pc->base + pc->data->regs.ctrl);

	if (enable)
		val |= enable_conf;
	else
		val &= ~enable_conf;

	writel_relaxed(val, pc->base + pc->data->regs.ctrl);

	if (!enable)
		clk_disable(pc->clk);

	return 0;
}

static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			      const struct pwm_state *state)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	struct pwm_state curstate;
	bool enabled;
	int ret = 0;

	ret = clk_enable(pc->pclk);
	if (ret)
		return ret;

	pwm_get_state(pwm, &curstate);
	enabled = curstate.enabled;

	if (state->polarity != curstate.polarity && enabled &&
	    !pc->data->supports_lock) {
		ret = rockchip_pwm_enable(chip, pwm, false);
		if (ret)
			goto out;
		enabled = false;
	}

	rockchip_pwm_config(chip, pwm, state);
	if (state->enabled != enabled) {
		ret = rockchip_pwm_enable(chip, pwm, state->enabled);
		if (ret)
			goto out;
	}

out:
	clk_disable(pc->pclk);

	return ret;
}

static const struct pwm_ops rockchip_pwm_ops = {
	.get_state = rockchip_pwm_get_state,
	.apply = rockchip_pwm_apply,
	.owner = THIS_MODULE,
};

static const struct rockchip_pwm_data pwm_data_v1 = {
	.regs = {
		.duty = 0x04,
		.period = 0x08,
		.cntr = 0x00,
		.ctrl = 0x0c,
	},
	.prescaler = 2,
	.supports_polarity = false,
	.supports_lock = false,
	.enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
};

static const struct rockchip_pwm_data pwm_data_v2 = {
	.regs = {
		.duty = 0x08,
		.period = 0x04,
		.cntr = 0x00,
		.ctrl = 0x0c,
	},
	.prescaler = 1,
	.supports_polarity = true,
	.supports_lock = false,
	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
		       PWM_CONTINUOUS,
};

static const struct rockchip_pwm_data pwm_data_vop = {
	.regs = {
		.duty = 0x08,
		.period = 0x04,
		.cntr = 0x0c,
		.ctrl = 0x00,
	},
	.prescaler = 1,
	.supports_polarity = true,
	.supports_lock = false,
	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
		       PWM_CONTINUOUS,
};

static const struct rockchip_pwm_data pwm_data_v3 = {
	.regs = {
		.duty = 0x08,
		.period = 0x04,
		.cntr = 0x00,
		.ctrl = 0x0c,
	},
	.prescaler = 1,
	.supports_polarity = true,
	.supports_lock = true,
	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
		       PWM_CONTINUOUS,
};

static const struct of_device_id rockchip_pwm_dt_ids[] = {
	{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
	{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
	{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
	{ .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);

static int rockchip_pwm_probe(struct platform_device *pdev)
{
	const struct of_device_id *id;
	struct rockchip_pwm_chip *pc;
	u32 enable_conf, ctrl;
	int ret, count;

	id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
	if (!id)
		return -EINVAL;

	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	pc->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pc->base))
		return PTR_ERR(pc->base);

	pc->clk = devm_clk_get(&pdev->dev, "pwm");
	if (IS_ERR(pc->clk)) {
		pc->clk = devm_clk_get(&pdev->dev, NULL);
		if (IS_ERR(pc->clk))
			return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
					     "Can't get bus clk\n");
	}

	count = of_count_phandle_with_args(pdev->dev.of_node,
					   "clocks", "#clock-cells");
	if (count == 2)
		pc->pclk = devm_clk_get(&pdev->dev, "pclk");
	else
		pc->pclk = pc->clk;

	if (IS_ERR(pc->pclk)) {
		ret = PTR_ERR(pc->pclk);
		if (ret != -EPROBE_DEFER)
			dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
		return ret;
	}

	ret = clk_prepare_enable(pc->clk);
	if (ret) {
		dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
		return ret;
	}

	ret = clk_prepare_enable(pc->pclk);
	if (ret) {
		dev_err(&pdev->dev, "Can't prepare enable APB clk: %d\n", ret);
		goto err_clk;
	}

	platform_set_drvdata(pdev, pc);

	pc->data = id->data;
	pc->chip.dev = &pdev->dev;
	pc->chip.ops = &rockchip_pwm_ops;
	pc->chip.base = -1;
	pc->chip.npwm = 1;

	if (pc->data->supports_polarity) {
		pc->chip.of_xlate = of_pwm_xlate_with_flags;
		pc->chip.of_pwm_n_cells = 3;
	}

	ret = pwmchip_add(&pc->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		goto err_pclk;
	}

	/* Keep the PWM clk enabled if the PWM appears to be up and running. */
	enable_conf = pc->data->enable_conf;
	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
	if ((ctrl & enable_conf) != enable_conf)
		clk_disable(pc->clk);

	clk_disable(pc->pclk);

	return 0;

err_pclk:
	clk_disable_unprepare(pc->pclk);
err_clk:
	clk_disable_unprepare(pc->clk);

	return ret;
}

static int rockchip_pwm_remove(struct platform_device *pdev)
{
	struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);

	/*
	 * Disable the PWM clk before unpreparing it if the PWM device is still
	 * running. This should only happen when the last PWM user left it
	 * enabled, or when nobody requested a PWM that was previously enabled
	 * by the bootloader.
	 *
	 * FIXME: Maybe the core should disable all PWM devices in
	 * pwmchip_remove(). In this case we'd only have to call
	 * clk_unprepare() after pwmchip_remove().
	 *
	 */
	if (pwm_is_enabled(pc->chip.pwms))
		clk_disable(pc->clk);

	clk_unprepare(pc->pclk);
	clk_unprepare(pc->clk);

	return pwmchip_remove(&pc->chip);
}

static struct platform_driver rockchip_pwm_driver = {
	.driver = {
		.name = "rockchip-pwm",
		.of_match_table = rockchip_pwm_dt_ids,
	},
	.probe = rockchip_pwm_probe,
	.remove = rockchip_pwm_remove,
};
module_platform_driver(rockchip_pwm_driver);

MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
MODULE_DESCRIPTION("Rockchip SoC PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
101353c8 BG	2	/*
	3	* PWM driver for Rockchip SoCs
	4	*
	5	* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
f6306299	6	* Copyright (C) 2014 ROCKCHIP, Inc.
101353c8 BG	7	*/
	8
	9	#include <linux/clk.h>
	10	#include <linux/io.h>
	11	#include <linux/module.h>
	12	#include <linux/of.h>
f6306299	13	#include <linux/of_device.h>
101353c8 BG	14	#include <linux/platform_device.h>
	15	#include <linux/pwm.h>
	16	#include <linux/time.h>
	17
101353c8 BG	18	#define PWM_CTRL_TIMER_EN (1 << 0)
	19	#define PWM_CTRL_OUTPUT_EN (1 << 3)
	20
f6306299 CW	21	#define PWM_ENABLE (1 << 0)
	22	#define PWM_CONTINUOUS (1 << 1)
	23	#define PWM_DUTY_POSITIVE (1 << 3)
7264354c	24	#define PWM_DUTY_NEGATIVE (0 << 3)
f6306299	25	#define PWM_INACTIVE_NEGATIVE (0 << 4)
7264354c	26	#define PWM_INACTIVE_POSITIVE (1 << 4)
bc834d7b	27	#define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE \| PWM_INACTIVE_POSITIVE)
f6306299	28	#define PWM_OUTPUT_LEFT (0 << 5)
3f9a3631	29	#define PWM_LOCK_EN (1 << 6)
f6306299	30	#define PWM_LP_DISABLE (0 << 8)
101353c8 BG	31
	32	struct rockchip_pwm_chip {
	33	struct pwm_chip chip;
	34	struct clk *clk;
27922ff5	35	struct clk *pclk;
f6306299	36	const struct rockchip_pwm_data *data;
101353c8 BG	37	void __iomem *base;
	38	};
	39
f6306299 CW	40	struct rockchip_pwm_regs {
	41	unsigned long duty;
	42	unsigned long period;
	43	unsigned long cntr;
	44	unsigned long ctrl;
	45	};
	46
	47	struct rockchip_pwm_data {
	48	struct rockchip_pwm_regs regs;
	49	unsigned int prescaler;
2bf1c98a	50	bool supports_polarity;
3f9a3631	51	bool supports_lock;
831b2790	52	u32 enable_conf;
f6306299 CW	53	};
f6306299 CW	54
101353c8 BG	55	static inline struct rockchip_pwm_chip to_rockchip_pwm_chip(struct pwm_chip c)
	56	{
	57	return container_of(c, struct rockchip_pwm_chip, chip);
	58	}
	59
1ebb74cf BB	60	static void rockchip_pwm_get_state(struct pwm_chip *chip,
	61	struct pwm_device *pwm,
	62	struct pwm_state *state)
	63	{
	64	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
831b2790	65	u32 enable_conf = pc->data->enable_conf;
1ebb74cf BB	66	unsigned long clk_rate;
1ebb74cf BB	67	u64 tmp;
831b2790	68	u32 val;
1ebb74cf BB	69	int ret;
1ebb74cf BB	70
27922ff5	71	ret = clk_enable(pc->pclk);
1ebb74cf BB	72	if (ret)
	73	return;
	74
	75	clk_rate = clk_get_rate(pc->clk);
	76
	77	tmp = readl_relaxed(pc->base + pc->data->regs.period);
	78	tmp = pc->data->prescaler NSEC_PER_SEC;
	79	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
	80
	81	tmp = readl_relaxed(pc->base + pc->data->regs.duty);
	82	tmp = pc->data->prescaler NSEC_PER_SEC;
831b2790	83	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
1ebb74cf	84
831b2790	85	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
cad0f296	86	state->enabled = (val & enable_conf) == enable_conf;
831b2790	87
ba73deb1 UKK	88	if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
	89	state->polarity = PWM_POLARITY_INVERSED;
	90	else
	91	state->polarity = PWM_POLARITY_NORMAL;
1ebb74cf	92
27922ff5	93	clk_disable(pc->pclk);
1ebb74cf BB	94	}
1ebb74cf BB	95
f90df9cd	96	static void rockchip_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
71523d18	97	const struct pwm_state *state)
101353c8 BG	98	{
	99	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	100	unsigned long period, duty;
	101	u64 clk_rate, div;
bc834d7b	102	u32 ctrl;
101353c8 BG	103
	104	clk_rate = clk_get_rate(pc->clk);
	105
	106	/*
	107	* Since period and duty cycle registers have a width of 32
	108	* bits, every possible input period can be obtained using the
	109	* default prescaler value for all practical clock rate values.
	110	*/
bc834d7b	111	div = clk_rate * state->period;
12f9ce4a BB	112	period = DIV_ROUND_CLOSEST_ULL(div,
12f9ce4a BB	113	pc->data->prescaler * NSEC_PER_SEC);
101353c8	114
bc834d7b	115	div = clk_rate * state->duty_cycle;
12f9ce4a	116	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
101353c8	117
3f9a3631 DW	118	/*
	119	* Lock the period and duty of previous configuration, then
	120	* change the duty and period, that would not be effective.
	121	*/
	122	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
	123	if (pc->data->supports_lock) {
	124	ctrl \|= PWM_LOCK_EN;
	125	writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
	126	}
	127
f6306299 CW	128	writel(period, pc->base + pc->data->regs.period);
f6306299 CW	129	writel(duty, pc->base + pc->data->regs.duty);
bc834d7b	130
bc834d7b DW	131	if (pc->data->supports_polarity) {
	132	ctrl &= ~PWM_POLARITY_MASK;
	133	if (state->polarity == PWM_POLARITY_INVERSED)
	134	ctrl \|= PWM_DUTY_NEGATIVE \| PWM_INACTIVE_POSITIVE;
	135	else
	136	ctrl \|= PWM_DUTY_POSITIVE \| PWM_INACTIVE_NEGATIVE;
	137	}
3f9a3631 DW	138
	139	/*
	140	* Unlock and set polarity at the same time,
	141	* the configuration of duty, period and polarity
	142	* would be effective together at next period.
	143	*/
	144	if (pc->data->supports_lock)
	145	ctrl &= ~PWM_LOCK_EN;
	146
bc834d7b	147	writel(ctrl, pc->base + pc->data->regs.ctrl);
7264354c DA	148	}
7264354c DA	149
a900152b	150	static int rockchip_pwm_enable(struct pwm_chip *chip,
bc834d7b	151	struct pwm_device *pwm,
831b2790	152	bool enable)
a900152b DW	153	{
a900152b DW	154	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
831b2790	155	u32 enable_conf = pc->data->enable_conf;
a900152b	156	int ret;
ed054693	157	u32 val;
a900152b DW	158
	159	if (enable) {
	160	ret = clk_enable(pc->clk);
	161	if (ret)
	162	return ret;
	163	}
	164
ed054693 DW	165	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
	166
	167	if (enable)
	168	val \|= enable_conf;
	169	else
	170	val &= ~enable_conf;
	171
	172	writel_relaxed(val, pc->base + pc->data->regs.ctrl);
a900152b DW	173
	174	if (!enable)
	175	clk_disable(pc->clk);
	176
	177	return 0;
	178	}
	179
831b2790	180	static int rockchip_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
71523d18	181	const struct pwm_state *state)
101353c8	182	{
831b2790	183	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
2bf1c98a BB	184	struct pwm_state curstate;
2bf1c98a BB	185	bool enabled;
ed054693	186	int ret = 0;
101353c8	187
831b2790 DW	188	ret = clk_enable(pc->pclk);
	189	if (ret)
	190	return ret;
	191
2bf1c98a BB	192	pwm_get_state(pwm, &curstate);
	193	enabled = curstate.enabled;
	194
3f9a3631 DW	195	if (state->polarity != curstate.polarity && enabled &&
3f9a3631 DW	196	!pc->data->supports_lock) {
831b2790	197	ret = rockchip_pwm_enable(chip, pwm, false);
a900152b	198	if (ret)
831b2790	199	goto out;
2bf1c98a BB	200	enabled = false;
2bf1c98a BB	201	}
101353c8	202
bc834d7b	203	rockchip_pwm_config(chip, pwm, state);
831b2790 DW	204	if (state->enabled != enabled) {
831b2790 DW	205	ret = rockchip_pwm_enable(chip, pwm, state->enabled);
a900152b	206	if (ret)
831b2790	207	goto out;
a900152b	208	}
101353c8	209
2bf1c98a	210	out:
27922ff5	211	clk_disable(pc->pclk);
2bf1c98a BB	212
2bf1c98a BB	213	return ret;
101353c8 BG	214	}
101353c8 BG	215
831b2790	216	static const struct pwm_ops rockchip_pwm_ops = {
1ebb74cf	217	.get_state = rockchip_pwm_get_state,
2bf1c98a	218	.apply = rockchip_pwm_apply,
7264354c DA	219	.owner = THIS_MODULE,
	220	};
	221
f6306299 CW	222	static const struct rockchip_pwm_data pwm_data_v1 = {
	223	.regs = {
	224	.duty = 0x04,
	225	.period = 0x08,
	226	.cntr = 0x00,
	227	.ctrl = 0x0c,
	228	},
	229	.prescaler = 2,
831b2790	230	.supports_polarity = false,
3f9a3631	231	.supports_lock = false,
831b2790	232	.enable_conf = PWM_CTRL_OUTPUT_EN \| PWM_CTRL_TIMER_EN,
f6306299 CW	233	};
	234
	235	static const struct rockchip_pwm_data pwm_data_v2 = {
	236	.regs = {
	237	.duty = 0x08,
	238	.period = 0x04,
	239	.cntr = 0x00,
	240	.ctrl = 0x0c,
	241	},
	242	.prescaler = 1,
2bf1c98a	243	.supports_polarity = true,
3f9a3631	244	.supports_lock = false,
831b2790 DW	245	.enable_conf = PWM_OUTPUT_LEFT \| PWM_LP_DISABLE \| PWM_ENABLE \|
831b2790 DW	246	PWM_CONTINUOUS,
f6306299 CW	247	};
	248
	249	static const struct rockchip_pwm_data pwm_data_vop = {
	250	.regs = {
	251	.duty = 0x08,
	252	.period = 0x04,
	253	.cntr = 0x0c,
	254	.ctrl = 0x00,
	255	},
	256	.prescaler = 1,
2bf1c98a	257	.supports_polarity = true,
3f9a3631 DW	258	.supports_lock = false,
	259	.enable_conf = PWM_OUTPUT_LEFT \| PWM_LP_DISABLE \| PWM_ENABLE \|
	260	PWM_CONTINUOUS,
	261	};
	262
	263	static const struct rockchip_pwm_data pwm_data_v3 = {
	264	.regs = {
	265	.duty = 0x08,
	266	.period = 0x04,
	267	.cntr = 0x00,
	268	.ctrl = 0x0c,
	269	},
	270	.prescaler = 1,
	271	.supports_polarity = true,
	272	.supports_lock = true,
831b2790 DW	273	.enable_conf = PWM_OUTPUT_LEFT \| PWM_LP_DISABLE \| PWM_ENABLE \|
831b2790 DW	274	PWM_CONTINUOUS,
f6306299 CW	275	};
	276
	277	static const struct of_device_id rockchip_pwm_dt_ids[] = {
	278	{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
	279	{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
	280	{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
3f9a3631	281	{ .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
f6306299 CW	282	{ /* sentinel */ }
	283	};
	284	MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
	285
101353c8 BG	286	static int rockchip_pwm_probe(struct platform_device *pdev)
101353c8 BG	287	{
f6306299	288	const struct of_device_id *id;
101353c8	289	struct rockchip_pwm_chip *pc;
457f74ab	290	u32 enable_conf, ctrl;
27922ff5	291	int ret, count;
101353c8	292
f6306299 CW	293	id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
	294	if (!id)
	295	return -EINVAL;
	296
101353c8 BG	297	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	298	if (!pc)
	299	return -ENOMEM;
	300
5119ee9e	301	pc->base = devm_platform_ioremap_resource(pdev, 0);
101353c8 BG	302	if (IS_ERR(pc->base))
	303	return PTR_ERR(pc->base);
	304
27922ff5 DW	305	pc->clk = devm_clk_get(&pdev->dev, "pwm");
	306	if (IS_ERR(pc->clk)) {
	307	pc->clk = devm_clk_get(&pdev->dev, NULL);
836719f8 KK	308	if (IS_ERR(pc->clk))
	309	return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
	310	"Can't get bus clk\n");
27922ff5 DW	311	}
	312
	313	count = of_count_phandle_with_args(pdev->dev.of_node,
	314	"clocks", "#clock-cells");
	315	if (count == 2)
	316	pc->pclk = devm_clk_get(&pdev->dev, "pclk");
	317	else
	318	pc->pclk = pc->clk;
	319
	320	if (IS_ERR(pc->pclk)) {
	321	ret = PTR_ERR(pc->pclk);
	322	if (ret != -EPROBE_DEFER)
	323	dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
	324	return ret;
	325	}
101353c8	326
48cf973c	327	ret = clk_prepare_enable(pc->clk);
27922ff5 DW	328	if (ret) {
27922ff5 DW	329	dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
101353c8	330	return ret;
27922ff5 DW	331	}
27922ff5 DW	332
d9b657a5	333	ret = clk_prepare_enable(pc->pclk);
27922ff5	334	if (ret) {
d9b657a5	335	dev_err(&pdev->dev, "Can't prepare enable APB clk: %d\n", ret);
27922ff5 DW	336	goto err_clk;
27922ff5 DW	337	}
101353c8 BG	338
	339	platform_set_drvdata(pdev, pc);
	340
f6306299	341	pc->data = id->data;
101353c8	342	pc->chip.dev = &pdev->dev;
831b2790	343	pc->chip.ops = &rockchip_pwm_ops;
101353c8 BG	344	pc->chip.base = -1;
	345	pc->chip.npwm = 1;
	346
2bf1c98a	347	if (pc->data->supports_polarity) {
7264354c DA	348	pc->chip.of_xlate = of_pwm_xlate_with_flags;
	349	pc->chip.of_pwm_n_cells = 3;
	350	}
	351
101353c8 BG	352	ret = pwmchip_add(&pc->chip);
101353c8 BG	353	if (ret < 0) {
101353c8	354	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
27922ff5	355	goto err_pclk;
101353c8 BG	356	}
101353c8 BG	357
48cf973c	358	/* Keep the PWM clk enabled if the PWM appears to be up and running. */
457f74ab SS	359	enable_conf = pc->data->enable_conf;
	360	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
	361	if ((ctrl & enable_conf) != enable_conf)
48cf973c BB	362	clk_disable(pc->clk);
48cf973c BB	363
d9b657a5 SS	364	clk_disable(pc->pclk);
d9b657a5 SS	365
27922ff5 DW	366	return 0;
	367
	368	err_pclk:
d9b657a5	369	clk_disable_unprepare(pc->pclk);
27922ff5 DW	370	err_clk:
	371	clk_disable_unprepare(pc->clk);
	372
101353c8 BG	373	return ret;
	374	}
	375
	376	static int rockchip_pwm_remove(struct platform_device *pdev)
	377	{
	378	struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
	379
48cf973c BB	380	/*
	381	* Disable the PWM clk before unpreparing it if the PWM device is still
	382	* running. This should only happen when the last PWM user left it
	383	* enabled, or when nobody requested a PWM that was previously enabled
	384	* by the bootloader.
	385	*
	386	* FIXME: Maybe the core should disable all PWM devices in
	387	* pwmchip_remove(). In this case we'd only have to call
	388	* clk_unprepare() after pwmchip_remove().
	389	*
	390	*/
	391	if (pwm_is_enabled(pc->chip.pwms))
	392	clk_disable(pc->clk);
	393
27922ff5	394	clk_unprepare(pc->pclk);
101353c8 BG	395	clk_unprepare(pc->clk);
	396
	397	return pwmchip_remove(&pc->chip);
	398	}
	399
101353c8 BG	400	static struct platform_driver rockchip_pwm_driver = {
	401	.driver = {
	402	.name = "rockchip-pwm",
	403	.of_match_table = rockchip_pwm_dt_ids,
	404	},
	405	.probe = rockchip_pwm_probe,
	406	.remove = rockchip_pwm_remove,
	407	};
	408	module_platform_driver(rockchip_pwm_driver);
	409
	410	MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
	411	MODULE_DESCRIPTION("Rockchip SoC PWM driver");
	412	MODULE_LICENSE("GPL v2");