[linux-2.6-block.git] / drivers / pwm / pwm-rockchip.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * PWM driver for Rockchip SoCs
 *
 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
 * Copyright (C) 2014 ROCKCHIP, Inc.
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/time.h>

#define PWM_CTRL_TIMER_EN	(1 << 0)
#define PWM_CTRL_OUTPUT_EN	(1 << 3)

#define PWM_ENABLE		(1 << 0)
#define PWM_CONTINUOUS		(1 << 1)
#define PWM_DUTY_POSITIVE	(1 << 3)
#define PWM_DUTY_NEGATIVE	(0 << 3)
#define PWM_INACTIVE_NEGATIVE	(0 << 4)
#define PWM_INACTIVE_POSITIVE	(1 << 4)
#define PWM_POLARITY_MASK	(PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
#define PWM_OUTPUT_LEFT		(0 << 5)
#define PWM_LOCK_EN		(1 << 6)
#define PWM_LP_DISABLE		(0 << 8)

struct rockchip_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	struct clk *pclk;
	const struct rockchip_pwm_data *data;
	void __iomem *base;
};

struct rockchip_pwm_regs {
	unsigned long duty;
	unsigned long period;
	unsigned long cntr;
	unsigned long ctrl;
};

struct rockchip_pwm_data {
	struct rockchip_pwm_regs regs;
	unsigned int prescaler;
	bool supports_polarity;
	bool supports_lock;
	u32 enable_conf;
};

static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
{
	return container_of(c, struct rockchip_pwm_chip, chip);
}

static void rockchip_pwm_get_state(struct pwm_chip *chip,
				   struct pwm_device *pwm,
				   struct pwm_state *state)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	u32 enable_conf = pc->data->enable_conf;
	unsigned long clk_rate;
	u64 tmp;
	u32 val;
	int ret;

	ret = clk_enable(pc->pclk);
	if (ret)
		return;

	clk_rate = clk_get_rate(pc->clk);

	tmp = readl_relaxed(pc->base + pc->data->regs.period);
	tmp *= pc->data->prescaler * NSEC_PER_SEC;
	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);

	tmp = readl_relaxed(pc->base + pc->data->regs.duty);
	tmp *= pc->data->prescaler * NSEC_PER_SEC;
	state->duty_cycle =  DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);

	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
	if (pc->data->supports_polarity)
		state->enabled = ((val & enable_conf) != enable_conf) ?
				 false : true;
	else
		state->enabled = ((val & enable_conf) == enable_conf) ?
				 true : false;

	if (pc->data->supports_polarity) {
		if (!(val & PWM_DUTY_POSITIVE))
			state->polarity = PWM_POLARITY_INVERSED;
	}

	clk_disable(pc->pclk);
}

static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			       struct pwm_state *state)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	unsigned long period, duty;
	u64 clk_rate, div;
	u32 ctrl;

	clk_rate = clk_get_rate(pc->clk);

	/*
	 * Since period and duty cycle registers have a width of 32
	 * bits, every possible input period can be obtained using the
	 * default prescaler value for all practical clock rate values.
	 */
	div = clk_rate * state->period;
	period = DIV_ROUND_CLOSEST_ULL(div,
				       pc->data->prescaler * NSEC_PER_SEC);

	div = clk_rate * state->duty_cycle;
	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);

	/*
	 * Lock the period and duty of previous configuration, then
	 * change the duty and period, that would not be effective.
	 */
	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
	if (pc->data->supports_lock) {
		ctrl |= PWM_LOCK_EN;
		writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
	}

	writel(period, pc->base + pc->data->regs.period);
	writel(duty, pc->base + pc->data->regs.duty);

	if (pc->data->supports_polarity) {
		ctrl &= ~PWM_POLARITY_MASK;
		if (state->polarity == PWM_POLARITY_INVERSED)
			ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
		else
			ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
	}

	/*
	 * Unlock and set polarity at the same time,
	 * the configuration of duty, period and polarity
	 * would be effective together at next period.
	 */
	if (pc->data->supports_lock)
		ctrl &= ~PWM_LOCK_EN;

	writel(ctrl, pc->base + pc->data->regs.ctrl);
}

static int rockchip_pwm_enable(struct pwm_chip *chip,
			       struct pwm_device *pwm,
			       bool enable)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	u32 enable_conf = pc->data->enable_conf;
	int ret;
	u32 val;

	if (enable) {
		ret = clk_enable(pc->clk);
		if (ret)
			return ret;
	}

	val = readl_relaxed(pc->base + pc->data->regs.ctrl);

	if (enable)
		val |= enable_conf;
	else
		val &= ~enable_conf;

	writel_relaxed(val, pc->base + pc->data->regs.ctrl);

	if (!enable)
		clk_disable(pc->clk);

	return 0;
}

static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			      struct pwm_state *state)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	struct pwm_state curstate;
	bool enabled;
	int ret = 0;

	ret = clk_enable(pc->pclk);
	if (ret)
		return ret;

	pwm_get_state(pwm, &curstate);
	enabled = curstate.enabled;

	if (state->polarity != curstate.polarity && enabled &&
	    !pc->data->supports_lock) {
		ret = rockchip_pwm_enable(chip, pwm, false);
		if (ret)
			goto out;
		enabled = false;
	}

	rockchip_pwm_config(chip, pwm, state);
	if (state->enabled != enabled) {
		ret = rockchip_pwm_enable(chip, pwm, state->enabled);
		if (ret)
			goto out;
	}

	/*
	 * Update the state with the real hardware, which can differ a bit
	 * because of period/duty_cycle approximation.
	 */
	rockchip_pwm_get_state(chip, pwm, state);

out:
	clk_disable(pc->pclk);

	return ret;
}

static const struct pwm_ops rockchip_pwm_ops = {
	.get_state = rockchip_pwm_get_state,
	.apply = rockchip_pwm_apply,
	.owner = THIS_MODULE,
};

static const struct rockchip_pwm_data pwm_data_v1 = {
	.regs = {
		.duty = 0x04,
		.period = 0x08,
		.cntr = 0x00,
		.ctrl = 0x0c,
	},
	.prescaler = 2,
	.supports_polarity = false,
	.supports_lock = false,
	.enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
};

static const struct rockchip_pwm_data pwm_data_v2 = {
	.regs = {
		.duty = 0x08,
		.period = 0x04,
		.cntr = 0x00,
		.ctrl = 0x0c,
	},
	.prescaler = 1,
	.supports_polarity = true,
	.supports_lock = false,
	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
		       PWM_CONTINUOUS,
};

static const struct rockchip_pwm_data pwm_data_vop = {
	.regs = {
		.duty = 0x08,
		.period = 0x04,
		.cntr = 0x0c,
		.ctrl = 0x00,
	},
	.prescaler = 1,
	.supports_polarity = true,
	.supports_lock = false,
	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
		       PWM_CONTINUOUS,
};

static const struct rockchip_pwm_data pwm_data_v3 = {
	.regs = {
		.duty = 0x08,
		.period = 0x04,
		.cntr = 0x00,
		.ctrl = 0x0c,
	},
	.prescaler = 1,
	.supports_polarity = true,
	.supports_lock = true,
	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
		       PWM_CONTINUOUS,
};

static const struct of_device_id rockchip_pwm_dt_ids[] = {
	{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
	{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
	{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
	{ .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);

static int rockchip_pwm_probe(struct platform_device *pdev)
{
	const struct of_device_id *id;
	struct rockchip_pwm_chip *pc;
	struct resource *r;
	int ret, count;

	id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
	if (!id)
		return -EINVAL;

	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pc->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(pc->base))
		return PTR_ERR(pc->base);

	pc->clk = devm_clk_get(&pdev->dev, "pwm");
	if (IS_ERR(pc->clk)) {
		pc->clk = devm_clk_get(&pdev->dev, NULL);
		if (IS_ERR(pc->clk)) {
			ret = PTR_ERR(pc->clk);
			if (ret != -EPROBE_DEFER)
				dev_err(&pdev->dev, "Can't get bus clk: %d\n",
					ret);
			return ret;
		}
	}

	count = of_count_phandle_with_args(pdev->dev.of_node,
					   "clocks", "#clock-cells");
	if (count == 2)
		pc->pclk = devm_clk_get(&pdev->dev, "pclk");
	else
		pc->pclk = pc->clk;

	if (IS_ERR(pc->pclk)) {
		ret = PTR_ERR(pc->pclk);
		if (ret != -EPROBE_DEFER)
			dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
		return ret;
	}

	ret = clk_prepare_enable(pc->clk);
	if (ret) {
		dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
		return ret;
	}

	ret = clk_prepare(pc->pclk);
	if (ret) {
		dev_err(&pdev->dev, "Can't prepare APB clk: %d\n", ret);
		goto err_clk;
	}

	platform_set_drvdata(pdev, pc);

	pc->data = id->data;
	pc->chip.dev = &pdev->dev;
	pc->chip.ops = &rockchip_pwm_ops;
	pc->chip.base = -1;
	pc->chip.npwm = 1;

	if (pc->data->supports_polarity) {
		pc->chip.of_xlate = of_pwm_xlate_with_flags;
		pc->chip.of_pwm_n_cells = 3;
	}

	ret = pwmchip_add(&pc->chip);
	if (ret < 0) {
		clk_unprepare(pc->clk);
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		goto err_pclk;
	}

	/* Keep the PWM clk enabled if the PWM appears to be up and running. */
	if (!pwm_is_enabled(pc->chip.pwms))
		clk_disable(pc->clk);

	return 0;

err_pclk:
	clk_unprepare(pc->pclk);
err_clk:
	clk_disable_unprepare(pc->clk);

	return ret;
}

static int rockchip_pwm_remove(struct platform_device *pdev)
{
	struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);

	/*
	 * Disable the PWM clk before unpreparing it if the PWM device is still
	 * running. This should only happen when the last PWM user left it
	 * enabled, or when nobody requested a PWM that was previously enabled
	 * by the bootloader.
	 *
	 * FIXME: Maybe the core should disable all PWM devices in
	 * pwmchip_remove(). In this case we'd only have to call
	 * clk_unprepare() after pwmchip_remove().
	 *
	 */
	if (pwm_is_enabled(pc->chip.pwms))
		clk_disable(pc->clk);

	clk_unprepare(pc->pclk);
	clk_unprepare(pc->clk);

	return pwmchip_remove(&pc->chip);
}

static struct platform_driver rockchip_pwm_driver = {
	.driver = {
		.name = "rockchip-pwm",
		.of_match_table = rockchip_pwm_dt_ids,
	},
	.probe = rockchip_pwm_probe,
	.remove = rockchip_pwm_remove,
};
module_platform_driver(rockchip_pwm_driver);

MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
MODULE_DESCRIPTION("Rockchip SoC PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
101353c8 BG	2	/*
	3	* PWM driver for Rockchip SoCs
	4	*
	5	* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
f6306299	6	* Copyright (C) 2014 ROCKCHIP, Inc.
101353c8 BG	7	*/
	8
	9	#include <linux/clk.h>
	10	#include <linux/io.h>
	11	#include <linux/module.h>
	12	#include <linux/of.h>
f6306299	13	#include <linux/of_device.h>
101353c8 BG	14	#include <linux/platform_device.h>
	15	#include <linux/pwm.h>
	16	#include <linux/time.h>
	17
101353c8 BG	18	#define PWM_CTRL_TIMER_EN (1 << 0)
	19	#define PWM_CTRL_OUTPUT_EN (1 << 3)
	20
f6306299 CW	21	#define PWM_ENABLE (1 << 0)
	22	#define PWM_CONTINUOUS (1 << 1)
	23	#define PWM_DUTY_POSITIVE (1 << 3)
7264354c	24	#define PWM_DUTY_NEGATIVE (0 << 3)
f6306299	25	#define PWM_INACTIVE_NEGATIVE (0 << 4)
7264354c	26	#define PWM_INACTIVE_POSITIVE (1 << 4)
bc834d7b	27	#define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE \| PWM_INACTIVE_POSITIVE)
f6306299	28	#define PWM_OUTPUT_LEFT (0 << 5)
3f9a3631	29	#define PWM_LOCK_EN (1 << 6)
f6306299	30	#define PWM_LP_DISABLE (0 << 8)
101353c8 BG	31
	32	struct rockchip_pwm_chip {
	33	struct pwm_chip chip;
	34	struct clk *clk;
27922ff5	35	struct clk *pclk;
f6306299	36	const struct rockchip_pwm_data *data;
101353c8 BG	37	void __iomem *base;
	38	};
	39
f6306299 CW	40	struct rockchip_pwm_regs {
	41	unsigned long duty;
	42	unsigned long period;
	43	unsigned long cntr;
	44	unsigned long ctrl;
	45	};
	46
	47	struct rockchip_pwm_data {
	48	struct rockchip_pwm_regs regs;
	49	unsigned int prescaler;
2bf1c98a	50	bool supports_polarity;
3f9a3631	51	bool supports_lock;
831b2790	52	u32 enable_conf;
f6306299 CW	53	};
f6306299 CW	54
101353c8 BG	55	static inline struct rockchip_pwm_chip to_rockchip_pwm_chip(struct pwm_chip c)
	56	{
	57	return container_of(c, struct rockchip_pwm_chip, chip);
	58	}
	59
1ebb74cf BB	60	static void rockchip_pwm_get_state(struct pwm_chip *chip,
	61	struct pwm_device *pwm,
	62	struct pwm_state *state)
	63	{
	64	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
831b2790	65	u32 enable_conf = pc->data->enable_conf;
1ebb74cf BB	66	unsigned long clk_rate;
1ebb74cf BB	67	u64 tmp;
831b2790	68	u32 val;
1ebb74cf BB	69	int ret;
1ebb74cf BB	70
27922ff5	71	ret = clk_enable(pc->pclk);
1ebb74cf BB	72	if (ret)
	73	return;
	74
	75	clk_rate = clk_get_rate(pc->clk);
	76
	77	tmp = readl_relaxed(pc->base + pc->data->regs.period);
	78	tmp = pc->data->prescaler NSEC_PER_SEC;
	79	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
	80
	81	tmp = readl_relaxed(pc->base + pc->data->regs.duty);
	82	tmp = pc->data->prescaler NSEC_PER_SEC;
831b2790	83	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
1ebb74cf	84
831b2790 DW	85	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
	86	if (pc->data->supports_polarity)
	87	state->enabled = ((val & enable_conf) != enable_conf) ?
	88	false : true;
	89	else
	90	state->enabled = ((val & enable_conf) == enable_conf) ?
	91	true : false;
	92
	93	if (pc->data->supports_polarity) {
	94	if (!(val & PWM_DUTY_POSITIVE))
	95	state->polarity = PWM_POLARITY_INVERSED;
	96	}
1ebb74cf	97
27922ff5	98	clk_disable(pc->pclk);
1ebb74cf BB	99	}
1ebb74cf BB	100
f90df9cd	101	static void rockchip_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
bc834d7b	102	struct pwm_state *state)
101353c8 BG	103	{
	104	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	105	unsigned long period, duty;
	106	u64 clk_rate, div;
bc834d7b	107	u32 ctrl;
101353c8 BG	108
	109	clk_rate = clk_get_rate(pc->clk);
	110
	111	/*
	112	* Since period and duty cycle registers have a width of 32
	113	* bits, every possible input period can be obtained using the
	114	* default prescaler value for all practical clock rate values.
	115	*/
bc834d7b	116	div = clk_rate * state->period;
12f9ce4a BB	117	period = DIV_ROUND_CLOSEST_ULL(div,
12f9ce4a BB	118	pc->data->prescaler * NSEC_PER_SEC);
101353c8	119
bc834d7b	120	div = clk_rate * state->duty_cycle;
12f9ce4a	121	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
101353c8	122
3f9a3631 DW	123	/*
	124	* Lock the period and duty of previous configuration, then
	125	* change the duty and period, that would not be effective.
	126	*/
	127	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
	128	if (pc->data->supports_lock) {
	129	ctrl \|= PWM_LOCK_EN;
	130	writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
	131	}
	132
f6306299 CW	133	writel(period, pc->base + pc->data->regs.period);
f6306299 CW	134	writel(duty, pc->base + pc->data->regs.duty);
bc834d7b	135
bc834d7b DW	136	if (pc->data->supports_polarity) {
	137	ctrl &= ~PWM_POLARITY_MASK;
	138	if (state->polarity == PWM_POLARITY_INVERSED)
	139	ctrl \|= PWM_DUTY_NEGATIVE \| PWM_INACTIVE_POSITIVE;
	140	else
	141	ctrl \|= PWM_DUTY_POSITIVE \| PWM_INACTIVE_NEGATIVE;
	142	}
3f9a3631 DW	143
	144	/*
	145	* Unlock and set polarity at the same time,
	146	* the configuration of duty, period and polarity
	147	* would be effective together at next period.
	148	*/
	149	if (pc->data->supports_lock)
	150	ctrl &= ~PWM_LOCK_EN;
	151
bc834d7b	152	writel(ctrl, pc->base + pc->data->regs.ctrl);
7264354c DA	153	}
7264354c DA	154
a900152b	155	static int rockchip_pwm_enable(struct pwm_chip *chip,
bc834d7b	156	struct pwm_device *pwm,
831b2790	157	bool enable)
a900152b DW	158	{
a900152b DW	159	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
831b2790	160	u32 enable_conf = pc->data->enable_conf;
a900152b	161	int ret;
ed054693	162	u32 val;
a900152b DW	163
	164	if (enable) {
	165	ret = clk_enable(pc->clk);
	166	if (ret)
	167	return ret;
	168	}
	169
ed054693 DW	170	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
	171
	172	if (enable)
	173	val \|= enable_conf;
	174	else
	175	val &= ~enable_conf;
	176
	177	writel_relaxed(val, pc->base + pc->data->regs.ctrl);
a900152b DW	178
	179	if (!enable)
	180	clk_disable(pc->clk);
	181
	182	return 0;
	183	}
	184
831b2790 DW	185	static int rockchip_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
831b2790 DW	186	struct pwm_state *state)
101353c8	187	{
831b2790	188	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
2bf1c98a BB	189	struct pwm_state curstate;
2bf1c98a BB	190	bool enabled;
ed054693	191	int ret = 0;
101353c8	192
831b2790 DW	193	ret = clk_enable(pc->pclk);
	194	if (ret)
	195	return ret;
	196
2bf1c98a BB	197	pwm_get_state(pwm, &curstate);
	198	enabled = curstate.enabled;
	199
3f9a3631 DW	200	if (state->polarity != curstate.polarity && enabled &&
3f9a3631 DW	201	!pc->data->supports_lock) {
831b2790	202	ret = rockchip_pwm_enable(chip, pwm, false);
a900152b	203	if (ret)
831b2790	204	goto out;
2bf1c98a BB	205	enabled = false;
2bf1c98a BB	206	}
101353c8	207
bc834d7b	208	rockchip_pwm_config(chip, pwm, state);
831b2790 DW	209	if (state->enabled != enabled) {
831b2790 DW	210	ret = rockchip_pwm_enable(chip, pwm, state->enabled);
a900152b	211	if (ret)
831b2790	212	goto out;
a900152b	213	}
101353c8	214
2bf1c98a BB	215	/*
	216	* Update the state with the real hardware, which can differ a bit
	217	* because of period/duty_cycle approximation.
	218	*/
	219	rockchip_pwm_get_state(chip, pwm, state);
101353c8	220
2bf1c98a	221	out:
27922ff5	222	clk_disable(pc->pclk);
2bf1c98a BB	223
2bf1c98a BB	224	return ret;
101353c8 BG	225	}
101353c8 BG	226
831b2790	227	static const struct pwm_ops rockchip_pwm_ops = {
1ebb74cf	228	.get_state = rockchip_pwm_get_state,
2bf1c98a	229	.apply = rockchip_pwm_apply,
7264354c DA	230	.owner = THIS_MODULE,
	231	};
	232
f6306299 CW	233	static const struct rockchip_pwm_data pwm_data_v1 = {
	234	.regs = {
	235	.duty = 0x04,
	236	.period = 0x08,
	237	.cntr = 0x00,
	238	.ctrl = 0x0c,
	239	},
	240	.prescaler = 2,
831b2790	241	.supports_polarity = false,
3f9a3631	242	.supports_lock = false,
831b2790	243	.enable_conf = PWM_CTRL_OUTPUT_EN \| PWM_CTRL_TIMER_EN,
f6306299 CW	244	};
	245
	246	static const struct rockchip_pwm_data pwm_data_v2 = {
	247	.regs = {
	248	.duty = 0x08,
	249	.period = 0x04,
	250	.cntr = 0x00,
	251	.ctrl = 0x0c,
	252	},
	253	.prescaler = 1,
2bf1c98a	254	.supports_polarity = true,
3f9a3631	255	.supports_lock = false,
831b2790 DW	256	.enable_conf = PWM_OUTPUT_LEFT \| PWM_LP_DISABLE \| PWM_ENABLE \|
831b2790 DW	257	PWM_CONTINUOUS,
f6306299 CW	258	};
	259
	260	static const struct rockchip_pwm_data pwm_data_vop = {
	261	.regs = {
	262	.duty = 0x08,
	263	.period = 0x04,
	264	.cntr = 0x0c,
	265	.ctrl = 0x00,
	266	},
	267	.prescaler = 1,
2bf1c98a	268	.supports_polarity = true,
3f9a3631 DW	269	.supports_lock = false,
	270	.enable_conf = PWM_OUTPUT_LEFT \| PWM_LP_DISABLE \| PWM_ENABLE \|
	271	PWM_CONTINUOUS,
	272	};
	273
	274	static const struct rockchip_pwm_data pwm_data_v3 = {
	275	.regs = {
	276	.duty = 0x08,
	277	.period = 0x04,
	278	.cntr = 0x00,
	279	.ctrl = 0x0c,
	280	},
	281	.prescaler = 1,
	282	.supports_polarity = true,
	283	.supports_lock = true,
831b2790 DW	284	.enable_conf = PWM_OUTPUT_LEFT \| PWM_LP_DISABLE \| PWM_ENABLE \|
831b2790 DW	285	PWM_CONTINUOUS,
f6306299 CW	286	};
	287
	288	static const struct of_device_id rockchip_pwm_dt_ids[] = {
	289	{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
	290	{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
	291	{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
3f9a3631	292	{ .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
f6306299 CW	293	{ /* sentinel */ }
	294	};
	295	MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
	296
101353c8 BG	297	static int rockchip_pwm_probe(struct platform_device *pdev)
101353c8 BG	298	{
f6306299	299	const struct of_device_id *id;
101353c8 BG	300	struct rockchip_pwm_chip *pc;
101353c8 BG	301	struct resource *r;
27922ff5	302	int ret, count;
101353c8	303
f6306299 CW	304	id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
	305	if (!id)
	306	return -EINVAL;
	307
101353c8 BG	308	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	309	if (!pc)
	310	return -ENOMEM;
	311
	312	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	313	pc->base = devm_ioremap_resource(&pdev->dev, r);
	314	if (IS_ERR(pc->base))
	315	return PTR_ERR(pc->base);
	316
27922ff5 DW	317	pc->clk = devm_clk_get(&pdev->dev, "pwm");
	318	if (IS_ERR(pc->clk)) {
	319	pc->clk = devm_clk_get(&pdev->dev, NULL);
	320	if (IS_ERR(pc->clk)) {
	321	ret = PTR_ERR(pc->clk);
	322	if (ret != -EPROBE_DEFER)
	323	dev_err(&pdev->dev, "Can't get bus clk: %d\n",
	324	ret);
	325	return ret;
	326	}
	327	}
	328
	329	count = of_count_phandle_with_args(pdev->dev.of_node,
	330	"clocks", "#clock-cells");
	331	if (count == 2)
	332	pc->pclk = devm_clk_get(&pdev->dev, "pclk");
	333	else
	334	pc->pclk = pc->clk;
	335
	336	if (IS_ERR(pc->pclk)) {
	337	ret = PTR_ERR(pc->pclk);
	338	if (ret != -EPROBE_DEFER)
	339	dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
	340	return ret;
	341	}
101353c8	342
48cf973c	343	ret = clk_prepare_enable(pc->clk);
27922ff5 DW	344	if (ret) {
27922ff5 DW	345	dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
101353c8	346	return ret;
27922ff5 DW	347	}
	348
	349	ret = clk_prepare(pc->pclk);
	350	if (ret) {
	351	dev_err(&pdev->dev, "Can't prepare APB clk: %d\n", ret);
	352	goto err_clk;
	353	}
101353c8 BG	354
	355	platform_set_drvdata(pdev, pc);
	356
f6306299	357	pc->data = id->data;
101353c8	358	pc->chip.dev = &pdev->dev;
831b2790	359	pc->chip.ops = &rockchip_pwm_ops;
101353c8 BG	360	pc->chip.base = -1;
	361	pc->chip.npwm = 1;
	362
2bf1c98a	363	if (pc->data->supports_polarity) {
7264354c DA	364	pc->chip.of_xlate = of_pwm_xlate_with_flags;
	365	pc->chip.of_pwm_n_cells = 3;
	366	}
	367
101353c8 BG	368	ret = pwmchip_add(&pc->chip);
	369	if (ret < 0) {
	370	clk_unprepare(pc->clk);
	371	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
27922ff5	372	goto err_pclk;
101353c8 BG	373	}
101353c8 BG	374
48cf973c BB	375	/* Keep the PWM clk enabled if the PWM appears to be up and running. */
	376	if (!pwm_is_enabled(pc->chip.pwms))
	377	clk_disable(pc->clk);
	378
27922ff5 DW	379	return 0;
	380
	381	err_pclk:
	382	clk_unprepare(pc->pclk);
	383	err_clk:
	384	clk_disable_unprepare(pc->clk);
	385
101353c8 BG	386	return ret;
	387	}
	388
	389	static int rockchip_pwm_remove(struct platform_device *pdev)
	390	{
	391	struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
	392
48cf973c BB	393	/*
	394	* Disable the PWM clk before unpreparing it if the PWM device is still
	395	* running. This should only happen when the last PWM user left it
	396	* enabled, or when nobody requested a PWM that was previously enabled
	397	* by the bootloader.
	398	*
	399	* FIXME: Maybe the core should disable all PWM devices in
	400	* pwmchip_remove(). In this case we'd only have to call
	401	* clk_unprepare() after pwmchip_remove().
	402	*
	403	*/
	404	if (pwm_is_enabled(pc->chip.pwms))
	405	clk_disable(pc->clk);
	406
27922ff5	407	clk_unprepare(pc->pclk);
101353c8 BG	408	clk_unprepare(pc->clk);
	409
	410	return pwmchip_remove(&pc->chip);
	411	}
	412
101353c8 BG	413	static struct platform_driver rockchip_pwm_driver = {
	414	.driver = {
	415	.name = "rockchip-pwm",
	416	.of_match_table = rockchip_pwm_dt_ids,
	417	},
	418	.probe = rockchip_pwm_probe,
	419	.remove = rockchip_pwm_remove,
	420	};
	421	module_platform_driver(rockchip_pwm_driver);
	422
	423	MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
	424	MODULE_DESCRIPTION("Rockchip SoC PWM driver");
	425	MODULE_LICENSE("GPL v2");