[linux-2.6-block.git] / drivers / pwm / pwm-rockchip.c

/*
 * PWM driver for Rockchip SoCs
 *
 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
 * Copyright (C) 2014 ROCKCHIP, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/time.h>

#define PWM_CTRL_TIMER_EN	(1 << 0)
#define PWM_CTRL_OUTPUT_EN	(1 << 3)

#define PWM_ENABLE		(1 << 0)
#define PWM_CONTINUOUS		(1 << 1)
#define PWM_DUTY_POSITIVE	(1 << 3)
#define PWM_DUTY_NEGATIVE	(0 << 3)
#define PWM_INACTIVE_NEGATIVE	(0 << 4)
#define PWM_INACTIVE_POSITIVE	(1 << 4)
#define PWM_POLARITY_MASK	(PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
#define PWM_OUTPUT_LEFT		(0 << 5)
#define PWM_LOCK_EN		(1 << 6)
#define PWM_LP_DISABLE		(0 << 8)

struct rockchip_pwm_chip {
	struct pwm_chip chip;
	struct clk *clk;
	struct clk *pclk;
	const struct rockchip_pwm_data *data;
	void __iomem *base;
};

struct rockchip_pwm_regs {
	unsigned long duty;
	unsigned long period;
	unsigned long cntr;
	unsigned long ctrl;
};

struct rockchip_pwm_data {
	struct rockchip_pwm_regs regs;
	unsigned int prescaler;
	bool supports_polarity;
	bool supports_lock;
	u32 enable_conf;
};

static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
{
	return container_of(c, struct rockchip_pwm_chip, chip);
}

static void rockchip_pwm_get_state(struct pwm_chip *chip,
				   struct pwm_device *pwm,
				   struct pwm_state *state)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	u32 enable_conf = pc->data->enable_conf;
	unsigned long clk_rate;
	u64 tmp;
	u32 val;
	int ret;

	ret = clk_enable(pc->pclk);
	if (ret)
		return;

	clk_rate = clk_get_rate(pc->clk);

	tmp = readl_relaxed(pc->base + pc->data->regs.period);
	tmp *= pc->data->prescaler * NSEC_PER_SEC;
	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);

	tmp = readl_relaxed(pc->base + pc->data->regs.duty);
	tmp *= pc->data->prescaler * NSEC_PER_SEC;
	state->duty_cycle =  DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);

	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
	if (pc->data->supports_polarity)
		state->enabled = ((val & enable_conf) != enable_conf) ?
				 false : true;
	else
		state->enabled = ((val & enable_conf) == enable_conf) ?
				 true : false;

	if (pc->data->supports_polarity) {
		if (!(val & PWM_DUTY_POSITIVE))
			state->polarity = PWM_POLARITY_INVERSED;
	}

	clk_disable(pc->pclk);
}

static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			       struct pwm_state *state)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	unsigned long period, duty;
	u64 clk_rate, div;
	u32 ctrl;

	clk_rate = clk_get_rate(pc->clk);

	/*
	 * Since period and duty cycle registers have a width of 32
	 * bits, every possible input period can be obtained using the
	 * default prescaler value for all practical clock rate values.
	 */
	div = clk_rate * state->period;
	period = DIV_ROUND_CLOSEST_ULL(div,
				       pc->data->prescaler * NSEC_PER_SEC);

	div = clk_rate * state->duty_cycle;
	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);

	/*
	 * Lock the period and duty of previous configuration, then
	 * change the duty and period, that would not be effective.
	 */
	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
	if (pc->data->supports_lock) {
		ctrl |= PWM_LOCK_EN;
		writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
	}

	writel(period, pc->base + pc->data->regs.period);
	writel(duty, pc->base + pc->data->regs.duty);

	if (pc->data->supports_polarity) {
		ctrl &= ~PWM_POLARITY_MASK;
		if (state->polarity == PWM_POLARITY_INVERSED)
			ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
		else
			ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
	}

	/*
	 * Unlock and set polarity at the same time,
	 * the configuration of duty, period and polarity
	 * would be effective together at next period.
	 */
	if (pc->data->supports_lock)
		ctrl &= ~PWM_LOCK_EN;

	writel(ctrl, pc->base + pc->data->regs.ctrl);
}

static int rockchip_pwm_enable(struct pwm_chip *chip,
			       struct pwm_device *pwm,
			       bool enable)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	u32 enable_conf = pc->data->enable_conf;
	int ret;
	u32 val;

	if (enable) {
		ret = clk_enable(pc->clk);
		if (ret)
			return ret;
	}

	val = readl_relaxed(pc->base + pc->data->regs.ctrl);

	if (enable)
		val |= enable_conf;
	else
		val &= ~enable_conf;

	writel_relaxed(val, pc->base + pc->data->regs.ctrl);

	if (!enable)
		clk_disable(pc->clk);

	return 0;
}

static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			      struct pwm_state *state)
{
	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	struct pwm_state curstate;
	bool enabled;
	int ret = 0;

	ret = clk_enable(pc->pclk);
	if (ret)
		return ret;

	pwm_get_state(pwm, &curstate);
	enabled = curstate.enabled;

	if (state->polarity != curstate.polarity && enabled &&
	    !pc->data->supports_lock) {
		ret = rockchip_pwm_enable(chip, pwm, false);
		if (ret)
			goto out;
		enabled = false;
	}

	rockchip_pwm_config(chip, pwm, state);
	if (state->enabled != enabled) {
		ret = rockchip_pwm_enable(chip, pwm, state->enabled);
		if (ret)
			goto out;
	}

	/*
	 * Update the state with the real hardware, which can differ a bit
	 * because of period/duty_cycle approximation.
	 */
	rockchip_pwm_get_state(chip, pwm, state);

out:
	clk_disable(pc->pclk);

	return ret;
}

static const struct pwm_ops rockchip_pwm_ops = {
	.get_state = rockchip_pwm_get_state,
	.apply = rockchip_pwm_apply,
	.owner = THIS_MODULE,
};

static const struct rockchip_pwm_data pwm_data_v1 = {
	.regs = {
		.duty = 0x04,
		.period = 0x08,
		.cntr = 0x00,
		.ctrl = 0x0c,
	},
	.prescaler = 2,
	.supports_polarity = false,
	.supports_lock = false,
	.enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
};

static const struct rockchip_pwm_data pwm_data_v2 = {
	.regs = {
		.duty = 0x08,
		.period = 0x04,
		.cntr = 0x00,
		.ctrl = 0x0c,
	},
	.prescaler = 1,
	.supports_polarity = true,
	.supports_lock = false,
	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
		       PWM_CONTINUOUS,
};

static const struct rockchip_pwm_data pwm_data_vop = {
	.regs = {
		.duty = 0x08,
		.period = 0x04,
		.cntr = 0x0c,
		.ctrl = 0x00,
	},
	.prescaler = 1,
	.supports_polarity = true,
	.supports_lock = false,
	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
		       PWM_CONTINUOUS,
};

static const struct rockchip_pwm_data pwm_data_v3 = {
	.regs = {
		.duty = 0x08,
		.period = 0x04,
		.cntr = 0x00,
		.ctrl = 0x0c,
	},
	.prescaler = 1,
	.supports_polarity = true,
	.supports_lock = true,
	.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
		       PWM_CONTINUOUS,
};

static const struct of_device_id rockchip_pwm_dt_ids[] = {
	{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
	{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
	{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
	{ .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);

static int rockchip_pwm_probe(struct platform_device *pdev)
{
	const struct of_device_id *id;
	struct rockchip_pwm_chip *pc;
	struct resource *r;
	int ret, count;

	id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
	if (!id)
		return -EINVAL;

	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	if (!pc)
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	pc->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(pc->base))
		return PTR_ERR(pc->base);

	pc->clk = devm_clk_get(&pdev->dev, "pwm");
	if (IS_ERR(pc->clk)) {
		pc->clk = devm_clk_get(&pdev->dev, NULL);
		if (IS_ERR(pc->clk)) {
			ret = PTR_ERR(pc->clk);
			if (ret != -EPROBE_DEFER)
				dev_err(&pdev->dev, "Can't get bus clk: %d\n",
					ret);
			return ret;
		}
	}

	count = of_count_phandle_with_args(pdev->dev.of_node,
					   "clocks", "#clock-cells");
	if (count == 2)
		pc->pclk = devm_clk_get(&pdev->dev, "pclk");
	else
		pc->pclk = pc->clk;

	if (IS_ERR(pc->pclk)) {
		ret = PTR_ERR(pc->pclk);
		if (ret != -EPROBE_DEFER)
			dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
		return ret;
	}

	ret = clk_prepare_enable(pc->clk);
	if (ret) {
		dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
		return ret;
	}

	ret = clk_prepare(pc->pclk);
	if (ret) {
		dev_err(&pdev->dev, "Can't prepare APB clk: %d\n", ret);
		goto err_clk;
	}

	platform_set_drvdata(pdev, pc);

	pc->data = id->data;
	pc->chip.dev = &pdev->dev;
	pc->chip.ops = &rockchip_pwm_ops;
	pc->chip.base = -1;
	pc->chip.npwm = 1;

	if (pc->data->supports_polarity) {
		pc->chip.of_xlate = of_pwm_xlate_with_flags;
		pc->chip.of_pwm_n_cells = 3;
	}

	ret = pwmchip_add(&pc->chip);
	if (ret < 0) {
		clk_unprepare(pc->clk);
		dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
		goto err_pclk;
	}

	/* Keep the PWM clk enabled if the PWM appears to be up and running. */
	if (!pwm_is_enabled(pc->chip.pwms))
		clk_disable(pc->clk);

	return 0;

err_pclk:
	clk_unprepare(pc->pclk);
err_clk:
	clk_disable_unprepare(pc->clk);

	return ret;
}

static int rockchip_pwm_remove(struct platform_device *pdev)
{
	struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);

	/*
	 * Disable the PWM clk before unpreparing it if the PWM device is still
	 * running. This should only happen when the last PWM user left it
	 * enabled, or when nobody requested a PWM that was previously enabled
	 * by the bootloader.
	 *
	 * FIXME: Maybe the core should disable all PWM devices in
	 * pwmchip_remove(). In this case we'd only have to call
	 * clk_unprepare() after pwmchip_remove().
	 *
	 */
	if (pwm_is_enabled(pc->chip.pwms))
		clk_disable(pc->clk);

	clk_unprepare(pc->pclk);
	clk_unprepare(pc->clk);

	return pwmchip_remove(&pc->chip);
}

static struct platform_driver rockchip_pwm_driver = {
	.driver = {
		.name = "rockchip-pwm",
		.of_match_table = rockchip_pwm_dt_ids,
	},
	.probe = rockchip_pwm_probe,
	.remove = rockchip_pwm_remove,
};
module_platform_driver(rockchip_pwm_driver);

MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
MODULE_DESCRIPTION("Rockchip SoC PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
101353c8 BG	1	/*
	2	* PWM driver for Rockchip SoCs
	3	*
	4	* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
f6306299	5	* Copyright (C) 2014 ROCKCHIP, Inc.
101353c8 BG	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License
	9	* version 2 as published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/clk.h>
	13	#include <linux/io.h>
	14	#include <linux/module.h>
	15	#include <linux/of.h>
f6306299	16	#include <linux/of_device.h>
101353c8 BG	17	#include <linux/platform_device.h>
	18	#include <linux/pwm.h>
	19	#include <linux/time.h>
	20
101353c8 BG	21	#define PWM_CTRL_TIMER_EN (1 << 0)
	22	#define PWM_CTRL_OUTPUT_EN (1 << 3)
	23
f6306299 CW	24	#define PWM_ENABLE (1 << 0)
	25	#define PWM_CONTINUOUS (1 << 1)
	26	#define PWM_DUTY_POSITIVE (1 << 3)
7264354c	27	#define PWM_DUTY_NEGATIVE (0 << 3)
f6306299	28	#define PWM_INACTIVE_NEGATIVE (0 << 4)
7264354c	29	#define PWM_INACTIVE_POSITIVE (1 << 4)
bc834d7b	30	#define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE \| PWM_INACTIVE_POSITIVE)
f6306299	31	#define PWM_OUTPUT_LEFT (0 << 5)
3f9a3631	32	#define PWM_LOCK_EN (1 << 6)
f6306299	33	#define PWM_LP_DISABLE (0 << 8)
101353c8 BG	34
	35	struct rockchip_pwm_chip {
	36	struct pwm_chip chip;
	37	struct clk *clk;
27922ff5	38	struct clk *pclk;
f6306299	39	const struct rockchip_pwm_data *data;
101353c8 BG	40	void __iomem *base;
	41	};
	42
f6306299 CW	43	struct rockchip_pwm_regs {
	44	unsigned long duty;
	45	unsigned long period;
	46	unsigned long cntr;
	47	unsigned long ctrl;
	48	};
	49
	50	struct rockchip_pwm_data {
	51	struct rockchip_pwm_regs regs;
	52	unsigned int prescaler;
2bf1c98a	53	bool supports_polarity;
3f9a3631	54	bool supports_lock;
831b2790	55	u32 enable_conf;
f6306299 CW	56	};
f6306299 CW	57
101353c8 BG	58	static inline struct rockchip_pwm_chip to_rockchip_pwm_chip(struct pwm_chip c)
	59	{
	60	return container_of(c, struct rockchip_pwm_chip, chip);
	61	}
	62
1ebb74cf BB	63	static void rockchip_pwm_get_state(struct pwm_chip *chip,
	64	struct pwm_device *pwm,
	65	struct pwm_state *state)
	66	{
	67	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
831b2790	68	u32 enable_conf = pc->data->enable_conf;
1ebb74cf BB	69	unsigned long clk_rate;
1ebb74cf BB	70	u64 tmp;
831b2790	71	u32 val;
1ebb74cf BB	72	int ret;
1ebb74cf BB	73
27922ff5	74	ret = clk_enable(pc->pclk);
1ebb74cf BB	75	if (ret)
	76	return;
	77
	78	clk_rate = clk_get_rate(pc->clk);
	79
	80	tmp = readl_relaxed(pc->base + pc->data->regs.period);
	81	tmp = pc->data->prescaler NSEC_PER_SEC;
	82	state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
	83
	84	tmp = readl_relaxed(pc->base + pc->data->regs.duty);
	85	tmp = pc->data->prescaler NSEC_PER_SEC;
831b2790	86	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
1ebb74cf	87
831b2790 DW	88	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
	89	if (pc->data->supports_polarity)
	90	state->enabled = ((val & enable_conf) != enable_conf) ?
	91	false : true;
	92	else
	93	state->enabled = ((val & enable_conf) == enable_conf) ?
	94	true : false;
	95
	96	if (pc->data->supports_polarity) {
	97	if (!(val & PWM_DUTY_POSITIVE))
	98	state->polarity = PWM_POLARITY_INVERSED;
	99	}
1ebb74cf	100
27922ff5	101	clk_disable(pc->pclk);
1ebb74cf BB	102	}
1ebb74cf BB	103
f90df9cd	104	static void rockchip_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
bc834d7b	105	struct pwm_state *state)
101353c8 BG	106	{
	107	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
	108	unsigned long period, duty;
	109	u64 clk_rate, div;
bc834d7b	110	u32 ctrl;
101353c8 BG	111
	112	clk_rate = clk_get_rate(pc->clk);
	113
	114	/*
	115	* Since period and duty cycle registers have a width of 32
	116	* bits, every possible input period can be obtained using the
	117	* default prescaler value for all practical clock rate values.
	118	*/
bc834d7b	119	div = clk_rate * state->period;
12f9ce4a BB	120	period = DIV_ROUND_CLOSEST_ULL(div,
12f9ce4a BB	121	pc->data->prescaler * NSEC_PER_SEC);
101353c8	122
bc834d7b	123	div = clk_rate * state->duty_cycle;
12f9ce4a	124	duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
101353c8	125
3f9a3631 DW	126	/*
	127	* Lock the period and duty of previous configuration, then
	128	* change the duty and period, that would not be effective.
	129	*/
	130	ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
	131	if (pc->data->supports_lock) {
	132	ctrl \|= PWM_LOCK_EN;
	133	writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
	134	}
	135
f6306299 CW	136	writel(period, pc->base + pc->data->regs.period);
f6306299 CW	137	writel(duty, pc->base + pc->data->regs.duty);
bc834d7b	138
bc834d7b DW	139	if (pc->data->supports_polarity) {
	140	ctrl &= ~PWM_POLARITY_MASK;
	141	if (state->polarity == PWM_POLARITY_INVERSED)
	142	ctrl \|= PWM_DUTY_NEGATIVE \| PWM_INACTIVE_POSITIVE;
	143	else
	144	ctrl \|= PWM_DUTY_POSITIVE \| PWM_INACTIVE_NEGATIVE;
	145	}
3f9a3631 DW	146
	147	/*
	148	* Unlock and set polarity at the same time,
	149	* the configuration of duty, period and polarity
	150	* would be effective together at next period.
	151	*/
	152	if (pc->data->supports_lock)
	153	ctrl &= ~PWM_LOCK_EN;
	154
bc834d7b	155	writel(ctrl, pc->base + pc->data->regs.ctrl);
7264354c DA	156	}
7264354c DA	157
a900152b	158	static int rockchip_pwm_enable(struct pwm_chip *chip,
bc834d7b	159	struct pwm_device *pwm,
831b2790	160	bool enable)
a900152b DW	161	{
a900152b DW	162	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
831b2790	163	u32 enable_conf = pc->data->enable_conf;
a900152b	164	int ret;
ed054693	165	u32 val;
a900152b DW	166
	167	if (enable) {
	168	ret = clk_enable(pc->clk);
	169	if (ret)
	170	return ret;
	171	}
	172
ed054693 DW	173	val = readl_relaxed(pc->base + pc->data->regs.ctrl);
	174
	175	if (enable)
	176	val \|= enable_conf;
	177	else
	178	val &= ~enable_conf;
	179
	180	writel_relaxed(val, pc->base + pc->data->regs.ctrl);
a900152b DW	181
	182	if (!enable)
	183	clk_disable(pc->clk);
	184
	185	return 0;
	186	}
	187
831b2790 DW	188	static int rockchip_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
831b2790 DW	189	struct pwm_state *state)
101353c8	190	{
831b2790	191	struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
2bf1c98a BB	192	struct pwm_state curstate;
2bf1c98a BB	193	bool enabled;
ed054693	194	int ret = 0;
101353c8	195
831b2790 DW	196	ret = clk_enable(pc->pclk);
	197	if (ret)
	198	return ret;
	199
2bf1c98a BB	200	pwm_get_state(pwm, &curstate);
	201	enabled = curstate.enabled;
	202
3f9a3631 DW	203	if (state->polarity != curstate.polarity && enabled &&
3f9a3631 DW	204	!pc->data->supports_lock) {
831b2790	205	ret = rockchip_pwm_enable(chip, pwm, false);
a900152b	206	if (ret)
831b2790	207	goto out;
2bf1c98a BB	208	enabled = false;
2bf1c98a BB	209	}
101353c8	210
bc834d7b	211	rockchip_pwm_config(chip, pwm, state);
831b2790 DW	212	if (state->enabled != enabled) {
831b2790 DW	213	ret = rockchip_pwm_enable(chip, pwm, state->enabled);
a900152b	214	if (ret)
831b2790	215	goto out;
a900152b	216	}
101353c8	217
2bf1c98a BB	218	/*
	219	* Update the state with the real hardware, which can differ a bit
	220	* because of period/duty_cycle approximation.
	221	*/
	222	rockchip_pwm_get_state(chip, pwm, state);
101353c8	223
2bf1c98a	224	out:
27922ff5	225	clk_disable(pc->pclk);
2bf1c98a BB	226
2bf1c98a BB	227	return ret;
101353c8 BG	228	}
101353c8 BG	229
831b2790	230	static const struct pwm_ops rockchip_pwm_ops = {
1ebb74cf	231	.get_state = rockchip_pwm_get_state,
2bf1c98a	232	.apply = rockchip_pwm_apply,
7264354c DA	233	.owner = THIS_MODULE,
	234	};
	235
f6306299 CW	236	static const struct rockchip_pwm_data pwm_data_v1 = {
	237	.regs = {
	238	.duty = 0x04,
	239	.period = 0x08,
	240	.cntr = 0x00,
	241	.ctrl = 0x0c,
	242	},
	243	.prescaler = 2,
831b2790	244	.supports_polarity = false,
3f9a3631	245	.supports_lock = false,
831b2790	246	.enable_conf = PWM_CTRL_OUTPUT_EN \| PWM_CTRL_TIMER_EN,
f6306299 CW	247	};
	248
	249	static const struct rockchip_pwm_data pwm_data_v2 = {
	250	.regs = {
	251	.duty = 0x08,
	252	.period = 0x04,
	253	.cntr = 0x00,
	254	.ctrl = 0x0c,
	255	},
	256	.prescaler = 1,
2bf1c98a	257	.supports_polarity = true,
3f9a3631	258	.supports_lock = false,
831b2790 DW	259	.enable_conf = PWM_OUTPUT_LEFT \| PWM_LP_DISABLE \| PWM_ENABLE \|
831b2790 DW	260	PWM_CONTINUOUS,
f6306299 CW	261	};
	262
	263	static const struct rockchip_pwm_data pwm_data_vop = {
	264	.regs = {
	265	.duty = 0x08,
	266	.period = 0x04,
	267	.cntr = 0x0c,
	268	.ctrl = 0x00,
	269	},
	270	.prescaler = 1,
2bf1c98a	271	.supports_polarity = true,
3f9a3631 DW	272	.supports_lock = false,
	273	.enable_conf = PWM_OUTPUT_LEFT \| PWM_LP_DISABLE \| PWM_ENABLE \|
	274	PWM_CONTINUOUS,
	275	};
	276
	277	static const struct rockchip_pwm_data pwm_data_v3 = {
	278	.regs = {
	279	.duty = 0x08,
	280	.period = 0x04,
	281	.cntr = 0x00,
	282	.ctrl = 0x0c,
	283	},
	284	.prescaler = 1,
	285	.supports_polarity = true,
	286	.supports_lock = true,
831b2790 DW	287	.enable_conf = PWM_OUTPUT_LEFT \| PWM_LP_DISABLE \| PWM_ENABLE \|
831b2790 DW	288	PWM_CONTINUOUS,
f6306299 CW	289	};
	290
	291	static const struct of_device_id rockchip_pwm_dt_ids[] = {
	292	{ .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
	293	{ .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
	294	{ .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
3f9a3631	295	{ .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
f6306299 CW	296	{ /* sentinel */ }
	297	};
	298	MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
	299
101353c8 BG	300	static int rockchip_pwm_probe(struct platform_device *pdev)
101353c8 BG	301	{
f6306299	302	const struct of_device_id *id;
101353c8 BG	303	struct rockchip_pwm_chip *pc;
101353c8 BG	304	struct resource *r;
27922ff5	305	int ret, count;
101353c8	306
f6306299 CW	307	id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
	308	if (!id)
	309	return -EINVAL;
	310
101353c8 BG	311	pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
	312	if (!pc)
	313	return -ENOMEM;
	314
	315	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	316	pc->base = devm_ioremap_resource(&pdev->dev, r);
	317	if (IS_ERR(pc->base))
	318	return PTR_ERR(pc->base);
	319
27922ff5 DW	320	pc->clk = devm_clk_get(&pdev->dev, "pwm");
	321	if (IS_ERR(pc->clk)) {
	322	pc->clk = devm_clk_get(&pdev->dev, NULL);
	323	if (IS_ERR(pc->clk)) {
	324	ret = PTR_ERR(pc->clk);
	325	if (ret != -EPROBE_DEFER)
	326	dev_err(&pdev->dev, "Can't get bus clk: %d\n",
	327	ret);
	328	return ret;
	329	}
	330	}
	331
	332	count = of_count_phandle_with_args(pdev->dev.of_node,
	333	"clocks", "#clock-cells");
	334	if (count == 2)
	335	pc->pclk = devm_clk_get(&pdev->dev, "pclk");
	336	else
	337	pc->pclk = pc->clk;
	338
	339	if (IS_ERR(pc->pclk)) {
	340	ret = PTR_ERR(pc->pclk);
	341	if (ret != -EPROBE_DEFER)
	342	dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
	343	return ret;
	344	}
101353c8	345
48cf973c	346	ret = clk_prepare_enable(pc->clk);
27922ff5 DW	347	if (ret) {
27922ff5 DW	348	dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
101353c8	349	return ret;
27922ff5 DW	350	}
	351
	352	ret = clk_prepare(pc->pclk);
	353	if (ret) {
	354	dev_err(&pdev->dev, "Can't prepare APB clk: %d\n", ret);
	355	goto err_clk;
	356	}
101353c8 BG	357
	358	platform_set_drvdata(pdev, pc);
	359
f6306299	360	pc->data = id->data;
101353c8	361	pc->chip.dev = &pdev->dev;
831b2790	362	pc->chip.ops = &rockchip_pwm_ops;
101353c8 BG	363	pc->chip.base = -1;
	364	pc->chip.npwm = 1;
	365
2bf1c98a	366	if (pc->data->supports_polarity) {
7264354c DA	367	pc->chip.of_xlate = of_pwm_xlate_with_flags;
	368	pc->chip.of_pwm_n_cells = 3;
	369	}
	370
101353c8 BG	371	ret = pwmchip_add(&pc->chip);
	372	if (ret < 0) {
	373	clk_unprepare(pc->clk);
	374	dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
27922ff5	375	goto err_pclk;
101353c8 BG	376	}
101353c8 BG	377
48cf973c BB	378	/* Keep the PWM clk enabled if the PWM appears to be up and running. */
	379	if (!pwm_is_enabled(pc->chip.pwms))
	380	clk_disable(pc->clk);
	381
27922ff5 DW	382	return 0;
	383
	384	err_pclk:
	385	clk_unprepare(pc->pclk);
	386	err_clk:
	387	clk_disable_unprepare(pc->clk);
	388
101353c8 BG	389	return ret;
	390	}
	391
	392	static int rockchip_pwm_remove(struct platform_device *pdev)
	393	{
	394	struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
	395
48cf973c BB	396	/*
	397	* Disable the PWM clk before unpreparing it if the PWM device is still
	398	* running. This should only happen when the last PWM user left it
	399	* enabled, or when nobody requested a PWM that was previously enabled
	400	* by the bootloader.
	401	*
	402	* FIXME: Maybe the core should disable all PWM devices in
	403	* pwmchip_remove(). In this case we'd only have to call
	404	* clk_unprepare() after pwmchip_remove().
	405	*
	406	*/
	407	if (pwm_is_enabled(pc->chip.pwms))
	408	clk_disable(pc->clk);
	409
27922ff5	410	clk_unprepare(pc->pclk);
101353c8 BG	411	clk_unprepare(pc->clk);
	412
	413	return pwmchip_remove(&pc->chip);
	414	}
	415
101353c8 BG	416	static struct platform_driver rockchip_pwm_driver = {
	417	.driver = {
	418	.name = "rockchip-pwm",
	419	.of_match_table = rockchip_pwm_dt_ids,
	420	},
	421	.probe = rockchip_pwm_probe,
	422	.remove = rockchip_pwm_remove,
	423	};
	424	module_platform_driver(rockchip_pwm_driver);
	425
	426	MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
	427	MODULE_DESCRIPTION("Rockchip SoC PWM driver");
	428	MODULE_LICENSE("GPL v2");