Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
101353c8 BG |
2 | /* |
3 | * PWM driver for Rockchip SoCs | |
4 | * | |
5 | * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> | |
f6306299 | 6 | * Copyright (C) 2014 ROCKCHIP, Inc. |
101353c8 BG |
7 | */ |
8 | ||
9 | #include <linux/clk.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of.h> | |
f6306299 | 13 | #include <linux/of_device.h> |
101353c8 BG |
14 | #include <linux/platform_device.h> |
15 | #include <linux/pwm.h> | |
16 | #include <linux/time.h> | |
17 | ||
101353c8 BG |
18 | #define PWM_CTRL_TIMER_EN (1 << 0) |
19 | #define PWM_CTRL_OUTPUT_EN (1 << 3) | |
20 | ||
f6306299 CW |
21 | #define PWM_ENABLE (1 << 0) |
22 | #define PWM_CONTINUOUS (1 << 1) | |
23 | #define PWM_DUTY_POSITIVE (1 << 3) | |
7264354c | 24 | #define PWM_DUTY_NEGATIVE (0 << 3) |
f6306299 | 25 | #define PWM_INACTIVE_NEGATIVE (0 << 4) |
7264354c | 26 | #define PWM_INACTIVE_POSITIVE (1 << 4) |
bc834d7b | 27 | #define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE) |
f6306299 | 28 | #define PWM_OUTPUT_LEFT (0 << 5) |
3f9a3631 | 29 | #define PWM_LOCK_EN (1 << 6) |
f6306299 | 30 | #define PWM_LP_DISABLE (0 << 8) |
101353c8 BG |
31 | |
32 | struct rockchip_pwm_chip { | |
33 | struct pwm_chip chip; | |
34 | struct clk *clk; | |
27922ff5 | 35 | struct clk *pclk; |
f6306299 | 36 | const struct rockchip_pwm_data *data; |
101353c8 BG |
37 | void __iomem *base; |
38 | }; | |
39 | ||
f6306299 CW |
40 | struct rockchip_pwm_regs { |
41 | unsigned long duty; | |
42 | unsigned long period; | |
43 | unsigned long cntr; | |
44 | unsigned long ctrl; | |
45 | }; | |
46 | ||
47 | struct rockchip_pwm_data { | |
48 | struct rockchip_pwm_regs regs; | |
49 | unsigned int prescaler; | |
2bf1c98a | 50 | bool supports_polarity; |
3f9a3631 | 51 | bool supports_lock; |
831b2790 | 52 | u32 enable_conf; |
f6306299 CW |
53 | }; |
54 | ||
101353c8 BG |
55 | static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) |
56 | { | |
57 | return container_of(c, struct rockchip_pwm_chip, chip); | |
58 | } | |
59 | ||
1ebb74cf BB |
60 | static void rockchip_pwm_get_state(struct pwm_chip *chip, |
61 | struct pwm_device *pwm, | |
62 | struct pwm_state *state) | |
63 | { | |
64 | struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); | |
831b2790 | 65 | u32 enable_conf = pc->data->enable_conf; |
1ebb74cf BB |
66 | unsigned long clk_rate; |
67 | u64 tmp; | |
831b2790 | 68 | u32 val; |
1ebb74cf BB |
69 | int ret; |
70 | ||
27922ff5 | 71 | ret = clk_enable(pc->pclk); |
1ebb74cf BB |
72 | if (ret) |
73 | return; | |
74 | ||
11be938a SS |
75 | ret = clk_enable(pc->clk); |
76 | if (ret) | |
77 | return; | |
78 | ||
1ebb74cf BB |
79 | clk_rate = clk_get_rate(pc->clk); |
80 | ||
81 | tmp = readl_relaxed(pc->base + pc->data->regs.period); | |
82 | tmp *= pc->data->prescaler * NSEC_PER_SEC; | |
83 | state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); | |
84 | ||
85 | tmp = readl_relaxed(pc->base + pc->data->regs.duty); | |
86 | tmp *= pc->data->prescaler * NSEC_PER_SEC; | |
831b2790 | 87 | state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); |
1ebb74cf | 88 | |
831b2790 | 89 | val = readl_relaxed(pc->base + pc->data->regs.ctrl); |
cad0f296 | 90 | state->enabled = (val & enable_conf) == enable_conf; |
831b2790 | 91 | |
ba73deb1 UKK |
92 | if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE)) |
93 | state->polarity = PWM_POLARITY_INVERSED; | |
94 | else | |
95 | state->polarity = PWM_POLARITY_NORMAL; | |
1ebb74cf | 96 | |
11be938a | 97 | clk_disable(pc->clk); |
27922ff5 | 98 | clk_disable(pc->pclk); |
1ebb74cf BB |
99 | } |
100 | ||
f90df9cd | 101 | static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
71523d18 | 102 | const struct pwm_state *state) |
101353c8 BG |
103 | { |
104 | struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); | |
105 | unsigned long period, duty; | |
106 | u64 clk_rate, div; | |
bc834d7b | 107 | u32 ctrl; |
101353c8 BG |
108 | |
109 | clk_rate = clk_get_rate(pc->clk); | |
110 | ||
111 | /* | |
112 | * Since period and duty cycle registers have a width of 32 | |
113 | * bits, every possible input period can be obtained using the | |
114 | * default prescaler value for all practical clock rate values. | |
115 | */ | |
bc834d7b | 116 | div = clk_rate * state->period; |
12f9ce4a BB |
117 | period = DIV_ROUND_CLOSEST_ULL(div, |
118 | pc->data->prescaler * NSEC_PER_SEC); | |
101353c8 | 119 | |
bc834d7b | 120 | div = clk_rate * state->duty_cycle; |
12f9ce4a | 121 | duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); |
101353c8 | 122 | |
3f9a3631 DW |
123 | /* |
124 | * Lock the period and duty of previous configuration, then | |
125 | * change the duty and period, that would not be effective. | |
126 | */ | |
127 | ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); | |
128 | if (pc->data->supports_lock) { | |
129 | ctrl |= PWM_LOCK_EN; | |
130 | writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl); | |
131 | } | |
132 | ||
f6306299 CW |
133 | writel(period, pc->base + pc->data->regs.period); |
134 | writel(duty, pc->base + pc->data->regs.duty); | |
bc834d7b | 135 | |
bc834d7b DW |
136 | if (pc->data->supports_polarity) { |
137 | ctrl &= ~PWM_POLARITY_MASK; | |
138 | if (state->polarity == PWM_POLARITY_INVERSED) | |
139 | ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE; | |
140 | else | |
141 | ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE; | |
142 | } | |
3f9a3631 DW |
143 | |
144 | /* | |
145 | * Unlock and set polarity at the same time, | |
146 | * the configuration of duty, period and polarity | |
147 | * would be effective together at next period. | |
148 | */ | |
149 | if (pc->data->supports_lock) | |
150 | ctrl &= ~PWM_LOCK_EN; | |
151 | ||
bc834d7b | 152 | writel(ctrl, pc->base + pc->data->regs.ctrl); |
7264354c DA |
153 | } |
154 | ||
a900152b | 155 | static int rockchip_pwm_enable(struct pwm_chip *chip, |
bc834d7b | 156 | struct pwm_device *pwm, |
831b2790 | 157 | bool enable) |
a900152b DW |
158 | { |
159 | struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); | |
831b2790 | 160 | u32 enable_conf = pc->data->enable_conf; |
a900152b | 161 | int ret; |
ed054693 | 162 | u32 val; |
a900152b DW |
163 | |
164 | if (enable) { | |
165 | ret = clk_enable(pc->clk); | |
166 | if (ret) | |
167 | return ret; | |
168 | } | |
169 | ||
ed054693 DW |
170 | val = readl_relaxed(pc->base + pc->data->regs.ctrl); |
171 | ||
172 | if (enable) | |
173 | val |= enable_conf; | |
174 | else | |
175 | val &= ~enable_conf; | |
176 | ||
177 | writel_relaxed(val, pc->base + pc->data->regs.ctrl); | |
a900152b DW |
178 | |
179 | if (!enable) | |
180 | clk_disable(pc->clk); | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
831b2790 | 185 | static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
71523d18 | 186 | const struct pwm_state *state) |
101353c8 | 187 | { |
831b2790 | 188 | struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); |
2bf1c98a BB |
189 | struct pwm_state curstate; |
190 | bool enabled; | |
ed054693 | 191 | int ret = 0; |
101353c8 | 192 | |
831b2790 DW |
193 | ret = clk_enable(pc->pclk); |
194 | if (ret) | |
195 | return ret; | |
196 | ||
11be938a SS |
197 | ret = clk_enable(pc->clk); |
198 | if (ret) | |
199 | return ret; | |
200 | ||
2bf1c98a BB |
201 | pwm_get_state(pwm, &curstate); |
202 | enabled = curstate.enabled; | |
203 | ||
3f9a3631 DW |
204 | if (state->polarity != curstate.polarity && enabled && |
205 | !pc->data->supports_lock) { | |
831b2790 | 206 | ret = rockchip_pwm_enable(chip, pwm, false); |
a900152b | 207 | if (ret) |
831b2790 | 208 | goto out; |
2bf1c98a BB |
209 | enabled = false; |
210 | } | |
101353c8 | 211 | |
bc834d7b | 212 | rockchip_pwm_config(chip, pwm, state); |
831b2790 DW |
213 | if (state->enabled != enabled) { |
214 | ret = rockchip_pwm_enable(chip, pwm, state->enabled); | |
a900152b | 215 | if (ret) |
831b2790 | 216 | goto out; |
a900152b | 217 | } |
101353c8 | 218 | |
2bf1c98a | 219 | out: |
11be938a | 220 | clk_disable(pc->clk); |
27922ff5 | 221 | clk_disable(pc->pclk); |
2bf1c98a BB |
222 | |
223 | return ret; | |
101353c8 BG |
224 | } |
225 | ||
831b2790 | 226 | static const struct pwm_ops rockchip_pwm_ops = { |
1ebb74cf | 227 | .get_state = rockchip_pwm_get_state, |
2bf1c98a | 228 | .apply = rockchip_pwm_apply, |
7264354c DA |
229 | .owner = THIS_MODULE, |
230 | }; | |
231 | ||
f6306299 CW |
232 | static const struct rockchip_pwm_data pwm_data_v1 = { |
233 | .regs = { | |
234 | .duty = 0x04, | |
235 | .period = 0x08, | |
236 | .cntr = 0x00, | |
237 | .ctrl = 0x0c, | |
238 | }, | |
239 | .prescaler = 2, | |
831b2790 | 240 | .supports_polarity = false, |
3f9a3631 | 241 | .supports_lock = false, |
831b2790 | 242 | .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN, |
f6306299 CW |
243 | }; |
244 | ||
245 | static const struct rockchip_pwm_data pwm_data_v2 = { | |
246 | .regs = { | |
247 | .duty = 0x08, | |
248 | .period = 0x04, | |
249 | .cntr = 0x00, | |
250 | .ctrl = 0x0c, | |
251 | }, | |
252 | .prescaler = 1, | |
2bf1c98a | 253 | .supports_polarity = true, |
3f9a3631 | 254 | .supports_lock = false, |
831b2790 DW |
255 | .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | |
256 | PWM_CONTINUOUS, | |
f6306299 CW |
257 | }; |
258 | ||
259 | static const struct rockchip_pwm_data pwm_data_vop = { | |
260 | .regs = { | |
261 | .duty = 0x08, | |
262 | .period = 0x04, | |
263 | .cntr = 0x0c, | |
264 | .ctrl = 0x00, | |
265 | }, | |
266 | .prescaler = 1, | |
2bf1c98a | 267 | .supports_polarity = true, |
3f9a3631 DW |
268 | .supports_lock = false, |
269 | .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | | |
270 | PWM_CONTINUOUS, | |
271 | }; | |
272 | ||
273 | static const struct rockchip_pwm_data pwm_data_v3 = { | |
274 | .regs = { | |
275 | .duty = 0x08, | |
276 | .period = 0x04, | |
277 | .cntr = 0x00, | |
278 | .ctrl = 0x0c, | |
279 | }, | |
280 | .prescaler = 1, | |
281 | .supports_polarity = true, | |
282 | .supports_lock = true, | |
831b2790 DW |
283 | .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | |
284 | PWM_CONTINUOUS, | |
f6306299 CW |
285 | }; |
286 | ||
287 | static const struct of_device_id rockchip_pwm_dt_ids[] = { | |
288 | { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1}, | |
289 | { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2}, | |
290 | { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop}, | |
3f9a3631 | 291 | { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3}, |
f6306299 CW |
292 | { /* sentinel */ } |
293 | }; | |
294 | MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); | |
295 | ||
101353c8 BG |
296 | static int rockchip_pwm_probe(struct platform_device *pdev) |
297 | { | |
f6306299 | 298 | const struct of_device_id *id; |
101353c8 | 299 | struct rockchip_pwm_chip *pc; |
457f74ab | 300 | u32 enable_conf, ctrl; |
d21ba5d6 | 301 | bool enabled; |
27922ff5 | 302 | int ret, count; |
101353c8 | 303 | |
f6306299 CW |
304 | id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev); |
305 | if (!id) | |
306 | return -EINVAL; | |
307 | ||
101353c8 BG |
308 | pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); |
309 | if (!pc) | |
310 | return -ENOMEM; | |
311 | ||
5119ee9e | 312 | pc->base = devm_platform_ioremap_resource(pdev, 0); |
101353c8 BG |
313 | if (IS_ERR(pc->base)) |
314 | return PTR_ERR(pc->base); | |
315 | ||
27922ff5 DW |
316 | pc->clk = devm_clk_get(&pdev->dev, "pwm"); |
317 | if (IS_ERR(pc->clk)) { | |
318 | pc->clk = devm_clk_get(&pdev->dev, NULL); | |
836719f8 KK |
319 | if (IS_ERR(pc->clk)) |
320 | return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk), | |
c9f809d0 | 321 | "Can't get PWM clk\n"); |
27922ff5 DW |
322 | } |
323 | ||
324 | count = of_count_phandle_with_args(pdev->dev.of_node, | |
325 | "clocks", "#clock-cells"); | |
326 | if (count == 2) | |
327 | pc->pclk = devm_clk_get(&pdev->dev, "pclk"); | |
328 | else | |
329 | pc->pclk = pc->clk; | |
330 | ||
331 | if (IS_ERR(pc->pclk)) { | |
332 | ret = PTR_ERR(pc->pclk); | |
333 | if (ret != -EPROBE_DEFER) | |
334 | dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret); | |
335 | return ret; | |
336 | } | |
101353c8 | 337 | |
48cf973c | 338 | ret = clk_prepare_enable(pc->clk); |
27922ff5 | 339 | if (ret) { |
c9f809d0 | 340 | dev_err(&pdev->dev, "Can't prepare enable PWM clk: %d\n", ret); |
101353c8 | 341 | return ret; |
27922ff5 DW |
342 | } |
343 | ||
d9b657a5 | 344 | ret = clk_prepare_enable(pc->pclk); |
27922ff5 | 345 | if (ret) { |
d9b657a5 | 346 | dev_err(&pdev->dev, "Can't prepare enable APB clk: %d\n", ret); |
27922ff5 DW |
347 | goto err_clk; |
348 | } | |
101353c8 BG |
349 | |
350 | platform_set_drvdata(pdev, pc); | |
351 | ||
f6306299 | 352 | pc->data = id->data; |
101353c8 | 353 | pc->chip.dev = &pdev->dev; |
831b2790 | 354 | pc->chip.ops = &rockchip_pwm_ops; |
101353c8 BG |
355 | pc->chip.npwm = 1; |
356 | ||
2bf1c98a | 357 | if (pc->data->supports_polarity) { |
7264354c DA |
358 | pc->chip.of_xlate = of_pwm_xlate_with_flags; |
359 | pc->chip.of_pwm_n_cells = 3; | |
360 | } | |
361 | ||
d21ba5d6 SS |
362 | enable_conf = pc->data->enable_conf; |
363 | ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); | |
364 | enabled = (ctrl & enable_conf) == enable_conf; | |
365 | ||
101353c8 BG |
366 | ret = pwmchip_add(&pc->chip); |
367 | if (ret < 0) { | |
101353c8 | 368 | dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); |
27922ff5 | 369 | goto err_pclk; |
101353c8 BG |
370 | } |
371 | ||
48cf973c | 372 | /* Keep the PWM clk enabled if the PWM appears to be up and running. */ |
d21ba5d6 | 373 | if (!enabled) |
48cf973c BB |
374 | clk_disable(pc->clk); |
375 | ||
d9b657a5 SS |
376 | clk_disable(pc->pclk); |
377 | ||
27922ff5 DW |
378 | return 0; |
379 | ||
380 | err_pclk: | |
d9b657a5 | 381 | clk_disable_unprepare(pc->pclk); |
27922ff5 DW |
382 | err_clk: |
383 | clk_disable_unprepare(pc->clk); | |
384 | ||
101353c8 BG |
385 | return ret; |
386 | } | |
387 | ||
388 | static int rockchip_pwm_remove(struct platform_device *pdev) | |
389 | { | |
390 | struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev); | |
391 | ||
48cf973c BB |
392 | /* |
393 | * Disable the PWM clk before unpreparing it if the PWM device is still | |
394 | * running. This should only happen when the last PWM user left it | |
395 | * enabled, or when nobody requested a PWM that was previously enabled | |
396 | * by the bootloader. | |
397 | * | |
398 | * FIXME: Maybe the core should disable all PWM devices in | |
399 | * pwmchip_remove(). In this case we'd only have to call | |
400 | * clk_unprepare() after pwmchip_remove(). | |
401 | * | |
402 | */ | |
403 | if (pwm_is_enabled(pc->chip.pwms)) | |
404 | clk_disable(pc->clk); | |
405 | ||
27922ff5 | 406 | clk_unprepare(pc->pclk); |
101353c8 BG |
407 | clk_unprepare(pc->clk); |
408 | ||
409 | return pwmchip_remove(&pc->chip); | |
410 | } | |
411 | ||
101353c8 BG |
412 | static struct platform_driver rockchip_pwm_driver = { |
413 | .driver = { | |
414 | .name = "rockchip-pwm", | |
415 | .of_match_table = rockchip_pwm_dt_ids, | |
416 | }, | |
417 | .probe = rockchip_pwm_probe, | |
418 | .remove = rockchip_pwm_remove, | |
419 | }; | |
420 | module_platform_driver(rockchip_pwm_driver); | |
421 | ||
422 | MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); | |
423 | MODULE_DESCRIPTION("Rockchip SoC PWM driver"); | |
424 | MODULE_LICENSE("GPL v2"); |