[linux-block.git] / drivers / pwm / pwm-renesas-tpu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * R-Mobile TPU PWM driver
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#define TPU_CHANNEL_MAX		4

#define TPU_TSTR		0x00	/* Timer start register (shared) */

#define TPU_TCRn		0x00	/* Timer control register */
#define TPU_TCR_CCLR_NONE	(0 << 5)
#define TPU_TCR_CCLR_TGRA	(1 << 5)
#define TPU_TCR_CCLR_TGRB	(2 << 5)
#define TPU_TCR_CCLR_TGRC	(5 << 5)
#define TPU_TCR_CCLR_TGRD	(6 << 5)
#define TPU_TCR_CKEG_RISING	(0 << 3)
#define TPU_TCR_CKEG_FALLING	(1 << 3)
#define TPU_TCR_CKEG_BOTH	(2 << 3)
#define TPU_TMDRn		0x04	/* Timer mode register */
#define TPU_TMDR_BFWT		(1 << 6)
#define TPU_TMDR_BFB		(1 << 5)
#define TPU_TMDR_BFA		(1 << 4)
#define TPU_TMDR_MD_NORMAL	(0 << 0)
#define TPU_TMDR_MD_PWM		(2 << 0)
#define TPU_TIORn		0x08	/* Timer I/O control register */
#define TPU_TIOR_IOA_0		(0 << 0)
#define TPU_TIOR_IOA_0_CLR	(1 << 0)
#define TPU_TIOR_IOA_0_SET	(2 << 0)
#define TPU_TIOR_IOA_0_TOGGLE	(3 << 0)
#define TPU_TIOR_IOA_1		(4 << 0)
#define TPU_TIOR_IOA_1_CLR	(5 << 0)
#define TPU_TIOR_IOA_1_SET	(6 << 0)
#define TPU_TIOR_IOA_1_TOGGLE	(7 << 0)
#define TPU_TIERn		0x0c	/* Timer interrupt enable register */
#define TPU_TSRn		0x10	/* Timer status register */
#define TPU_TCNTn		0x14	/* Timer counter */
#define TPU_TGRAn		0x18	/* Timer general register A */
#define TPU_TGRBn		0x1c	/* Timer general register B */
#define TPU_TGRCn		0x20	/* Timer general register C */
#define TPU_TGRDn		0x24	/* Timer general register D */

#define TPU_CHANNEL_OFFSET	0x10
#define TPU_CHANNEL_SIZE	0x40

enum tpu_pin_state {
	TPU_PIN_INACTIVE,		/* Pin is driven inactive */
	TPU_PIN_PWM,			/* Pin is driven by PWM */
	TPU_PIN_ACTIVE,			/* Pin is driven active */
};

struct tpu_device;

struct tpu_pwm_device {
	bool timer_on;			/* Whether the timer is running */

	struct tpu_device *tpu;
	unsigned int channel;		/* Channel number in the TPU */

	enum pwm_polarity polarity;
	unsigned int prescaler;
	u16 period;
	u16 duty;
};

struct tpu_device {
	struct platform_device *pdev;
	struct pwm_chip chip;
	spinlock_t lock;

	void __iomem *base;
	struct clk *clk;
};

#define to_tpu_device(c)	container_of(c, struct tpu_device, chip)

static void tpu_pwm_write(struct tpu_pwm_device *tpd, int reg_nr, u16 value)
{
	void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET
			   + tpd->channel * TPU_CHANNEL_SIZE;

	iowrite16(value, base + reg_nr);
}

static void tpu_pwm_set_pin(struct tpu_pwm_device *tpd,
			    enum tpu_pin_state state)
{
	static const char * const states[] = { "inactive", "PWM", "active" };

	dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n",
		tpd->channel, states[state]);

	switch (state) {
	case TPU_PIN_INACTIVE:
		tpu_pwm_write(tpd, TPU_TIORn,
			      tpd->polarity == PWM_POLARITY_INVERSED ?
			      TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0);
		break;
	case TPU_PIN_PWM:
		tpu_pwm_write(tpd, TPU_TIORn,
			      tpd->polarity == PWM_POLARITY_INVERSED ?
			      TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR);
		break;
	case TPU_PIN_ACTIVE:
		tpu_pwm_write(tpd, TPU_TIORn,
			      tpd->polarity == PWM_POLARITY_INVERSED ?
			      TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1);
		break;
	}
}

static void tpu_pwm_start_stop(struct tpu_pwm_device *tpd, int start)
{
	unsigned long flags;
	u16 value;

	spin_lock_irqsave(&tpd->tpu->lock, flags);
	value = ioread16(tpd->tpu->base + TPU_TSTR);

	if (start)
		value |= 1 << tpd->channel;
	else
		value &= ~(1 << tpd->channel);

	iowrite16(value, tpd->tpu->base + TPU_TSTR);
	spin_unlock_irqrestore(&tpd->tpu->lock, flags);
}

static int tpu_pwm_timer_start(struct tpu_pwm_device *tpd)
{
	int ret;

	if (!tpd->timer_on) {
		/* Wake up device and enable clock. */
		pm_runtime_get_sync(&tpd->tpu->pdev->dev);
		ret = clk_prepare_enable(tpd->tpu->clk);
		if (ret) {
			dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n");
			return ret;
		}
		tpd->timer_on = true;
	}

	/*
	 * Make sure the channel is stopped, as we need to reconfigure it
	 * completely. First drive the pin to the inactive state to avoid
	 * glitches.
	 */
	tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
	tpu_pwm_start_stop(tpd, false);

	/*
	 * - Clear TCNT on TGRB match
	 * - Count on rising edge
	 * - Set prescaler
	 * - Output 0 until TGRA, output 1 until TGRB (active low polarity)
	 * - Output 1 until TGRA, output 0 until TGRB (active high polarity
	 * - PWM mode
	 */
	tpu_pwm_write(tpd, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING |
		      tpd->prescaler);
	tpu_pwm_write(tpd, TPU_TMDRn, TPU_TMDR_MD_PWM);
	tpu_pwm_set_pin(tpd, TPU_PIN_PWM);
	tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
	tpu_pwm_write(tpd, TPU_TGRBn, tpd->period);

	dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
		tpd->channel, tpd->duty, tpd->period);

	/* Start the channel. */
	tpu_pwm_start_stop(tpd, true);

	return 0;
}

static void tpu_pwm_timer_stop(struct tpu_pwm_device *tpd)
{
	if (!tpd->timer_on)
		return;

	/* Disable channel. */
	tpu_pwm_start_stop(tpd, false);

	/* Stop clock and mark device as idle. */
	clk_disable_unprepare(tpd->tpu->clk);
	pm_runtime_put(&tpd->tpu->pdev->dev);

	tpd->timer_on = false;
}

/* -----------------------------------------------------------------------------
 * PWM API
 */

static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tpu_device *tpu = to_tpu_device(chip);
	struct tpu_pwm_device *tpd;

	if (pwm->hwpwm >= TPU_CHANNEL_MAX)
		return -EINVAL;

	tpd = kzalloc(sizeof(*tpd), GFP_KERNEL);
	if (tpd == NULL)
		return -ENOMEM;

	tpd->tpu = tpu;
	tpd->channel = pwm->hwpwm;
	tpd->polarity = PWM_POLARITY_NORMAL;
	tpd->prescaler = 0;
	tpd->period = 0;
	tpd->duty = 0;

	tpd->timer_on = false;

	pwm_set_chip_data(pwm, tpd);

	return 0;
}

static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);

	tpu_pwm_timer_stop(tpd);
	kfree(tpd);
}

static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			  u64 duty_ns, u64 period_ns, bool enabled)
{
	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
	struct tpu_device *tpu = to_tpu_device(chip);
	unsigned int prescaler;
	bool duty_only = false;
	u32 clk_rate;
	u64 period;
	u32 duty;
	int ret;

	clk_rate = clk_get_rate(tpu->clk);
	if (unlikely(clk_rate > NSEC_PER_SEC)) {
		/*
		 * This won't happen in the nearer future, so this is only a
		 * safeguard to prevent the following calculation from
		 * overflowing. With this clk_rate * period_ns / NSEC_PER_SEC is
		 * not greater than period_ns and so fits into an u64.
		 */
		return -EINVAL;
	}

	period = mul_u64_u64_div_u64(clk_rate, period_ns, NSEC_PER_SEC);

	/*
	 * Find the minimal prescaler in [0..3] such that
	 *
	 *     period >> (2 * prescaler) < 0x10000
	 *
	 * This could be calculated using something like:
	 *
	 *     prescaler = max(ilog2(period) / 2, 7) - 7;
	 *
	 * but given there are only four allowed results and that ilog2 isn't
	 * cheap on all platforms using a switch statement is more effective.
	 */
	switch (period) {
	case 1 ... 0xffff:
		prescaler = 0;
		break;

	case 0x10000 ... 0x3ffff:
		prescaler = 1;
		break;

	case 0x40000 ... 0xfffff:
		prescaler = 2;
		break;

	case 0x100000 ... 0x3fffff:
		prescaler = 3;
		break;

	default:
		return -EINVAL;
	}

	period >>= 2 * prescaler;

	if (duty_ns)
		duty = mul_u64_u64_div_u64(clk_rate, duty_ns,
					   (u64)NSEC_PER_SEC << (2 * prescaler));
	else
		duty = 0;

	dev_dbg(&tpu->pdev->dev,
		"rate %u, prescaler %u, period %u, duty %u\n",
		clk_rate, 1 << (2 * prescaler), (u32)period, duty);

	if (tpd->prescaler == prescaler && tpd->period == period)
		duty_only = true;

	tpd->prescaler = prescaler;
	tpd->period = period;
	tpd->duty = duty;

	/* If the channel is disabled we're done. */
	if (!enabled)
		return 0;

	if (duty_only && tpd->timer_on) {
		/*
		 * If only the duty cycle changed and the timer is already
		 * running, there's no need to reconfigure it completely, Just
		 * modify the duty cycle.
		 */
		tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
		dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel,
			tpd->duty);
	} else {
		/* Otherwise perform a full reconfiguration. */
		ret = tpu_pwm_timer_start(tpd);
		if (ret < 0)
			return ret;
	}

	if (duty == 0 || duty == period) {
		/*
		 * To avoid running the timer when not strictly required, handle
		 * 0% and 100% duty cycles as fixed levels and stop the timer.
		 */
		tpu_pwm_set_pin(tpd, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
		tpu_pwm_timer_stop(tpd);
	}

	return 0;
}

static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
				enum pwm_polarity polarity)
{
	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);

	tpd->polarity = polarity;

	return 0;
}

static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
	int ret;

	ret = tpu_pwm_timer_start(tpd);
	if (ret < 0)
		return ret;

	/*
	 * To avoid running the timer when not strictly required, handle 0% and
	 * 100% duty cycles as fixed levels and stop the timer.
	 */
	if (tpd->duty == 0 || tpd->duty == tpd->period) {
		tpu_pwm_set_pin(tpd, tpd->duty ?
				TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
		tpu_pwm_timer_stop(tpd);
	}

	return 0;
}

static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);

	/* The timer must be running to modify the pin output configuration. */
	tpu_pwm_timer_start(tpd);
	tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
	tpu_pwm_timer_stop(tpd);
}

static int tpu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			 const struct pwm_state *state)
{
	int err;
	bool enabled = pwm->state.enabled;

	if (state->polarity != pwm->state.polarity) {
		if (enabled) {
			tpu_pwm_disable(chip, pwm);
			enabled = false;
		}

		err = tpu_pwm_set_polarity(chip, pwm, state->polarity);
		if (err)
			return err;
	}

	if (!state->enabled) {
		if (enabled)
			tpu_pwm_disable(chip, pwm);

		return 0;
	}

	err = tpu_pwm_config(pwm->chip, pwm,
			     state->duty_cycle, state->period, enabled);
	if (err)
		return err;

	if (!enabled)
		err = tpu_pwm_enable(chip, pwm);

	return err;
}

static const struct pwm_ops tpu_pwm_ops = {
	.request = tpu_pwm_request,
	.free = tpu_pwm_free,
	.apply = tpu_pwm_apply,
	.owner = THIS_MODULE,
};

/* -----------------------------------------------------------------------------
 * Probe and remove
 */

static int tpu_probe(struct platform_device *pdev)
{
	struct tpu_device *tpu;
	int ret;

	tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
	if (tpu == NULL)
		return -ENOMEM;

	spin_lock_init(&tpu->lock);
	tpu->pdev = pdev;

	/* Map memory, get clock and pin control. */
	tpu->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(tpu->base))
		return PTR_ERR(tpu->base);

	tpu->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(tpu->clk))
		return dev_err_probe(&pdev->dev, PTR_ERR(tpu->clk), "Failed to get clock\n");

	/* Initialize and register the device. */
	platform_set_drvdata(pdev, tpu);

	tpu->chip.dev = &pdev->dev;
	tpu->chip.ops = &tpu_pwm_ops;
	tpu->chip.npwm = TPU_CHANNEL_MAX;

	ret = devm_pm_runtime_enable(&pdev->dev);
	if (ret < 0)
		return dev_err_probe(&pdev->dev, ret, "Failed to enable runtime PM\n");

	ret = devm_pwmchip_add(&pdev->dev, &tpu->chip);
	if (ret < 0)
		return dev_err_probe(&pdev->dev, ret, "Failed to register PWM chip\n");

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id tpu_of_table[] = {
	{ .compatible = "renesas,tpu-r8a73a4", },
	{ .compatible = "renesas,tpu-r8a7740", },
	{ .compatible = "renesas,tpu-r8a7790", },
	{ .compatible = "renesas,tpu", },
	{ },
};

MODULE_DEVICE_TABLE(of, tpu_of_table);
#endif

static struct platform_driver tpu_driver = {
	.probe		= tpu_probe,
	.driver		= {
		.name	= "renesas-tpu-pwm",
		.of_match_table = of_match_ptr(tpu_of_table),
	}
};

module_platform_driver(tpu_driver);

MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
MODULE_DESCRIPTION("Renesas TPU PWM Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:renesas-tpu-pwm");
Commit	Line	Data
e4ab5172	1	// SPDX-License-Identifier: GPL-2.0
99b82abb LP	2	/*
	3	* R-Mobile TPU PWM driver
	4	*
	5	* Copyright (C) 2012 Renesas Solutions Corp.
99b82abb LP	6	*/
	7
	8	#include <linux/clk.h>
	9	#include <linux/err.h>
	10	#include <linux/io.h>
	11	#include <linux/init.h>
	12	#include <linux/ioport.h>
	13	#include <linux/module.h>
	14	#include <linux/mutex.h>
382457e5	15	#include <linux/of.h>
99b82abb LP	16	#include <linux/platform_device.h>
	17	#include <linux/pm_runtime.h>
	18	#include <linux/pwm.h>
	19	#include <linux/slab.h>
	20	#include <linux/spinlock.h>
	21
dc671157 AB	22	#define TPU_CHANNEL_MAX 4
dc671157 AB	23
99b82abb LP	24	#define TPU_TSTR 0x00 /* Timer start register (shared) */
	25
	26	#define TPU_TCRn 0x00 /* Timer control register */
	27	#define TPU_TCR_CCLR_NONE (0 << 5)
	28	#define TPU_TCR_CCLR_TGRA (1 << 5)
	29	#define TPU_TCR_CCLR_TGRB (2 << 5)
	30	#define TPU_TCR_CCLR_TGRC (5 << 5)
	31	#define TPU_TCR_CCLR_TGRD (6 << 5)
	32	#define TPU_TCR_CKEG_RISING (0 << 3)
	33	#define TPU_TCR_CKEG_FALLING (1 << 3)
	34	#define TPU_TCR_CKEG_BOTH (2 << 3)
	35	#define TPU_TMDRn 0x04 /* Timer mode register */
	36	#define TPU_TMDR_BFWT (1 << 6)
	37	#define TPU_TMDR_BFB (1 << 5)
	38	#define TPU_TMDR_BFA (1 << 4)
	39	#define TPU_TMDR_MD_NORMAL (0 << 0)
	40	#define TPU_TMDR_MD_PWM (2 << 0)
	41	#define TPU_TIORn 0x08 /* Timer I/O control register */
	42	#define TPU_TIOR_IOA_0 (0 << 0)
	43	#define TPU_TIOR_IOA_0_CLR (1 << 0)
	44	#define TPU_TIOR_IOA_0_SET (2 << 0)
	45	#define TPU_TIOR_IOA_0_TOGGLE (3 << 0)
	46	#define TPU_TIOR_IOA_1 (4 << 0)
	47	#define TPU_TIOR_IOA_1_CLR (5 << 0)
	48	#define TPU_TIOR_IOA_1_SET (6 << 0)
	49	#define TPU_TIOR_IOA_1_TOGGLE (7 << 0)
	50	#define TPU_TIERn 0x0c /* Timer interrupt enable register */
	51	#define TPU_TSRn 0x10 /* Timer status register */
	52	#define TPU_TCNTn 0x14 /* Timer counter */
	53	#define TPU_TGRAn 0x18 /* Timer general register A */
	54	#define TPU_TGRBn 0x1c /* Timer general register B */
	55	#define TPU_TGRCn 0x20 /* Timer general register C */
	56	#define TPU_TGRDn 0x24 /* Timer general register D */
	57
	58	#define TPU_CHANNEL_OFFSET 0x10
	59	#define TPU_CHANNEL_SIZE 0x40
	60
	61	enum tpu_pin_state {
	62	TPU_PIN_INACTIVE, /* Pin is driven inactive */
	63	TPU_PIN_PWM, /* Pin is driven by PWM */
	64	TPU_PIN_ACTIVE, /* Pin is driven active */
	65	};
	66
	67	struct tpu_device;
	68
	69	struct tpu_pwm_device {
	70	bool timer_on; /* Whether the timer is running */
	71
	72	struct tpu_device *tpu;
	73	unsigned int channel; /* Channel number in the TPU */
	74
	75	enum pwm_polarity polarity;
	76	unsigned int prescaler;
	77	u16 period;
	78	u16 duty;
	79	};
	80
	81	struct tpu_device {
	82	struct platform_device *pdev;
99b82abb LP	83	struct pwm_chip chip;
	84	spinlock_t lock;
	85
	86	void __iomem *base;
	87	struct clk *clk;
	88	};
	89
	90	#define to_tpu_device(c) container_of(c, struct tpu_device, chip)
	91
208ab867	92	static void tpu_pwm_write(struct tpu_pwm_device *tpd, int reg_nr, u16 value)
99b82abb	93	{
208ab867 UKK	94	void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET
208ab867 UKK	95	+ tpd->channel * TPU_CHANNEL_SIZE;
99b82abb LP	96
	97	iowrite16(value, base + reg_nr);
	98	}
	99
208ab867	100	static void tpu_pwm_set_pin(struct tpu_pwm_device *tpd,
99b82abb LP	101	enum tpu_pin_state state)
	102	{
	103	static const char * const states[] = { "inactive", "PWM", "active" };
	104
208ab867 UKK	105	dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n",
208ab867 UKK	106	tpd->channel, states[state]);
99b82abb LP	107
	108	switch (state) {
	109	case TPU_PIN_INACTIVE:
208ab867 UKK	110	tpu_pwm_write(tpd, TPU_TIORn,
208ab867 UKK	111	tpd->polarity == PWM_POLARITY_INVERSED ?
99b82abb LP	112	TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0);
	113	break;
	114	case TPU_PIN_PWM:
208ab867 UKK	115	tpu_pwm_write(tpd, TPU_TIORn,
208ab867 UKK	116	tpd->polarity == PWM_POLARITY_INVERSED ?
99b82abb LP	117	TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR);
	118	break;
	119	case TPU_PIN_ACTIVE:
208ab867 UKK	120	tpu_pwm_write(tpd, TPU_TIORn,
208ab867 UKK	121	tpd->polarity == PWM_POLARITY_INVERSED ?
99b82abb LP	122	TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1);
	123	break;
	124	}
	125	}
	126
208ab867	127	static void tpu_pwm_start_stop(struct tpu_pwm_device *tpd, int start)
99b82abb LP	128	{
	129	unsigned long flags;
	130	u16 value;
	131
208ab867 UKK	132	spin_lock_irqsave(&tpd->tpu->lock, flags);
208ab867 UKK	133	value = ioread16(tpd->tpu->base + TPU_TSTR);
99b82abb LP	134
99b82abb LP	135	if (start)
208ab867	136	value \|= 1 << tpd->channel;
99b82abb	137	else
208ab867	138	value &= ~(1 << tpd->channel);
99b82abb	139
208ab867 UKK	140	iowrite16(value, tpd->tpu->base + TPU_TSTR);
208ab867 UKK	141	spin_unlock_irqrestore(&tpd->tpu->lock, flags);
99b82abb LP	142	}
99b82abb LP	143
208ab867	144	static int tpu_pwm_timer_start(struct tpu_pwm_device *tpd)
99b82abb LP	145	{
	146	int ret;
	147
208ab867	148	if (!tpd->timer_on) {
99b82abb	149	/* Wake up device and enable clock. */
208ab867 UKK	150	pm_runtime_get_sync(&tpd->tpu->pdev->dev);
208ab867 UKK	151	ret = clk_prepare_enable(tpd->tpu->clk);
99b82abb	152	if (ret) {
208ab867	153	dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n");
99b82abb LP	154	return ret;
99b82abb LP	155	}
208ab867	156	tpd->timer_on = true;
99b82abb LP	157	}
	158
	159	/*
	160	* Make sure the channel is stopped, as we need to reconfigure it
	161	* completely. First drive the pin to the inactive state to avoid
	162	* glitches.
	163	*/
208ab867 UKK	164	tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
208ab867 UKK	165	tpu_pwm_start_stop(tpd, false);
99b82abb LP	166
	167	/*
	168	* - Clear TCNT on TGRB match
	169	* - Count on rising edge
	170	* - Set prescaler
	171	* - Output 0 until TGRA, output 1 until TGRB (active low polarity)
	172	* - Output 1 until TGRA, output 0 until TGRB (active high polarity
	173	* - PWM mode
	174	*/
208ab867 UKK	175	tpu_pwm_write(tpd, TPU_TCRn, TPU_TCR_CCLR_TGRB \| TPU_TCR_CKEG_RISING \|
	176	tpd->prescaler);
	177	tpu_pwm_write(tpd, TPU_TMDRn, TPU_TMDR_MD_PWM);
	178	tpu_pwm_set_pin(tpd, TPU_PIN_PWM);
	179	tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
	180	tpu_pwm_write(tpd, TPU_TGRBn, tpd->period);
99b82abb	181
208ab867 UKK	182	dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
208ab867 UKK	183	tpd->channel, tpd->duty, tpd->period);
99b82abb LP	184
99b82abb LP	185	/* Start the channel. */
208ab867	186	tpu_pwm_start_stop(tpd, true);
99b82abb LP	187
	188	return 0;
	189	}
	190
208ab867	191	static void tpu_pwm_timer_stop(struct tpu_pwm_device *tpd)
99b82abb	192	{
208ab867	193	if (!tpd->timer_on)
99b82abb LP	194	return;
	195
	196	/* Disable channel. */
208ab867	197	tpu_pwm_start_stop(tpd, false);
99b82abb LP	198
99b82abb LP	199	/* Stop clock and mark device as idle. */
208ab867 UKK	200	clk_disable_unprepare(tpd->tpu->clk);
208ab867 UKK	201	pm_runtime_put(&tpd->tpu->pdev->dev);
99b82abb	202
208ab867	203	tpd->timer_on = false;
99b82abb LP	204	}
	205
	206	/* -----------------------------------------------------------------------------
	207	* PWM API
	208	*/
	209
208ab867	210	static int tpu_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
99b82abb LP	211	{
99b82abb LP	212	struct tpu_device *tpu = to_tpu_device(chip);
208ab867	213	struct tpu_pwm_device *tpd;
99b82abb	214
208ab867	215	if (pwm->hwpwm >= TPU_CHANNEL_MAX)
99b82abb LP	216	return -EINVAL;
99b82abb LP	217
208ab867 UKK	218	tpd = kzalloc(sizeof(*tpd), GFP_KERNEL);
208ab867 UKK	219	if (tpd == NULL)
99b82abb LP	220	return -ENOMEM;
99b82abb LP	221
208ab867 UKK	222	tpd->tpu = tpu;
	223	tpd->channel = pwm->hwpwm;
	224	tpd->polarity = PWM_POLARITY_NORMAL;
	225	tpd->prescaler = 0;
	226	tpd->period = 0;
	227	tpd->duty = 0;
99b82abb	228
208ab867	229	tpd->timer_on = false;
99b82abb	230
208ab867	231	pwm_set_chip_data(pwm, tpd);
99b82abb LP	232
	233	return 0;
	234	}
	235
208ab867	236	static void tpu_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
99b82abb	237	{
208ab867	238	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
99b82abb	239
208ab867 UKK	240	tpu_pwm_timer_stop(tpd);
208ab867 UKK	241	kfree(tpd);
99b82abb LP	242	}
99b82abb LP	243
208ab867	244	static int tpu_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
615f4e84	245	u64 duty_ns, u64 period_ns, bool enabled)
99b82abb	246	{
208ab867	247	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
99b82abb LP	248	struct tpu_device *tpu = to_tpu_device(chip);
	249	unsigned int prescaler;
	250	bool duty_only = false;
	251	u32 clk_rate;
615f4e84	252	u64 period;
99b82abb LP	253	u32 duty;
	254	int ret;
	255
3c173376	256	clk_rate = clk_get_rate(tpu->clk);
615f4e84 UKK	257	if (unlikely(clk_rate > NSEC_PER_SEC)) {
	258	/*
	259	* This won't happen in the nearer future, so this is only a
	260	* safeguard to prevent the following calculation from
	261	* overflowing. With this clk_rate * period_ns / NSEC_PER_SEC is
	262	* not greater than period_ns and so fits into an u64.
	263	*/
	264	return -EINVAL;
	265	}
3c173376	266
615f4e84	267	period = mul_u64_u64_div_u64(clk_rate, period_ns, NSEC_PER_SEC);
3c173376	268
99b82abb	269	/*
3c173376 UKK	270	* Find the minimal prescaler in [0..3] such that
	271	*
	272	* period >> (2 * prescaler) < 0x10000
	273	*
	274	* This could be calculated using something like:
	275	*
	276	* prescaler = max(ilog2(period) / 2, 7) - 7;
	277	*
	278	* but given there are only four allowed results and that ilog2 isn't
	279	* cheap on all platforms using a switch statement is more effective.
99b82abb	280	*/
3c173376 UKK	281	switch (period) {
	282	case 1 ... 0xffff:
	283	prescaler = 0;
	284	break;
99b82abb	285
3c173376 UKK	286	case 0x10000 ... 0x3ffff:
	287	prescaler = 1;
	288	break;
99b82abb	289
3c173376 UKK	290	case 0x40000 ... 0xfffff:
	291	prescaler = 2;
	292	break;
	293
	294	case 0x100000 ... 0x3fffff:
	295	prescaler = 3;
	296	break;
	297
	298	default:
	299	return -EINVAL;
99b82abb LP	300	}
99b82abb LP	301
3c173376 UKK	302	period >>= 2 * prescaler;
3c173376 UKK	303
615f4e84 UKK	304	if (duty_ns)
	305	duty = mul_u64_u64_div_u64(clk_rate, duty_ns,
	306	(u64)NSEC_PER_SEC << (2 * prescaler));
	307	else
99b82abb	308	duty = 0;
99b82abb LP	309
	310	dev_dbg(&tpu->pdev->dev,
	311	"rate %u, prescaler %u, period %u, duty %u\n",
615f4e84	312	clk_rate, 1 << (2 * prescaler), (u32)period, duty);
99b82abb	313
208ab867	314	if (tpd->prescaler == prescaler && tpd->period == period)
99b82abb LP	315	duty_only = true;
99b82abb LP	316
208ab867 UKK	317	tpd->prescaler = prescaler;
	318	tpd->period = period;
	319	tpd->duty = duty;
99b82abb LP	320
99b82abb LP	321	/* If the channel is disabled we're done. */
ec00cd5e	322	if (!enabled)
99b82abb LP	323	return 0;
99b82abb LP	324
208ab867	325	if (duty_only && tpd->timer_on) {
99b82abb LP	326	/*
	327	* If only the duty cycle changed and the timer is already
	328	* running, there's no need to reconfigure it completely, Just
	329	* modify the duty cycle.
	330	*/
208ab867 UKK	331	tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
	332	dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel,
	333	tpd->duty);
99b82abb LP	334	} else {
99b82abb LP	335	/* Otherwise perform a full reconfiguration. */
208ab867	336	ret = tpu_pwm_timer_start(tpd);
99b82abb LP	337	if (ret < 0)
	338	return ret;
	339	}
	340
	341	if (duty == 0 \|\| duty == period) {
	342	/*
	343	* To avoid running the timer when not strictly required, handle
	344	* 0% and 100% duty cycles as fixed levels and stop the timer.
	345	*/
208ab867 UKK	346	tpu_pwm_set_pin(tpd, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
208ab867 UKK	347	tpu_pwm_timer_stop(tpd);
99b82abb LP	348	}
	349
	350	return 0;
	351	}
	352
208ab867	353	static int tpu_pwm_set_polarity(struct pwm_chip chip, struct pwm_device pwm,
99b82abb LP	354	enum pwm_polarity polarity)
99b82abb LP	355	{
208ab867	356	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
99b82abb	357
208ab867	358	tpd->polarity = polarity;
99b82abb LP	359
	360	return 0;
	361	}
	362
208ab867	363	static int tpu_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
99b82abb	364	{
208ab867	365	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
99b82abb LP	366	int ret;
99b82abb LP	367
208ab867	368	ret = tpu_pwm_timer_start(tpd);
99b82abb LP	369	if (ret < 0)
	370	return ret;
	371
	372	/*
	373	* To avoid running the timer when not strictly required, handle 0% and
	374	* 100% duty cycles as fixed levels and stop the timer.
	375	*/
208ab867 UKK	376	if (tpd->duty == 0 \|\| tpd->duty == tpd->period) {
208ab867 UKK	377	tpu_pwm_set_pin(tpd, tpd->duty ?
99b82abb	378	TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
208ab867	379	tpu_pwm_timer_stop(tpd);
99b82abb LP	380	}
	381
	382	return 0;
	383	}
	384
208ab867	385	static void tpu_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
99b82abb	386	{
208ab867	387	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
99b82abb LP	388
99b82abb LP	389	/* The timer must be running to modify the pin output configuration. */
208ab867 UKK	390	tpu_pwm_timer_start(tpd);
	391	tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
	392	tpu_pwm_timer_stop(tpd);
99b82abb LP	393	}
99b82abb LP	394
ec00cd5e UKK	395	static int tpu_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	396	const struct pwm_state *state)
	397	{
	398	int err;
	399	bool enabled = pwm->state.enabled;
	400
	401	if (state->polarity != pwm->state.polarity) {
	402	if (enabled) {
	403	tpu_pwm_disable(chip, pwm);
	404	enabled = false;
	405	}
	406
	407	err = tpu_pwm_set_polarity(chip, pwm, state->polarity);
	408	if (err)
	409	return err;
	410	}
	411
	412	if (!state->enabled) {
	413	if (enabled)
	414	tpu_pwm_disable(chip, pwm);
	415
	416	return 0;
	417	}
	418
	419	err = tpu_pwm_config(pwm->chip, pwm,
	420	state->duty_cycle, state->period, enabled);
	421	if (err)
	422	return err;
	423
	424	if (!enabled)
	425	err = tpu_pwm_enable(chip, pwm);
	426
	427	return err;
	428	}
	429
99b82abb LP	430	static const struct pwm_ops tpu_pwm_ops = {
	431	.request = tpu_pwm_request,
	432	.free = tpu_pwm_free,
ec00cd5e	433	.apply = tpu_pwm_apply,
99b82abb LP	434	.owner = THIS_MODULE,
	435	};
	436
	437	/* -----------------------------------------------------------------------------
	438	* Probe and remove
	439	*/
	440
	441	static int tpu_probe(struct platform_device *pdev)
	442	{
	443	struct tpu_device *tpu;
99b82abb LP	444	int ret;
	445
	446	tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
6c5059cc	447	if (tpu == NULL)
99b82abb	448	return -ENOMEM;
99b82abb	449
382457e5 LP	450	spin_lock_init(&tpu->lock);
	451	tpu->pdev = pdev;
	452
99b82abb	453	/* Map memory, get clock and pin control. */
e3f22bc2	454	tpu->base = devm_platform_ioremap_resource(pdev, 0);
00cf99ee WY	455	if (IS_ERR(tpu->base))
00cf99ee WY	456	return PTR_ERR(tpu->base);
99b82abb LP	457
99b82abb LP	458	tpu->clk = devm_clk_get(&pdev->dev, NULL);
6eb3af76 UKK	459	if (IS_ERR(tpu->clk))
6eb3af76 UKK	460	return dev_err_probe(&pdev->dev, PTR_ERR(tpu->clk), "Failed to get clock\n");
99b82abb LP	461
	462	/* Initialize and register the device. */
	463	platform_set_drvdata(pdev, tpu);
	464
99b82abb LP	465	tpu->chip.dev = &pdev->dev;
99b82abb LP	466	tpu->chip.ops = &tpu_pwm_ops;
99b82abb LP	467	tpu->chip.npwm = TPU_CHANNEL_MAX;
99b82abb LP	468
ff4bcd56 UKK	469	ret = devm_pm_runtime_enable(&pdev->dev);
	470	if (ret < 0)
	471	return dev_err_probe(&pdev->dev, ret, "Failed to enable runtime PM\n");
d5a3c7a4	472
ff4bcd56 UKK	473	ret = devm_pwmchip_add(&pdev->dev, &tpu->chip);
ff4bcd56 UKK	474	if (ret < 0)
6eb3af76	475	return dev_err_probe(&pdev->dev, ret, "Failed to register PWM chip\n");
99b82abb	476
81d4b5c4	477	return 0;
99b82abb LP	478	}
99b82abb LP	479
382457e5 LP	480	#ifdef CONFIG_OF
	481	static const struct of_device_id tpu_of_table[] = {
	482	{ .compatible = "renesas,tpu-r8a73a4", },
	483	{ .compatible = "renesas,tpu-r8a7740", },
	484	{ .compatible = "renesas,tpu-r8a7790", },
382457e5 LP	485	{ .compatible = "renesas,tpu", },
	486	{ },
	487	};
	488
	489	MODULE_DEVICE_TABLE(of, tpu_of_table);
	490	#endif
	491
99b82abb LP	492	static struct platform_driver tpu_driver = {
99b82abb LP	493	.probe = tpu_probe,
99b82abb LP	494	.driver = {
99b82abb LP	495	.name = "renesas-tpu-pwm",
382457e5	496	.of_match_table = of_match_ptr(tpu_of_table),
99b82abb LP	497	}
	498	};
	499
	500	module_platform_driver(tpu_driver);
	501
	502	MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
	503	MODULE_DESCRIPTION("Renesas TPU PWM Driver");
	504	MODULE_LICENSE("GPL v2");
71077bc8	505	MODULE_ALIAS("platform:renesas-tpu-pwm");