[linux-block.git] / drivers / pwm / pwm-renesas-tpu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * R-Mobile TPU PWM driver
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/pwm.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#define TPU_CHANNEL_MAX		4

#define TPU_TSTR		0x00	/* Timer start register (shared) */

#define TPU_TCRn		0x00	/* Timer control register */
#define TPU_TCR_CCLR_NONE	(0 << 5)
#define TPU_TCR_CCLR_TGRA	(1 << 5)
#define TPU_TCR_CCLR_TGRB	(2 << 5)
#define TPU_TCR_CCLR_TGRC	(5 << 5)
#define TPU_TCR_CCLR_TGRD	(6 << 5)
#define TPU_TCR_CKEG_RISING	(0 << 3)
#define TPU_TCR_CKEG_FALLING	(1 << 3)
#define TPU_TCR_CKEG_BOTH	(2 << 3)
#define TPU_TMDRn		0x04	/* Timer mode register */
#define TPU_TMDR_BFWT		(1 << 6)
#define TPU_TMDR_BFB		(1 << 5)
#define TPU_TMDR_BFA		(1 << 4)
#define TPU_TMDR_MD_NORMAL	(0 << 0)
#define TPU_TMDR_MD_PWM		(2 << 0)
#define TPU_TIORn		0x08	/* Timer I/O control register */
#define TPU_TIOR_IOA_0		(0 << 0)
#define TPU_TIOR_IOA_0_CLR	(1 << 0)
#define TPU_TIOR_IOA_0_SET	(2 << 0)
#define TPU_TIOR_IOA_0_TOGGLE	(3 << 0)
#define TPU_TIOR_IOA_1		(4 << 0)
#define TPU_TIOR_IOA_1_CLR	(5 << 0)
#define TPU_TIOR_IOA_1_SET	(6 << 0)
#define TPU_TIOR_IOA_1_TOGGLE	(7 << 0)
#define TPU_TIERn		0x0c	/* Timer interrupt enable register */
#define TPU_TSRn		0x10	/* Timer status register */
#define TPU_TCNTn		0x14	/* Timer counter */
#define TPU_TGRAn		0x18	/* Timer general register A */
#define TPU_TGRBn		0x1c	/* Timer general register B */
#define TPU_TGRCn		0x20	/* Timer general register C */
#define TPU_TGRDn		0x24	/* Timer general register D */

#define TPU_CHANNEL_OFFSET	0x10
#define TPU_CHANNEL_SIZE	0x40

enum tpu_pin_state {
	TPU_PIN_INACTIVE,		/* Pin is driven inactive */
	TPU_PIN_PWM,			/* Pin is driven by PWM */
	TPU_PIN_ACTIVE,			/* Pin is driven active */
};

struct tpu_device;

struct tpu_pwm_device {
	bool timer_on;			/* Whether the timer is running */

	struct tpu_device *tpu;
	unsigned int channel;		/* Channel number in the TPU */

	enum pwm_polarity polarity;
	unsigned int prescaler;
	u16 period;
	u16 duty;
};

struct tpu_device {
	struct platform_device *pdev;
	struct pwm_chip chip;
	spinlock_t lock;

	void __iomem *base;
	struct clk *clk;
};

#define to_tpu_device(c)	container_of(c, struct tpu_device, chip)

static void tpu_pwm_write(struct tpu_pwm_device *tpd, int reg_nr, u16 value)
{
	void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET
			   + tpd->channel * TPU_CHANNEL_SIZE;

	iowrite16(value, base + reg_nr);
}

static void tpu_pwm_set_pin(struct tpu_pwm_device *tpd,
			    enum tpu_pin_state state)
{
	static const char * const states[] = { "inactive", "PWM", "active" };

	dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n",
		tpd->channel, states[state]);

	switch (state) {
	case TPU_PIN_INACTIVE:
		tpu_pwm_write(tpd, TPU_TIORn,
			      tpd->polarity == PWM_POLARITY_INVERSED ?
			      TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0);
		break;
	case TPU_PIN_PWM:
		tpu_pwm_write(tpd, TPU_TIORn,
			      tpd->polarity == PWM_POLARITY_INVERSED ?
			      TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR);
		break;
	case TPU_PIN_ACTIVE:
		tpu_pwm_write(tpd, TPU_TIORn,
			      tpd->polarity == PWM_POLARITY_INVERSED ?
			      TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1);
		break;
	}
}

static void tpu_pwm_start_stop(struct tpu_pwm_device *tpd, int start)
{
	unsigned long flags;
	u16 value;

	spin_lock_irqsave(&tpd->tpu->lock, flags);
	value = ioread16(tpd->tpu->base + TPU_TSTR);

	if (start)
		value |= 1 << tpd->channel;
	else
		value &= ~(1 << tpd->channel);

	iowrite16(value, tpd->tpu->base + TPU_TSTR);
	spin_unlock_irqrestore(&tpd->tpu->lock, flags);
}

static int tpu_pwm_timer_start(struct tpu_pwm_device *tpd)
{
	int ret;

	if (!tpd->timer_on) {
		/* Wake up device and enable clock. */
		pm_runtime_get_sync(&tpd->tpu->pdev->dev);
		ret = clk_prepare_enable(tpd->tpu->clk);
		if (ret) {
			dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n");
			return ret;
		}
		tpd->timer_on = true;
	}

	/*
	 * Make sure the channel is stopped, as we need to reconfigure it
	 * completely. First drive the pin to the inactive state to avoid
	 * glitches.
	 */
	tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
	tpu_pwm_start_stop(tpd, false);

	/*
	 * - Clear TCNT on TGRB match
	 * - Count on rising edge
	 * - Set prescaler
	 * - Output 0 until TGRA, output 1 until TGRB (active low polarity)
	 * - Output 1 until TGRA, output 0 until TGRB (active high polarity
	 * - PWM mode
	 */
	tpu_pwm_write(tpd, TPU_TCRn, TPU_TCR_CCLR_TGRB | TPU_TCR_CKEG_RISING |
		      tpd->prescaler);
	tpu_pwm_write(tpd, TPU_TMDRn, TPU_TMDR_MD_PWM);
	tpu_pwm_set_pin(tpd, TPU_PIN_PWM);
	tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
	tpu_pwm_write(tpd, TPU_TGRBn, tpd->period);

	dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
		tpd->channel, tpd->duty, tpd->period);

	/* Start the channel. */
	tpu_pwm_start_stop(tpd, true);

	return 0;
}

static void tpu_pwm_timer_stop(struct tpu_pwm_device *tpd)
{
	if (!tpd->timer_on)
		return;

	/* Disable channel. */
	tpu_pwm_start_stop(tpd, false);

	/* Stop clock and mark device as idle. */
	clk_disable_unprepare(tpd->tpu->clk);
	pm_runtime_put(&tpd->tpu->pdev->dev);

	tpd->timer_on = false;
}

/* -----------------------------------------------------------------------------
 * PWM API
 */

static int tpu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tpu_device *tpu = to_tpu_device(chip);
	struct tpu_pwm_device *tpd;

	if (pwm->hwpwm >= TPU_CHANNEL_MAX)
		return -EINVAL;

	tpd = kzalloc(sizeof(*tpd), GFP_KERNEL);
	if (tpd == NULL)
		return -ENOMEM;

	tpd->tpu = tpu;
	tpd->channel = pwm->hwpwm;
	tpd->polarity = PWM_POLARITY_NORMAL;
	tpd->prescaler = 0;
	tpd->period = 0;
	tpd->duty = 0;

	tpd->timer_on = false;

	pwm_set_chip_data(pwm, tpd);

	return 0;
}

static void tpu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);

	tpu_pwm_timer_stop(tpd);
	kfree(tpd);
}

static int tpu_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			  int duty_ns, int period_ns, bool enabled)
{
	static const unsigned int prescalers[] = { 1, 4, 16, 64 };
	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
	struct tpu_device *tpu = to_tpu_device(chip);
	unsigned int prescaler;
	bool duty_only = false;
	u32 clk_rate;
	u32 period;
	u32 duty;
	int ret;

	/*
	 * Pick a prescaler to avoid overflowing the counter.
	 * TODO: Pick the highest acceptable prescaler.
	 */
	clk_rate = clk_get_rate(tpu->clk);

	for (prescaler = 0; prescaler < ARRAY_SIZE(prescalers); ++prescaler) {
		period = clk_rate / prescalers[prescaler]
		       / (NSEC_PER_SEC / period_ns);
		if (period <= 0xffff)
			break;
	}

	if (prescaler == ARRAY_SIZE(prescalers) || period == 0) {
		dev_err(&tpu->pdev->dev, "clock rate mismatch\n");
		return -ENOTSUPP;
	}

	if (duty_ns) {
		duty = clk_rate / prescalers[prescaler]
		     / (NSEC_PER_SEC / duty_ns);
		if (duty > period)
			return -EINVAL;
	} else {
		duty = 0;
	}

	dev_dbg(&tpu->pdev->dev,
		"rate %u, prescaler %u, period %u, duty %u\n",
		clk_rate, prescalers[prescaler], period, duty);

	if (tpd->prescaler == prescaler && tpd->period == period)
		duty_only = true;

	tpd->prescaler = prescaler;
	tpd->period = period;
	tpd->duty = duty;

	/* If the channel is disabled we're done. */
	if (!enabled)
		return 0;

	if (duty_only && tpd->timer_on) {
		/*
		 * If only the duty cycle changed and the timer is already
		 * running, there's no need to reconfigure it completely, Just
		 * modify the duty cycle.
		 */
		tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
		dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel,
			tpd->duty);
	} else {
		/* Otherwise perform a full reconfiguration. */
		ret = tpu_pwm_timer_start(tpd);
		if (ret < 0)
			return ret;
	}

	if (duty == 0 || duty == period) {
		/*
		 * To avoid running the timer when not strictly required, handle
		 * 0% and 100% duty cycles as fixed levels and stop the timer.
		 */
		tpu_pwm_set_pin(tpd, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
		tpu_pwm_timer_stop(tpd);
	}

	return 0;
}

static int tpu_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
				enum pwm_polarity polarity)
{
	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);

	tpd->polarity = polarity;

	return 0;
}

static int tpu_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
	int ret;

	ret = tpu_pwm_timer_start(tpd);
	if (ret < 0)
		return ret;

	/*
	 * To avoid running the timer when not strictly required, handle 0% and
	 * 100% duty cycles as fixed levels and stop the timer.
	 */
	if (tpd->duty == 0 || tpd->duty == tpd->period) {
		tpu_pwm_set_pin(tpd, tpd->duty ?
				TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
		tpu_pwm_timer_stop(tpd);
	}

	return 0;
}

static void tpu_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);

	/* The timer must be running to modify the pin output configuration. */
	tpu_pwm_timer_start(tpd);
	tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
	tpu_pwm_timer_stop(tpd);
}

static int tpu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			 const struct pwm_state *state)
{
	int err;
	bool enabled = pwm->state.enabled;

	if (state->polarity != pwm->state.polarity) {
		if (enabled) {
			tpu_pwm_disable(chip, pwm);
			enabled = false;
		}

		err = tpu_pwm_set_polarity(chip, pwm, state->polarity);
		if (err)
			return err;
	}

	if (!state->enabled) {
		if (enabled)
			tpu_pwm_disable(chip, pwm);

		return 0;
	}

	err = tpu_pwm_config(pwm->chip, pwm,
			     state->duty_cycle, state->period, enabled);
	if (err)
		return err;

	if (!enabled)
		err = tpu_pwm_enable(chip, pwm);

	return err;
}

static const struct pwm_ops tpu_pwm_ops = {
	.request = tpu_pwm_request,
	.free = tpu_pwm_free,
	.apply = tpu_pwm_apply,
	.owner = THIS_MODULE,
};

/* -----------------------------------------------------------------------------
 * Probe and remove
 */

static int tpu_probe(struct platform_device *pdev)
{
	struct tpu_device *tpu;
	int ret;

	tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
	if (tpu == NULL)
		return -ENOMEM;

	spin_lock_init(&tpu->lock);
	tpu->pdev = pdev;

	/* Map memory, get clock and pin control. */
	tpu->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(tpu->base))
		return PTR_ERR(tpu->base);

	tpu->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(tpu->clk))
		return dev_err_probe(&pdev->dev, PTR_ERR(tpu->clk), "Failed to get clock\n");

	/* Initialize and register the device. */
	platform_set_drvdata(pdev, tpu);

	tpu->chip.dev = &pdev->dev;
	tpu->chip.ops = &tpu_pwm_ops;
	tpu->chip.npwm = TPU_CHANNEL_MAX;

	ret = devm_pm_runtime_enable(&pdev->dev);
	if (ret < 0)
		return dev_err_probe(&pdev->dev, ret, "Failed to enable runtime PM\n");

	ret = devm_pwmchip_add(&pdev->dev, &tpu->chip);
	if (ret < 0)
		return dev_err_probe(&pdev->dev, ret, "Failed to register PWM chip\n");

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id tpu_of_table[] = {
	{ .compatible = "renesas,tpu-r8a73a4", },
	{ .compatible = "renesas,tpu-r8a7740", },
	{ .compatible = "renesas,tpu-r8a7790", },
	{ .compatible = "renesas,tpu", },
	{ },
};

MODULE_DEVICE_TABLE(of, tpu_of_table);
#endif

static struct platform_driver tpu_driver = {
	.probe		= tpu_probe,
	.driver		= {
		.name	= "renesas-tpu-pwm",
		.of_match_table = of_match_ptr(tpu_of_table),
	}
};

module_platform_driver(tpu_driver);

MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
MODULE_DESCRIPTION("Renesas TPU PWM Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:renesas-tpu-pwm");
Commit	Line	Data
e4ab5172	1	// SPDX-License-Identifier: GPL-2.0
99b82abb LP	2	/*
	3	* R-Mobile TPU PWM driver
	4	*
	5	* Copyright (C) 2012 Renesas Solutions Corp.
99b82abb LP	6	*/
	7
	8	#include <linux/clk.h>
	9	#include <linux/err.h>
	10	#include <linux/io.h>
	11	#include <linux/init.h>
	12	#include <linux/ioport.h>
	13	#include <linux/module.h>
	14	#include <linux/mutex.h>
382457e5	15	#include <linux/of.h>
99b82abb LP	16	#include <linux/platform_device.h>
	17	#include <linux/pm_runtime.h>
	18	#include <linux/pwm.h>
	19	#include <linux/slab.h>
	20	#include <linux/spinlock.h>
	21
dc671157 AB	22	#define TPU_CHANNEL_MAX 4
dc671157 AB	23
99b82abb LP	24	#define TPU_TSTR 0x00 /* Timer start register (shared) */
	25
	26	#define TPU_TCRn 0x00 /* Timer control register */
	27	#define TPU_TCR_CCLR_NONE (0 << 5)
	28	#define TPU_TCR_CCLR_TGRA (1 << 5)
	29	#define TPU_TCR_CCLR_TGRB (2 << 5)
	30	#define TPU_TCR_CCLR_TGRC (5 << 5)
	31	#define TPU_TCR_CCLR_TGRD (6 << 5)
	32	#define TPU_TCR_CKEG_RISING (0 << 3)
	33	#define TPU_TCR_CKEG_FALLING (1 << 3)
	34	#define TPU_TCR_CKEG_BOTH (2 << 3)
	35	#define TPU_TMDRn 0x04 /* Timer mode register */
	36	#define TPU_TMDR_BFWT (1 << 6)
	37	#define TPU_TMDR_BFB (1 << 5)
	38	#define TPU_TMDR_BFA (1 << 4)
	39	#define TPU_TMDR_MD_NORMAL (0 << 0)
	40	#define TPU_TMDR_MD_PWM (2 << 0)
	41	#define TPU_TIORn 0x08 /* Timer I/O control register */
	42	#define TPU_TIOR_IOA_0 (0 << 0)
	43	#define TPU_TIOR_IOA_0_CLR (1 << 0)
	44	#define TPU_TIOR_IOA_0_SET (2 << 0)
	45	#define TPU_TIOR_IOA_0_TOGGLE (3 << 0)
	46	#define TPU_TIOR_IOA_1 (4 << 0)
	47	#define TPU_TIOR_IOA_1_CLR (5 << 0)
	48	#define TPU_TIOR_IOA_1_SET (6 << 0)
	49	#define TPU_TIOR_IOA_1_TOGGLE (7 << 0)
	50	#define TPU_TIERn 0x0c /* Timer interrupt enable register */
	51	#define TPU_TSRn 0x10 /* Timer status register */
	52	#define TPU_TCNTn 0x14 /* Timer counter */
	53	#define TPU_TGRAn 0x18 /* Timer general register A */
	54	#define TPU_TGRBn 0x1c /* Timer general register B */
	55	#define TPU_TGRCn 0x20 /* Timer general register C */
	56	#define TPU_TGRDn 0x24 /* Timer general register D */
	57
	58	#define TPU_CHANNEL_OFFSET 0x10
	59	#define TPU_CHANNEL_SIZE 0x40
	60
	61	enum tpu_pin_state {
	62	TPU_PIN_INACTIVE, /* Pin is driven inactive */
	63	TPU_PIN_PWM, /* Pin is driven by PWM */
	64	TPU_PIN_ACTIVE, /* Pin is driven active */
	65	};
	66
	67	struct tpu_device;
	68
	69	struct tpu_pwm_device {
	70	bool timer_on; /* Whether the timer is running */
	71
	72	struct tpu_device *tpu;
	73	unsigned int channel; /* Channel number in the TPU */
	74
	75	enum pwm_polarity polarity;
	76	unsigned int prescaler;
	77	u16 period;
	78	u16 duty;
	79	};
	80
	81	struct tpu_device {
	82	struct platform_device *pdev;
99b82abb LP	83	struct pwm_chip chip;
	84	spinlock_t lock;
	85
	86	void __iomem *base;
	87	struct clk *clk;
	88	};
	89
	90	#define to_tpu_device(c) container_of(c, struct tpu_device, chip)
	91
208ab867	92	static void tpu_pwm_write(struct tpu_pwm_device *tpd, int reg_nr, u16 value)
99b82abb	93	{
208ab867 UKK	94	void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET
208ab867 UKK	95	+ tpd->channel * TPU_CHANNEL_SIZE;
99b82abb LP	96
	97	iowrite16(value, base + reg_nr);
	98	}
	99
208ab867	100	static void tpu_pwm_set_pin(struct tpu_pwm_device *tpd,
99b82abb LP	101	enum tpu_pin_state state)
	102	{
	103	static const char * const states[] = { "inactive", "PWM", "active" };
	104
208ab867 UKK	105	dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n",
208ab867 UKK	106	tpd->channel, states[state]);
99b82abb LP	107
	108	switch (state) {
	109	case TPU_PIN_INACTIVE:
208ab867 UKK	110	tpu_pwm_write(tpd, TPU_TIORn,
208ab867 UKK	111	tpd->polarity == PWM_POLARITY_INVERSED ?
99b82abb LP	112	TPU_TIOR_IOA_1 : TPU_TIOR_IOA_0);
	113	break;
	114	case TPU_PIN_PWM:
208ab867 UKK	115	tpu_pwm_write(tpd, TPU_TIORn,
208ab867 UKK	116	tpd->polarity == PWM_POLARITY_INVERSED ?
99b82abb LP	117	TPU_TIOR_IOA_0_SET : TPU_TIOR_IOA_1_CLR);
	118	break;
	119	case TPU_PIN_ACTIVE:
208ab867 UKK	120	tpu_pwm_write(tpd, TPU_TIORn,
208ab867 UKK	121	tpd->polarity == PWM_POLARITY_INVERSED ?
99b82abb LP	122	TPU_TIOR_IOA_0 : TPU_TIOR_IOA_1);
	123	break;
	124	}
	125	}
	126
208ab867	127	static void tpu_pwm_start_stop(struct tpu_pwm_device *tpd, int start)
99b82abb LP	128	{
	129	unsigned long flags;
	130	u16 value;
	131
208ab867 UKK	132	spin_lock_irqsave(&tpd->tpu->lock, flags);
208ab867 UKK	133	value = ioread16(tpd->tpu->base + TPU_TSTR);
99b82abb LP	134
99b82abb LP	135	if (start)
208ab867	136	value \|= 1 << tpd->channel;
99b82abb	137	else
208ab867	138	value &= ~(1 << tpd->channel);
99b82abb	139
208ab867 UKK	140	iowrite16(value, tpd->tpu->base + TPU_TSTR);
208ab867 UKK	141	spin_unlock_irqrestore(&tpd->tpu->lock, flags);
99b82abb LP	142	}
99b82abb LP	143
208ab867	144	static int tpu_pwm_timer_start(struct tpu_pwm_device *tpd)
99b82abb LP	145	{
	146	int ret;
	147
208ab867	148	if (!tpd->timer_on) {
99b82abb	149	/* Wake up device and enable clock. */
208ab867 UKK	150	pm_runtime_get_sync(&tpd->tpu->pdev->dev);
208ab867 UKK	151	ret = clk_prepare_enable(tpd->tpu->clk);
99b82abb	152	if (ret) {
208ab867	153	dev_err(&tpd->tpu->pdev->dev, "cannot enable clock\n");
99b82abb LP	154	return ret;
99b82abb LP	155	}
208ab867	156	tpd->timer_on = true;
99b82abb LP	157	}
	158
	159	/*
	160	* Make sure the channel is stopped, as we need to reconfigure it
	161	* completely. First drive the pin to the inactive state to avoid
	162	* glitches.
	163	*/
208ab867 UKK	164	tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
208ab867 UKK	165	tpu_pwm_start_stop(tpd, false);
99b82abb LP	166
	167	/*
	168	* - Clear TCNT on TGRB match
	169	* - Count on rising edge
	170	* - Set prescaler
	171	* - Output 0 until TGRA, output 1 until TGRB (active low polarity)
	172	* - Output 1 until TGRA, output 0 until TGRB (active high polarity
	173	* - PWM mode
	174	*/
208ab867 UKK	175	tpu_pwm_write(tpd, TPU_TCRn, TPU_TCR_CCLR_TGRB \| TPU_TCR_CKEG_RISING \|
	176	tpd->prescaler);
	177	tpu_pwm_write(tpd, TPU_TMDRn, TPU_TMDR_MD_PWM);
	178	tpu_pwm_set_pin(tpd, TPU_PIN_PWM);
	179	tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
	180	tpu_pwm_write(tpd, TPU_TGRBn, tpd->period);
99b82abb	181
208ab867 UKK	182	dev_dbg(&tpd->tpu->pdev->dev, "%u: TGRA 0x%04x TGRB 0x%04x\n",
208ab867 UKK	183	tpd->channel, tpd->duty, tpd->period);
99b82abb LP	184
99b82abb LP	185	/* Start the channel. */
208ab867	186	tpu_pwm_start_stop(tpd, true);
99b82abb LP	187
	188	return 0;
	189	}
	190
208ab867	191	static void tpu_pwm_timer_stop(struct tpu_pwm_device *tpd)
99b82abb	192	{
208ab867	193	if (!tpd->timer_on)
99b82abb LP	194	return;
	195
	196	/* Disable channel. */
208ab867	197	tpu_pwm_start_stop(tpd, false);
99b82abb LP	198
99b82abb LP	199	/* Stop clock and mark device as idle. */
208ab867 UKK	200	clk_disable_unprepare(tpd->tpu->clk);
208ab867 UKK	201	pm_runtime_put(&tpd->tpu->pdev->dev);
99b82abb	202
208ab867	203	tpd->timer_on = false;
99b82abb LP	204	}
	205
	206	/* -----------------------------------------------------------------------------
	207	* PWM API
	208	*/
	209
208ab867	210	static int tpu_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
99b82abb LP	211	{
99b82abb LP	212	struct tpu_device *tpu = to_tpu_device(chip);
208ab867	213	struct tpu_pwm_device *tpd;
99b82abb	214
208ab867	215	if (pwm->hwpwm >= TPU_CHANNEL_MAX)
99b82abb LP	216	return -EINVAL;
99b82abb LP	217
208ab867 UKK	218	tpd = kzalloc(sizeof(*tpd), GFP_KERNEL);
208ab867 UKK	219	if (tpd == NULL)
99b82abb LP	220	return -ENOMEM;
99b82abb LP	221
208ab867 UKK	222	tpd->tpu = tpu;
	223	tpd->channel = pwm->hwpwm;
	224	tpd->polarity = PWM_POLARITY_NORMAL;
	225	tpd->prescaler = 0;
	226	tpd->period = 0;
	227	tpd->duty = 0;
99b82abb	228
208ab867	229	tpd->timer_on = false;
99b82abb	230
208ab867	231	pwm_set_chip_data(pwm, tpd);
99b82abb LP	232
	233	return 0;
	234	}
	235
208ab867	236	static void tpu_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
99b82abb	237	{
208ab867	238	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
99b82abb	239
208ab867 UKK	240	tpu_pwm_timer_stop(tpd);
208ab867 UKK	241	kfree(tpd);
99b82abb LP	242	}
99b82abb LP	243
208ab867	244	static int tpu_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
ec00cd5e	245	int duty_ns, int period_ns, bool enabled)
99b82abb LP	246	{
99b82abb LP	247	static const unsigned int prescalers[] = { 1, 4, 16, 64 };
208ab867	248	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
99b82abb LP	249	struct tpu_device *tpu = to_tpu_device(chip);
	250	unsigned int prescaler;
	251	bool duty_only = false;
	252	u32 clk_rate;
	253	u32 period;
	254	u32 duty;
	255	int ret;
	256
	257	/*
	258	* Pick a prescaler to avoid overflowing the counter.
	259	* TODO: Pick the highest acceptable prescaler.
	260	*/
	261	clk_rate = clk_get_rate(tpu->clk);
	262
	263	for (prescaler = 0; prescaler < ARRAY_SIZE(prescalers); ++prescaler) {
	264	period = clk_rate / prescalers[prescaler]
	265	/ (NSEC_PER_SEC / period_ns);
	266	if (period <= 0xffff)
	267	break;
	268	}
	269
	270	if (prescaler == ARRAY_SIZE(prescalers) \|\| period == 0) {
	271	dev_err(&tpu->pdev->dev, "clock rate mismatch\n");
	272	return -ENOTSUPP;
	273	}
	274
	275	if (duty_ns) {
	276	duty = clk_rate / prescalers[prescaler]
	277	/ (NSEC_PER_SEC / duty_ns);
	278	if (duty > period)
	279	return -EINVAL;
	280	} else {
	281	duty = 0;
	282	}
	283
	284	dev_dbg(&tpu->pdev->dev,
	285	"rate %u, prescaler %u, period %u, duty %u\n",
	286	clk_rate, prescalers[prescaler], period, duty);
	287
208ab867	288	if (tpd->prescaler == prescaler && tpd->period == period)
99b82abb LP	289	duty_only = true;
99b82abb LP	290
208ab867 UKK	291	tpd->prescaler = prescaler;
	292	tpd->period = period;
	293	tpd->duty = duty;
99b82abb LP	294
99b82abb LP	295	/* If the channel is disabled we're done. */
ec00cd5e	296	if (!enabled)
99b82abb LP	297	return 0;
99b82abb LP	298
208ab867	299	if (duty_only && tpd->timer_on) {
99b82abb LP	300	/*
	301	* If only the duty cycle changed and the timer is already
	302	* running, there's no need to reconfigure it completely, Just
	303	* modify the duty cycle.
	304	*/
208ab867 UKK	305	tpu_pwm_write(tpd, TPU_TGRAn, tpd->duty);
	306	dev_dbg(&tpu->pdev->dev, "%u: TGRA 0x%04x\n", tpd->channel,
	307	tpd->duty);
99b82abb LP	308	} else {
99b82abb LP	309	/* Otherwise perform a full reconfiguration. */
208ab867	310	ret = tpu_pwm_timer_start(tpd);
99b82abb LP	311	if (ret < 0)
	312	return ret;
	313	}
	314
	315	if (duty == 0 \|\| duty == period) {
	316	/*
	317	* To avoid running the timer when not strictly required, handle
	318	* 0% and 100% duty cycles as fixed levels and stop the timer.
	319	*/
208ab867 UKK	320	tpu_pwm_set_pin(tpd, duty ? TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
208ab867 UKK	321	tpu_pwm_timer_stop(tpd);
99b82abb LP	322	}
	323
	324	return 0;
	325	}
	326
208ab867	327	static int tpu_pwm_set_polarity(struct pwm_chip chip, struct pwm_device pwm,
99b82abb LP	328	enum pwm_polarity polarity)
99b82abb LP	329	{
208ab867	330	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
99b82abb	331
208ab867	332	tpd->polarity = polarity;
99b82abb LP	333
	334	return 0;
	335	}
	336
208ab867	337	static int tpu_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
99b82abb	338	{
208ab867	339	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
99b82abb LP	340	int ret;
99b82abb LP	341
208ab867	342	ret = tpu_pwm_timer_start(tpd);
99b82abb LP	343	if (ret < 0)
	344	return ret;
	345
	346	/*
	347	* To avoid running the timer when not strictly required, handle 0% and
	348	* 100% duty cycles as fixed levels and stop the timer.
	349	*/
208ab867 UKK	350	if (tpd->duty == 0 \|\| tpd->duty == tpd->period) {
208ab867 UKK	351	tpu_pwm_set_pin(tpd, tpd->duty ?
99b82abb	352	TPU_PIN_ACTIVE : TPU_PIN_INACTIVE);
208ab867	353	tpu_pwm_timer_stop(tpd);
99b82abb LP	354	}
	355
	356	return 0;
	357	}
	358
208ab867	359	static void tpu_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
99b82abb	360	{
208ab867	361	struct tpu_pwm_device *tpd = pwm_get_chip_data(pwm);
99b82abb LP	362
99b82abb LP	363	/* The timer must be running to modify the pin output configuration. */
208ab867 UKK	364	tpu_pwm_timer_start(tpd);
	365	tpu_pwm_set_pin(tpd, TPU_PIN_INACTIVE);
	366	tpu_pwm_timer_stop(tpd);
99b82abb LP	367	}
99b82abb LP	368
ec00cd5e UKK	369	static int tpu_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	370	const struct pwm_state *state)
	371	{
	372	int err;
	373	bool enabled = pwm->state.enabled;
	374
	375	if (state->polarity != pwm->state.polarity) {
	376	if (enabled) {
	377	tpu_pwm_disable(chip, pwm);
	378	enabled = false;
	379	}
	380
	381	err = tpu_pwm_set_polarity(chip, pwm, state->polarity);
	382	if (err)
	383	return err;
	384	}
	385
	386	if (!state->enabled) {
	387	if (enabled)
	388	tpu_pwm_disable(chip, pwm);
	389
	390	return 0;
	391	}
	392
	393	err = tpu_pwm_config(pwm->chip, pwm,
	394	state->duty_cycle, state->period, enabled);
	395	if (err)
	396	return err;
	397
	398	if (!enabled)
	399	err = tpu_pwm_enable(chip, pwm);
	400
	401	return err;
	402	}
	403
99b82abb LP	404	static const struct pwm_ops tpu_pwm_ops = {
	405	.request = tpu_pwm_request,
	406	.free = tpu_pwm_free,
ec00cd5e	407	.apply = tpu_pwm_apply,
99b82abb LP	408	.owner = THIS_MODULE,
	409	};
	410
	411	/* -----------------------------------------------------------------------------
	412	* Probe and remove
	413	*/
	414
	415	static int tpu_probe(struct platform_device *pdev)
	416	{
	417	struct tpu_device *tpu;
99b82abb LP	418	int ret;
	419
	420	tpu = devm_kzalloc(&pdev->dev, sizeof(*tpu), GFP_KERNEL);
6c5059cc	421	if (tpu == NULL)
99b82abb	422	return -ENOMEM;
99b82abb	423
382457e5 LP	424	spin_lock_init(&tpu->lock);
	425	tpu->pdev = pdev;
	426
99b82abb	427	/* Map memory, get clock and pin control. */
e3f22bc2	428	tpu->base = devm_platform_ioremap_resource(pdev, 0);
00cf99ee WY	429	if (IS_ERR(tpu->base))
00cf99ee WY	430	return PTR_ERR(tpu->base);
99b82abb LP	431
99b82abb LP	432	tpu->clk = devm_clk_get(&pdev->dev, NULL);
6eb3af76 UKK	433	if (IS_ERR(tpu->clk))
6eb3af76 UKK	434	return dev_err_probe(&pdev->dev, PTR_ERR(tpu->clk), "Failed to get clock\n");
99b82abb LP	435
	436	/* Initialize and register the device. */
	437	platform_set_drvdata(pdev, tpu);
	438
99b82abb LP	439	tpu->chip.dev = &pdev->dev;
99b82abb LP	440	tpu->chip.ops = &tpu_pwm_ops;
99b82abb LP	441	tpu->chip.npwm = TPU_CHANNEL_MAX;
99b82abb LP	442
ff4bcd56 UKK	443	ret = devm_pm_runtime_enable(&pdev->dev);
	444	if (ret < 0)
	445	return dev_err_probe(&pdev->dev, ret, "Failed to enable runtime PM\n");
d5a3c7a4	446
ff4bcd56 UKK	447	ret = devm_pwmchip_add(&pdev->dev, &tpu->chip);
ff4bcd56 UKK	448	if (ret < 0)
6eb3af76	449	return dev_err_probe(&pdev->dev, ret, "Failed to register PWM chip\n");
99b82abb	450
81d4b5c4	451	return 0;
99b82abb LP	452	}
99b82abb LP	453
382457e5 LP	454	#ifdef CONFIG_OF
	455	static const struct of_device_id tpu_of_table[] = {
	456	{ .compatible = "renesas,tpu-r8a73a4", },
	457	{ .compatible = "renesas,tpu-r8a7740", },
	458	{ .compatible = "renesas,tpu-r8a7790", },
382457e5 LP	459	{ .compatible = "renesas,tpu", },
	460	{ },
	461	};
	462
	463	MODULE_DEVICE_TABLE(of, tpu_of_table);
	464	#endif
	465
99b82abb LP	466	static struct platform_driver tpu_driver = {
99b82abb LP	467	.probe = tpu_probe,
99b82abb LP	468	.driver = {
99b82abb LP	469	.name = "renesas-tpu-pwm",
382457e5	470	.of_match_table = of_match_ptr(tpu_of_table),
99b82abb LP	471	}
	472	};
	473
	474	module_platform_driver(tpu_driver);
	475
	476	MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
	477	MODULE_DESCRIPTION("Renesas TPU PWM Driver");
	478	MODULE_LICENSE("GPL v2");
71077bc8	479	MODULE_ALIAS("platform:renesas-tpu-pwm");