[linux-2.6-block.git] / drivers / pwm / pwm-rcar.c

// SPDX-License-Identifier: GPL-2.0
/*
 * R-Car PWM Timer driver
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/log2.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/pwm.h>
#include <linux/slab.h>

#define RCAR_PWM_MAX_DIVISION	24
#define RCAR_PWM_MAX_CYCLE	1023

#define RCAR_PWMCR		0x00
#define  RCAR_PWMCR_CC0_MASK	0x000f0000
#define  RCAR_PWMCR_CC0_SHIFT	16
#define  RCAR_PWMCR_CCMD	BIT(15)
#define  RCAR_PWMCR_SYNC	BIT(11)
#define  RCAR_PWMCR_SS0		BIT(4)
#define  RCAR_PWMCR_EN0		BIT(0)

#define RCAR_PWMCNT		0x04
#define  RCAR_PWMCNT_CYC0_MASK	0x03ff0000
#define  RCAR_PWMCNT_CYC0_SHIFT	16
#define  RCAR_PWMCNT_PH0_MASK	0x000003ff
#define  RCAR_PWMCNT_PH0_SHIFT	0

struct rcar_pwm_chip {
	struct pwm_chip chip;
	void __iomem *base;
	struct clk *clk;
};

static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
{
	return container_of(chip, struct rcar_pwm_chip, chip);
}

static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
			   unsigned int offset)
{
	writel(data, rp->base + offset);
}

static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
{
	return readl(rp->base + offset);
}

static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
			    unsigned int offset)
{
	u32 value;

	value = rcar_pwm_read(rp, offset);
	value &= ~mask;
	value |= data & mask;
	rcar_pwm_write(rp, value, offset);
}

static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
{
	unsigned long clk_rate = clk_get_rate(rp->clk);
	u64 div, tmp;

	if (clk_rate == 0)
		return -EINVAL;

	div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
	tmp = (u64)period_ns * clk_rate + div - 1;
	tmp = div64_u64(tmp, div);
	div = ilog2(tmp - 1) + 1;

	return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
}

static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
				       unsigned int div)
{
	u32 value;

	value = rcar_pwm_read(rp, RCAR_PWMCR);
	value &= ~(RCAR_PWMCR_CCMD | RCAR_PWMCR_CC0_MASK);

	if (div & 1)
		value |= RCAR_PWMCR_CCMD;

	div >>= 1;

	value |= div << RCAR_PWMCR_CC0_SHIFT;
	rcar_pwm_write(rp, value, RCAR_PWMCR);
}

static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
				int period_ns)
{
	unsigned long long one_cycle, tmp;	/* 0.01 nanoseconds */
	unsigned long clk_rate = clk_get_rate(rp->clk);
	u32 cyc, ph;

	one_cycle = (unsigned long long)NSEC_PER_SEC * 100ULL * (1 << div);
	do_div(one_cycle, clk_rate);

	tmp = period_ns * 100ULL;
	do_div(tmp, one_cycle);
	cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;

	tmp = duty_ns * 100ULL;
	do_div(tmp, one_cycle);
	ph = tmp & RCAR_PWMCNT_PH0_MASK;

	/* Avoid prohibited setting */
	if (cyc == 0 || ph == 0)
		return -EINVAL;

	rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);

	return 0;
}

static int rcar_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
	return pm_runtime_get_sync(chip->dev);
}

static void rcar_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
{
	pm_runtime_put(chip->dev);
}

static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
{
	u32 value;

	/* Don't enable the PWM device if CYC0 or PH0 is 0 */
	value = rcar_pwm_read(rp, RCAR_PWMCNT);
	if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 ||
	    (value & RCAR_PWMCNT_PH0_MASK) == 0)
		return -EINVAL;

	rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);

	return 0;
}

static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
{
	rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
}

static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
			  struct pwm_state *state)
{
	struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
	struct pwm_state cur_state;
	int div, ret;

	/* This HW/driver only supports normal polarity */
	pwm_get_state(pwm, &cur_state);
	if (state->polarity != PWM_POLARITY_NORMAL)
		return -ENOTSUPP;

	if (!state->enabled) {
		rcar_pwm_disable(rp);
		return 0;
	}

	div = rcar_pwm_get_clock_division(rp, state->period);
	if (div < 0)
		return div;

	rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);

	ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
	if (!ret)
		rcar_pwm_set_clock_control(rp, div);

	/* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
	rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);

	if (!ret && state->enabled)
		ret = rcar_pwm_enable(rp);

	return ret;
}

static const struct pwm_ops rcar_pwm_ops = {
	.request = rcar_pwm_request,
	.free = rcar_pwm_free,
	.apply = rcar_pwm_apply,
	.owner = THIS_MODULE,
};

static int rcar_pwm_probe(struct platform_device *pdev)
{
	struct rcar_pwm_chip *rcar_pwm;
	struct resource *res;
	int ret;

	rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
	if (rcar_pwm == NULL)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(rcar_pwm->base))
		return PTR_ERR(rcar_pwm->base);

	rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(rcar_pwm->clk)) {
		dev_err(&pdev->dev, "cannot get clock\n");
		return PTR_ERR(rcar_pwm->clk);
	}

	platform_set_drvdata(pdev, rcar_pwm);

	rcar_pwm->chip.dev = &pdev->dev;
	rcar_pwm->chip.ops = &rcar_pwm_ops;
	rcar_pwm->chip.base = -1;
	rcar_pwm->chip.npwm = 1;

	ret = pwmchip_add(&rcar_pwm->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
		return ret;
	}

	pm_runtime_enable(&pdev->dev);

	return 0;
}

static int rcar_pwm_remove(struct platform_device *pdev)
{
	struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);

	pm_runtime_disable(&pdev->dev);

	return pwmchip_remove(&rcar_pwm->chip);
}

static const struct of_device_id rcar_pwm_of_table[] = {
	{ .compatible = "renesas,pwm-rcar", },
	{ },
};
MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);

static struct platform_driver rcar_pwm_driver = {
	.probe = rcar_pwm_probe,
	.remove = rcar_pwm_remove,
	.driver = {
		.name = "pwm-rcar",
		.of_match_table = of_match_ptr(rcar_pwm_of_table),
	}
};
module_platform_driver(rcar_pwm_driver);

MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
MODULE_DESCRIPTION("Renesas PWM Timer Driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:pwm-rcar");
Commit	Line	Data
e4ab5172	1	// SPDX-License-Identifier: GPL-2.0
ed6c1476 YS	2	/*
	3	* R-Car PWM Timer driver
	4	*
	5	* Copyright (C) 2015 Renesas Electronics Corporation
ed6c1476 YS	6	*/
	7
	8	#include <linux/clk.h>
	9	#include <linux/err.h>
	10	#include <linux/io.h>
b4f9a726 YS	11	#include <linux/log2.h>
b4f9a726 YS	12	#include <linux/math64.h>
ed6c1476 YS	13	#include <linux/module.h>
	14	#include <linux/of.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/pm_runtime.h>
	17	#include <linux/pwm.h>
	18	#include <linux/slab.h>
	19
	20	#define RCAR_PWM_MAX_DIVISION 24
	21	#define RCAR_PWM_MAX_CYCLE 1023
	22
	23	#define RCAR_PWMCR 0x00
	24	#define RCAR_PWMCR_CC0_MASK 0x000f0000
	25	#define RCAR_PWMCR_CC0_SHIFT 16
	26	#define RCAR_PWMCR_CCMD BIT(15)
	27	#define RCAR_PWMCR_SYNC BIT(11)
	28	#define RCAR_PWMCR_SS0 BIT(4)
	29	#define RCAR_PWMCR_EN0 BIT(0)
	30
	31	#define RCAR_PWMCNT 0x04
	32	#define RCAR_PWMCNT_CYC0_MASK 0x03ff0000
	33	#define RCAR_PWMCNT_CYC0_SHIFT 16
	34	#define RCAR_PWMCNT_PH0_MASK 0x000003ff
	35	#define RCAR_PWMCNT_PH0_SHIFT 0
	36
	37	struct rcar_pwm_chip {
	38	struct pwm_chip chip;
	39	void __iomem *base;
	40	struct clk *clk;
	41	};
	42
	43	static inline struct rcar_pwm_chip to_rcar_pwm_chip(struct pwm_chip chip)
	44	{
	45	return container_of(chip, struct rcar_pwm_chip, chip);
	46	}
	47
	48	static void rcar_pwm_write(struct rcar_pwm_chip *rp, u32 data,
	49	unsigned int offset)
	50	{
	51	writel(data, rp->base + offset);
	52	}
	53
	54	static u32 rcar_pwm_read(struct rcar_pwm_chip *rp, unsigned int offset)
	55	{
	56	return readl(rp->base + offset);
	57	}
	58
	59	static void rcar_pwm_update(struct rcar_pwm_chip *rp, u32 mask, u32 data,
	60	unsigned int offset)
	61	{
	62	u32 value;
	63
	64	value = rcar_pwm_read(rp, offset);
	65	value &= ~mask;
	66	value \|= data & mask;
	67	rcar_pwm_write(rp, value, offset);
	68	}
	69
	70	static int rcar_pwm_get_clock_division(struct rcar_pwm_chip *rp, int period_ns)
	71	{
	72	unsigned long clk_rate = clk_get_rate(rp->clk);
b4f9a726	73	u64 div, tmp;
ed6c1476 YS	74
	75	if (clk_rate == 0)
	76	return -EINVAL;
	77
b4f9a726 YS	78	div = (u64)NSEC_PER_SEC * RCAR_PWM_MAX_CYCLE;
	79	tmp = (u64)period_ns * clk_rate + div - 1;
	80	tmp = div64_u64(tmp, div);
	81	div = ilog2(tmp - 1) + 1;
ed6c1476 YS	82
	83	return (div <= RCAR_PWM_MAX_DIVISION) ? div : -ERANGE;
	84	}
	85
	86	static void rcar_pwm_set_clock_control(struct rcar_pwm_chip *rp,
	87	unsigned int div)
	88	{
	89	u32 value;
	90
	91	value = rcar_pwm_read(rp, RCAR_PWMCR);
	92	value &= ~(RCAR_PWMCR_CCMD \| RCAR_PWMCR_CC0_MASK);
	93
	94	if (div & 1)
	95	value \|= RCAR_PWMCR_CCMD;
	96
	97	div >>= 1;
	98
	99	value \|= div << RCAR_PWMCR_CC0_SHIFT;
	100	rcar_pwm_write(rp, value, RCAR_PWMCR);
	101	}
	102
	103	static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
	104	int period_ns)
	105	{
	106	unsigned long long one_cycle, tmp; /* 0.01 nanoseconds */
	107	unsigned long clk_rate = clk_get_rate(rp->clk);
	108	u32 cyc, ph;
	109
	110	one_cycle = (unsigned long long)NSEC_PER_SEC * 100ULL * (1 << div);
	111	do_div(one_cycle, clk_rate);
	112
	113	tmp = period_ns * 100ULL;
	114	do_div(tmp, one_cycle);
	115	cyc = (tmp << RCAR_PWMCNT_CYC0_SHIFT) & RCAR_PWMCNT_CYC0_MASK;
	116
	117	tmp = duty_ns * 100ULL;
	118	do_div(tmp, one_cycle);
	119	ph = tmp & RCAR_PWMCNT_PH0_MASK;
	120
	121	/* Avoid prohibited setting */
	122	if (cyc == 0 \|\| ph == 0)
	123	return -EINVAL;
	124
	125	rcar_pwm_write(rp, cyc \| ph, RCAR_PWMCNT);
	126
	127	return 0;
	128	}
	129
	130	static int rcar_pwm_request(struct pwm_chip chip, struct pwm_device pwm)
	131	{
f2e6142c	132	return pm_runtime_get_sync(chip->dev);
ed6c1476 YS	133	}
	134
	135	static void rcar_pwm_free(struct pwm_chip chip, struct pwm_device pwm)
	136	{
f2e6142c	137	pm_runtime_put(chip->dev);
ed6c1476 YS	138	}
ed6c1476 YS	139
8cc2b970	140	static int rcar_pwm_enable(struct rcar_pwm_chip *rp)
ed6c1476	141	{
ed6c1476 YS	142	u32 value;
	143
	144	/* Don't enable the PWM device if CYC0 or PH0 is 0 */
	145	value = rcar_pwm_read(rp, RCAR_PWMCNT);
	146	if ((value & RCAR_PWMCNT_CYC0_MASK) == 0 \|\|
	147	(value & RCAR_PWMCNT_PH0_MASK) == 0)
	148	return -EINVAL;
	149
	150	rcar_pwm_update(rp, RCAR_PWMCR_EN0, RCAR_PWMCR_EN0, RCAR_PWMCR);
	151
	152	return 0;
	153	}
	154
8cc2b970	155	static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
ed6c1476	156	{
ed6c1476 YS	157	rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
	158	}
	159
7f68ce82 YS	160	static int rcar_pwm_apply(struct pwm_chip chip, struct pwm_device pwm,
	161	struct pwm_state *state)
	162	{
	163	struct rcar_pwm_chip *rp = to_rcar_pwm_chip(chip);
	164	struct pwm_state cur_state;
	165	int div, ret;
	166
	167	/* This HW/driver only supports normal polarity */
	168	pwm_get_state(pwm, &cur_state);
	169	if (state->polarity != PWM_POLARITY_NORMAL)
	170	return -ENOTSUPP;
	171
	172	if (!state->enabled) {
8cc2b970	173	rcar_pwm_disable(rp);
7f68ce82 YS	174	return 0;
	175	}
	176
	177	div = rcar_pwm_get_clock_division(rp, state->period);
	178	if (div < 0)
	179	return div;
	180
	181	rcar_pwm_update(rp, RCAR_PWMCR_SYNC, RCAR_PWMCR_SYNC, RCAR_PWMCR);
	182
	183	ret = rcar_pwm_set_counter(rp, div, state->duty_cycle, state->period);
	184	if (!ret)
	185	rcar_pwm_set_clock_control(rp, div);
	186
	187	/* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
	188	rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
	189
	190	if (!ret && state->enabled)
8cc2b970	191	ret = rcar_pwm_enable(rp);
7f68ce82 YS	192
	193	return ret;
	194	}
	195
ed6c1476 YS	196	static const struct pwm_ops rcar_pwm_ops = {
	197	.request = rcar_pwm_request,
	198	.free = rcar_pwm_free,
7f68ce82	199	.apply = rcar_pwm_apply,
ed6c1476 YS	200	.owner = THIS_MODULE,
	201	};
	202
	203	static int rcar_pwm_probe(struct platform_device *pdev)
	204	{
	205	struct rcar_pwm_chip *rcar_pwm;
	206	struct resource *res;
	207	int ret;
	208
	209	rcar_pwm = devm_kzalloc(&pdev->dev, sizeof(*rcar_pwm), GFP_KERNEL);
	210	if (rcar_pwm == NULL)
	211	return -ENOMEM;
	212
	213	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	214	rcar_pwm->base = devm_ioremap_resource(&pdev->dev, res);
	215	if (IS_ERR(rcar_pwm->base))
	216	return PTR_ERR(rcar_pwm->base);
	217
	218	rcar_pwm->clk = devm_clk_get(&pdev->dev, NULL);
	219	if (IS_ERR(rcar_pwm->clk)) {
	220	dev_err(&pdev->dev, "cannot get clock\n");
	221	return PTR_ERR(rcar_pwm->clk);
	222	}
	223
	224	platform_set_drvdata(pdev, rcar_pwm);
	225
	226	rcar_pwm->chip.dev = &pdev->dev;
	227	rcar_pwm->chip.ops = &rcar_pwm_ops;
	228	rcar_pwm->chip.base = -1;
	229	rcar_pwm->chip.npwm = 1;
	230
	231	ret = pwmchip_add(&rcar_pwm->chip);
	232	if (ret < 0) {
	233	dev_err(&pdev->dev, "failed to register PWM chip: %d\n", ret);
	234	return ret;
	235	}
	236
	237	pm_runtime_enable(&pdev->dev);
	238
	239	return 0;
	240	}
	241
	242	static int rcar_pwm_remove(struct platform_device *pdev)
	243	{
	244	struct rcar_pwm_chip *rcar_pwm = platform_get_drvdata(pdev);
	245
	246	pm_runtime_disable(&pdev->dev);
	247
	248	return pwmchip_remove(&rcar_pwm->chip);
	249	}
	250
	251	static const struct of_device_id rcar_pwm_of_table[] = {
	252	{ .compatible = "renesas,pwm-rcar", },
	253	{ },
	254	};
	255	MODULE_DEVICE_TABLE(of, rcar_pwm_of_table);
	256
	257	static struct platform_driver rcar_pwm_driver = {
	258	.probe = rcar_pwm_probe,
	259	.remove = rcar_pwm_remove,
	260	.driver = {
	261	.name = "pwm-rcar",
	262	.of_match_table = of_match_ptr(rcar_pwm_of_table),
	263	}
264	};
265	module_platform_driver(rcar_pwm_driver);
266
267	MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");
268	MODULE_DESCRIPTION("Renesas PWM Timer Driver");
269	MODULE_LICENSE("GPL v2");
270	MODULE_ALIAS("platform:pwm-rcar");