Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
75540c1a | 2 | /* |
45b301d2 | 3 | * drivers/pwm/pwm-pxa.c |
75540c1a | 4 | * |
5 | * simple driver for PWM (Pulse Width Modulator) controller | |
6 | * | |
75540c1a | 7 | * 2008-02-13 initial version |
b07ab663 | 8 | * eric miao <eric.miao@marvell.com> |
8ba2725f DB |
9 | * |
10 | * Links to reference manuals for some of the supported PWM chips can be found | |
11 | * in Documentation/arm/marvell.rst. | |
12 | * | |
13 | * Limitations: | |
14 | * - When PWM is stopped, the current PWM period stops abruptly at the next | |
15 | * input clock (PWMCR_SD is set) and the output is driven to inactive. | |
75540c1a | 16 | */ |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/platform_device.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
75540c1a | 22 | #include <linux/err.h> |
23 | #include <linux/clk.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/pwm.h> | |
b52fa7bc | 26 | #include <linux/of_device.h> |
75540c1a | 27 | |
28 | #include <asm/div64.h> | |
75540c1a | 29 | |
3d2a98cd EM |
30 | #define HAS_SECONDARY_PWM 0x10 |
31 | ||
32 | static const struct platform_device_id pwm_id_table[] = { | |
33 | /* PWM has_secondary_pwm? */ | |
34 | { "pxa25x-pwm", 0 }, | |
22976a5d AL |
35 | { "pxa27x-pwm", HAS_SECONDARY_PWM }, |
36 | { "pxa168-pwm", 0 }, | |
37 | { "pxa910-pwm", 0 }, | |
3d2a98cd EM |
38 | { }, |
39 | }; | |
40 | MODULE_DEVICE_TABLE(platform, pwm_id_table); | |
41 | ||
75540c1a | 42 | /* PWM registers and bits definitions */ |
43 | #define PWMCR (0x00) | |
44 | #define PWMDCR (0x04) | |
45 | #define PWMPCR (0x08) | |
46 | ||
47 | #define PWMCR_SD (1 << 6) | |
48 | #define PWMDCR_FD (1 << 10) | |
49 | ||
17b2b478 TR |
50 | struct pxa_pwm_chip { |
51 | struct pwm_chip chip; | |
52 | struct device *dev; | |
75540c1a | 53 | |
75540c1a | 54 | struct clk *clk; |
55 | void __iomem *mmio_base; | |
75540c1a | 56 | }; |
57 | ||
17b2b478 TR |
58 | static inline struct pxa_pwm_chip *to_pxa_pwm_chip(struct pwm_chip *chip) |
59 | { | |
60 | return container_of(chip, struct pxa_pwm_chip, chip); | |
61 | } | |
62 | ||
75540c1a | 63 | /* |
64 | * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE | |
65 | * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE | |
66 | */ | |
17b2b478 | 67 | static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
657e54e5 | 68 | u64 duty_ns, u64 period_ns) |
75540c1a | 69 | { |
17b2b478 | 70 | struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); |
75540c1a | 71 | unsigned long long c; |
72 | unsigned long period_cycles, prescale, pv, dc; | |
17b2b478 | 73 | unsigned long offset; |
75540c1a | 74 | |
17b2b478 TR |
75 | offset = pwm->hwpwm ? 0x10 : 0; |
76 | ||
77 | c = clk_get_rate(pc->clk); | |
75540c1a | 78 | c = c * period_ns; |
79 | do_div(c, 1000000000); | |
80 | period_cycles = c; | |
81 | ||
71a35d75 | 82 | if (period_cycles < 1) |
75540c1a | 83 | period_cycles = 1; |
84 | prescale = (period_cycles - 1) / 1024; | |
85 | pv = period_cycles / (prescale + 1) - 1; | |
86 | ||
87 | if (prescale > 63) | |
88 | return -EINVAL; | |
89 | ||
90 | if (duty_ns == period_ns) | |
91 | dc = PWMDCR_FD; | |
92 | else | |
657e54e5 | 93 | dc = mul_u64_u64_div_u64(pv + 1, duty_ns, period_ns); |
75540c1a | 94 | |
092c2ef4 | 95 | writel(prescale | PWMCR_SD, pc->mmio_base + offset + PWMCR); |
17b2b478 TR |
96 | writel(dc, pc->mmio_base + offset + PWMDCR); |
97 | writel(pv, pc->mmio_base + offset + PWMPCR); | |
75540c1a | 98 | |
99 | return 0; | |
100 | } | |
75540c1a | 101 | |
657e54e5 UKK |
102 | static int pxa_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
103 | const struct pwm_state *state) | |
104 | { | |
f956b838 | 105 | struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); |
152f2d1d | 106 | u64 duty_cycle; |
657e54e5 UKK |
107 | int err; |
108 | ||
109 | if (state->polarity != PWM_POLARITY_NORMAL) | |
110 | return -EINVAL; | |
111 | ||
152f2d1d DB |
112 | err = clk_prepare_enable(pc->clk); |
113 | if (err) | |
114 | return err; | |
657e54e5 | 115 | |
152f2d1d | 116 | duty_cycle = state->enabled ? state->duty_cycle : 0; |
657e54e5 | 117 | |
152f2d1d DB |
118 | err = pxa_pwm_config(chip, pwm, duty_cycle, state->period); |
119 | if (err) { | |
120 | clk_disable_unprepare(pc->clk); | |
657e54e5 | 121 | return err; |
152f2d1d DB |
122 | } |
123 | ||
124 | if (state->enabled && !pwm->state.enabled) | |
125 | return 0; | |
126 | ||
127 | clk_disable_unprepare(pc->clk); | |
657e54e5 | 128 | |
152f2d1d DB |
129 | if (!state->enabled && pwm->state.enabled) |
130 | clk_disable_unprepare(pc->clk); | |
657e54e5 UKK |
131 | |
132 | return 0; | |
133 | } | |
134 | ||
b2ec9efc | 135 | static const struct pwm_ops pxa_pwm_ops = { |
657e54e5 | 136 | .apply = pxa_pwm_apply, |
17b2b478 TR |
137 | .owner = THIS_MODULE, |
138 | }; | |
75540c1a | 139 | |
b52fa7bc MD |
140 | #ifdef CONFIG_OF |
141 | /* | |
fdec4f72 | 142 | * Device tree users must create one device instance for each PWM channel. |
b52fa7bc MD |
143 | * Hence we dispense with the HAS_SECONDARY_PWM and "tell" the original driver |
144 | * code that this is a single channel pxa25x-pwm. Currently all devices are | |
145 | * supported identically. | |
146 | */ | |
2ae69a46 | 147 | static const struct of_device_id pwm_of_match[] = { |
b52fa7bc MD |
148 | { .compatible = "marvell,pxa250-pwm", .data = &pwm_id_table[0]}, |
149 | { .compatible = "marvell,pxa270-pwm", .data = &pwm_id_table[0]}, | |
150 | { .compatible = "marvell,pxa168-pwm", .data = &pwm_id_table[0]}, | |
151 | { .compatible = "marvell,pxa910-pwm", .data = &pwm_id_table[0]}, | |
152 | { } | |
153 | }; | |
154 | MODULE_DEVICE_TABLE(of, pwm_of_match); | |
f409cd38 TR |
155 | #else |
156 | #define pwm_of_match NULL | |
b52fa7bc MD |
157 | #endif |
158 | ||
159 | static const struct platform_device_id *pxa_pwm_get_id_dt(struct device *dev) | |
160 | { | |
161 | const struct of_device_id *id = of_match_device(pwm_of_match, dev); | |
162 | ||
163 | return id ? id->data : NULL; | |
164 | } | |
165 | ||
3e9fe83d | 166 | static int pwm_probe(struct platform_device *pdev) |
75540c1a | 167 | { |
b3282ab1 | 168 | const struct platform_device_id *id = platform_get_device_id(pdev); |
b63d60b2 | 169 | struct pxa_pwm_chip *pc; |
75540c1a | 170 | int ret = 0; |
171 | ||
b52fa7bc MD |
172 | if (IS_ENABLED(CONFIG_OF) && id == NULL) |
173 | id = pxa_pwm_get_id_dt(&pdev->dev); | |
174 | ||
175 | if (id == NULL) | |
176 | return -EINVAL; | |
177 | ||
b63d60b2 UKK |
178 | pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); |
179 | if (pc == NULL) | |
3d2a98cd | 180 | return -ENOMEM; |
75540c1a | 181 | |
b63d60b2 UKK |
182 | pc->clk = devm_clk_get(&pdev->dev, NULL); |
183 | if (IS_ERR(pc->clk)) | |
184 | return PTR_ERR(pc->clk); | |
45b301d2 | 185 | |
b63d60b2 UKK |
186 | pc->chip.dev = &pdev->dev; |
187 | pc->chip.ops = &pxa_pwm_ops; | |
188 | pc->chip.npwm = (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1; | |
75540c1a | 189 | |
b52fa7bc | 190 | if (IS_ENABLED(CONFIG_OF)) { |
3ab7b6ac | 191 | pc->chip.of_xlate = of_pwm_single_xlate; |
b63d60b2 | 192 | pc->chip.of_pwm_n_cells = 1; |
b52fa7bc MD |
193 | } |
194 | ||
b63d60b2 UKK |
195 | pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); |
196 | if (IS_ERR(pc->mmio_base)) | |
197 | return PTR_ERR(pc->mmio_base); | |
75540c1a | 198 | |
97f29035 | 199 | ret = devm_pwmchip_add(&pdev->dev, &pc->chip); |
17b2b478 TR |
200 | if (ret < 0) { |
201 | dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); | |
202 | return ret; | |
3d2a98cd EM |
203 | } |
204 | ||
3d2a98cd | 205 | return 0; |
75540c1a | 206 | } |
207 | ||
3d2a98cd | 208 | static struct platform_driver pwm_driver = { |
75540c1a | 209 | .driver = { |
210 | .name = "pxa25x-pwm", | |
f409cd38 | 211 | .of_match_table = pwm_of_match, |
75540c1a | 212 | }, |
3d2a98cd | 213 | .probe = pwm_probe, |
3d2a98cd | 214 | .id_table = pwm_id_table, |
75540c1a | 215 | }; |
216 | ||
1e185c7a | 217 | module_platform_driver(pwm_driver); |
b5f0228a GL |
218 | |
219 | MODULE_LICENSE("GPL v2"); |