Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
75540c1a | 2 | /* |
45b301d2 | 3 | * drivers/pwm/pwm-pxa.c |
75540c1a | 4 | * |
5 | * simple driver for PWM (Pulse Width Modulator) controller | |
6 | * | |
75540c1a | 7 | * 2008-02-13 initial version |
b07ab663 | 8 | * eric miao <eric.miao@marvell.com> |
75540c1a | 9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/platform_device.h> | |
5a0e3ad6 | 14 | #include <linux/slab.h> |
75540c1a | 15 | #include <linux/err.h> |
16 | #include <linux/clk.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/pwm.h> | |
b52fa7bc | 19 | #include <linux/of_device.h> |
75540c1a | 20 | |
21 | #include <asm/div64.h> | |
75540c1a | 22 | |
3d2a98cd EM |
23 | #define HAS_SECONDARY_PWM 0x10 |
24 | ||
25 | static const struct platform_device_id pwm_id_table[] = { | |
26 | /* PWM has_secondary_pwm? */ | |
27 | { "pxa25x-pwm", 0 }, | |
22976a5d AL |
28 | { "pxa27x-pwm", HAS_SECONDARY_PWM }, |
29 | { "pxa168-pwm", 0 }, | |
30 | { "pxa910-pwm", 0 }, | |
3d2a98cd EM |
31 | { }, |
32 | }; | |
33 | MODULE_DEVICE_TABLE(platform, pwm_id_table); | |
34 | ||
75540c1a | 35 | /* PWM registers and bits definitions */ |
36 | #define PWMCR (0x00) | |
37 | #define PWMDCR (0x04) | |
38 | #define PWMPCR (0x08) | |
39 | ||
40 | #define PWMCR_SD (1 << 6) | |
41 | #define PWMDCR_FD (1 << 10) | |
42 | ||
17b2b478 TR |
43 | struct pxa_pwm_chip { |
44 | struct pwm_chip chip; | |
45 | struct device *dev; | |
75540c1a | 46 | |
75540c1a | 47 | struct clk *clk; |
48 | void __iomem *mmio_base; | |
75540c1a | 49 | }; |
50 | ||
17b2b478 TR |
51 | static inline struct pxa_pwm_chip *to_pxa_pwm_chip(struct pwm_chip *chip) |
52 | { | |
53 | return container_of(chip, struct pxa_pwm_chip, chip); | |
54 | } | |
55 | ||
75540c1a | 56 | /* |
57 | * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE | |
58 | * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE | |
59 | */ | |
17b2b478 TR |
60 | static int pxa_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
61 | int duty_ns, int period_ns) | |
75540c1a | 62 | { |
17b2b478 | 63 | struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); |
75540c1a | 64 | unsigned long long c; |
65 | unsigned long period_cycles, prescale, pv, dc; | |
17b2b478 TR |
66 | unsigned long offset; |
67 | int rc; | |
75540c1a | 68 | |
17b2b478 TR |
69 | offset = pwm->hwpwm ? 0x10 : 0; |
70 | ||
71 | c = clk_get_rate(pc->clk); | |
75540c1a | 72 | c = c * period_ns; |
73 | do_div(c, 1000000000); | |
74 | period_cycles = c; | |
75 | ||
71a35d75 | 76 | if (period_cycles < 1) |
75540c1a | 77 | period_cycles = 1; |
78 | prescale = (period_cycles - 1) / 1024; | |
79 | pv = period_cycles / (prescale + 1) - 1; | |
80 | ||
81 | if (prescale > 63) | |
82 | return -EINVAL; | |
83 | ||
84 | if (duty_ns == period_ns) | |
85 | dc = PWMDCR_FD; | |
86 | else | |
87 | dc = (pv + 1) * duty_ns / period_ns; | |
88 | ||
89 | /* NOTE: the clock to PWM has to be enabled first | |
90 | * before writing to the registers | |
91 | */ | |
17b2b478 TR |
92 | rc = clk_prepare_enable(pc->clk); |
93 | if (rc < 0) | |
94 | return rc; | |
95 | ||
96 | writel(prescale, pc->mmio_base + offset + PWMCR); | |
97 | writel(dc, pc->mmio_base + offset + PWMDCR); | |
98 | writel(pv, pc->mmio_base + offset + PWMPCR); | |
75540c1a | 99 | |
17b2b478 | 100 | clk_disable_unprepare(pc->clk); |
75540c1a | 101 | return 0; |
102 | } | |
75540c1a | 103 | |
17b2b478 | 104 | static int pxa_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
75540c1a | 105 | { |
17b2b478 | 106 | struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); |
c860d701 | 107 | |
b014a30c | 108 | return clk_prepare_enable(pc->clk); |
75540c1a | 109 | } |
75540c1a | 110 | |
17b2b478 | 111 | static void pxa_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
75540c1a | 112 | { |
17b2b478 | 113 | struct pxa_pwm_chip *pc = to_pxa_pwm_chip(chip); |
75540c1a | 114 | |
b014a30c | 115 | clk_disable_unprepare(pc->clk); |
75540c1a | 116 | } |
75540c1a | 117 | |
b2ec9efc | 118 | static const struct pwm_ops pxa_pwm_ops = { |
17b2b478 TR |
119 | .config = pxa_pwm_config, |
120 | .enable = pxa_pwm_enable, | |
121 | .disable = pxa_pwm_disable, | |
122 | .owner = THIS_MODULE, | |
123 | }; | |
75540c1a | 124 | |
b52fa7bc MD |
125 | #ifdef CONFIG_OF |
126 | /* | |
fdec4f72 | 127 | * Device tree users must create one device instance for each PWM channel. |
b52fa7bc MD |
128 | * Hence we dispense with the HAS_SECONDARY_PWM and "tell" the original driver |
129 | * code that this is a single channel pxa25x-pwm. Currently all devices are | |
130 | * supported identically. | |
131 | */ | |
2ae69a46 | 132 | static const struct of_device_id pwm_of_match[] = { |
b52fa7bc MD |
133 | { .compatible = "marvell,pxa250-pwm", .data = &pwm_id_table[0]}, |
134 | { .compatible = "marvell,pxa270-pwm", .data = &pwm_id_table[0]}, | |
135 | { .compatible = "marvell,pxa168-pwm", .data = &pwm_id_table[0]}, | |
136 | { .compatible = "marvell,pxa910-pwm", .data = &pwm_id_table[0]}, | |
137 | { } | |
138 | }; | |
139 | MODULE_DEVICE_TABLE(of, pwm_of_match); | |
f409cd38 TR |
140 | #else |
141 | #define pwm_of_match NULL | |
b52fa7bc MD |
142 | #endif |
143 | ||
144 | static const struct platform_device_id *pxa_pwm_get_id_dt(struct device *dev) | |
145 | { | |
146 | const struct of_device_id *id = of_match_device(pwm_of_match, dev); | |
147 | ||
148 | return id ? id->data : NULL; | |
149 | } | |
150 | ||
151 | static struct pwm_device * | |
152 | pxa_pwm_of_xlate(struct pwm_chip *pc, const struct of_phandle_args *args) | |
153 | { | |
154 | struct pwm_device *pwm; | |
155 | ||
156 | pwm = pwm_request_from_chip(pc, 0, NULL); | |
157 | if (IS_ERR(pwm)) | |
158 | return pwm; | |
159 | ||
e39c0df1 | 160 | pwm->args.period = args->args[0]; |
b52fa7bc MD |
161 | |
162 | return pwm; | |
163 | } | |
164 | ||
3e9fe83d | 165 | static int pwm_probe(struct platform_device *pdev) |
75540c1a | 166 | { |
b3282ab1 | 167 | const struct platform_device_id *id = platform_get_device_id(pdev); |
17b2b478 | 168 | struct pxa_pwm_chip *pwm; |
75540c1a | 169 | int ret = 0; |
170 | ||
b52fa7bc MD |
171 | if (IS_ENABLED(CONFIG_OF) && id == NULL) |
172 | id = pxa_pwm_get_id_dt(&pdev->dev); | |
173 | ||
174 | if (id == NULL) | |
175 | return -EINVAL; | |
176 | ||
45b301d2 | 177 | pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); |
d93fc78f | 178 | if (pwm == NULL) |
3d2a98cd | 179 | return -ENOMEM; |
75540c1a | 180 | |
45b301d2 AL |
181 | pwm->clk = devm_clk_get(&pdev->dev, NULL); |
182 | if (IS_ERR(pwm->clk)) | |
183 | return PTR_ERR(pwm->clk); | |
184 | ||
17b2b478 TR |
185 | pwm->chip.dev = &pdev->dev; |
186 | pwm->chip.ops = &pxa_pwm_ops; | |
17b2b478 | 187 | pwm->chip.npwm = (id->driver_data & HAS_SECONDARY_PWM) ? 2 : 1; |
75540c1a | 188 | |
b52fa7bc MD |
189 | if (IS_ENABLED(CONFIG_OF)) { |
190 | pwm->chip.of_xlate = pxa_pwm_of_xlate; | |
191 | pwm->chip.of_pwm_n_cells = 1; | |
192 | } | |
193 | ||
6945fe42 | 194 | pwm->mmio_base = devm_platform_ioremap_resource(pdev, 0); |
6d4294d1 TR |
195 | if (IS_ERR(pwm->mmio_base)) |
196 | return PTR_ERR(pwm->mmio_base); | |
75540c1a | 197 | |
17b2b478 TR |
198 | ret = pwmchip_add(&pwm->chip); |
199 | if (ret < 0) { | |
200 | dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); | |
201 | return ret; | |
3d2a98cd EM |
202 | } |
203 | ||
75540c1a | 204 | platform_set_drvdata(pdev, pwm); |
3d2a98cd | 205 | return 0; |
75540c1a | 206 | } |
207 | ||
77f37917 | 208 | static int pwm_remove(struct platform_device *pdev) |
75540c1a | 209 | { |
17b2b478 | 210 | struct pxa_pwm_chip *chip; |
75540c1a | 211 | |
17b2b478 TR |
212 | chip = platform_get_drvdata(pdev); |
213 | if (chip == NULL) | |
75540c1a | 214 | return -ENODEV; |
215 | ||
abeaf755 | 216 | return pwmchip_remove(&chip->chip); |
75540c1a | 217 | } |
218 | ||
3d2a98cd | 219 | static struct platform_driver pwm_driver = { |
75540c1a | 220 | .driver = { |
221 | .name = "pxa25x-pwm", | |
f409cd38 | 222 | .of_match_table = pwm_of_match, |
75540c1a | 223 | }, |
3d2a98cd | 224 | .probe = pwm_probe, |
fd109112 | 225 | .remove = pwm_remove, |
3d2a98cd | 226 | .id_table = pwm_id_table, |
75540c1a | 227 | }; |
228 | ||
1e185c7a | 229 | module_platform_driver(pwm_driver); |
b5f0228a GL |
230 | |
231 | MODULE_LICENSE("GPL v2"); |