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19ad2b75 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
4dce82c1 SG |
2 | /* |
3 | * Copyright 2012 Freescale Semiconductor, Inc. | |
4dce82c1 SG |
4 | */ |
5 | ||
6 | #include <linux/clk.h> | |
7 | #include <linux/err.h> | |
8 | #include <linux/io.h> | |
9 | #include <linux/kernel.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/of.h> | |
4dce82c1 SG |
12 | #include <linux/platform_device.h> |
13 | #include <linux/pwm.h> | |
14 | #include <linux/slab.h> | |
01bf32e9 | 15 | #include <linux/stmp_device.h> |
4dce82c1 SG |
16 | |
17 | #define SET 0x4 | |
18 | #define CLR 0x8 | |
19 | #define TOG 0xc | |
20 | ||
21 | #define PWM_CTRL 0x0 | |
22 | #define PWM_ACTIVE0 0x10 | |
23 | #define PWM_PERIOD0 0x20 | |
24 | #define PERIOD_PERIOD(p) ((p) & 0xffff) | |
25 | #define PERIOD_PERIOD_MAX 0x10000 | |
26 | #define PERIOD_ACTIVE_HIGH (3 << 16) | |
2cf0f6fe RV |
27 | #define PERIOD_ACTIVE_LOW (2 << 16) |
28 | #define PERIOD_INACTIVE_HIGH (3 << 18) | |
4dce82c1 | 29 | #define PERIOD_INACTIVE_LOW (2 << 18) |
bf29c2ff | 30 | #define PERIOD_POLARITY_NORMAL (PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW) |
2cf0f6fe | 31 | #define PERIOD_POLARITY_INVERSE (PERIOD_ACTIVE_LOW | PERIOD_INACTIVE_HIGH) |
4dce82c1 SG |
32 | #define PERIOD_CDIV(div) (((div) & 0x7) << 20) |
33 | #define PERIOD_CDIV_MAX 8 | |
34 | ||
3c64ed74 RV |
35 | static const u8 cdiv_shift[PERIOD_CDIV_MAX] = { |
36 | 0, 1, 2, 3, 4, 6, 8, 10 | |
24ccea1c GH |
37 | }; |
38 | ||
4dce82c1 SG |
39 | struct mxs_pwm_chip { |
40 | struct pwm_chip chip; | |
4dce82c1 SG |
41 | struct clk *clk; |
42 | void __iomem *base; | |
43 | }; | |
44 | ||
45 | #define to_mxs_pwm_chip(_chip) container_of(_chip, struct mxs_pwm_chip, chip) | |
46 | ||
bf29c2ff RV |
47 | static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
48 | const struct pwm_state *state) | |
49 | { | |
50 | struct mxs_pwm_chip *mxs = to_mxs_pwm_chip(chip); | |
51 | int ret, div = 0; | |
52 | unsigned int period_cycles, duty_cycles; | |
53 | unsigned long rate; | |
54 | unsigned long long c; | |
2cf0f6fe | 55 | unsigned int pol_bits; |
bf29c2ff RV |
56 | |
57 | /* | |
58 | * If the PWM channel is disabled, make sure to turn on the | |
59 | * clock before calling clk_get_rate() and writing to the | |
60 | * registers. Otherwise, just keep it enabled. | |
61 | */ | |
62 | if (!pwm_is_enabled(pwm)) { | |
63 | ret = clk_prepare_enable(mxs->clk); | |
64 | if (ret) | |
65 | return ret; | |
66 | } | |
67 | ||
68 | if (!state->enabled && pwm_is_enabled(pwm)) | |
69 | writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR); | |
70 | ||
71 | rate = clk_get_rate(mxs->clk); | |
72 | while (1) { | |
3c64ed74 | 73 | c = rate >> cdiv_shift[div]; |
bf29c2ff RV |
74 | c = c * state->period; |
75 | do_div(c, 1000000000); | |
76 | if (c < PERIOD_PERIOD_MAX) | |
77 | break; | |
78 | div++; | |
79 | if (div >= PERIOD_CDIV_MAX) | |
80 | return -EINVAL; | |
81 | } | |
82 | ||
83 | period_cycles = c; | |
84 | c *= state->duty_cycle; | |
85 | do_div(c, state->period); | |
86 | duty_cycles = c; | |
87 | ||
88 | /* | |
89 | * The data sheet the says registers must be written to in | |
90 | * this order (ACTIVEn, then PERIODn). Also, the new settings | |
91 | * only take effect at the beginning of a new period, avoiding | |
92 | * glitches. | |
93 | */ | |
2cf0f6fe RV |
94 | |
95 | pol_bits = state->polarity == PWM_POLARITY_NORMAL ? | |
96 | PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE; | |
bf29c2ff RV |
97 | writel(duty_cycles << 16, |
98 | mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20); | |
2cf0f6fe | 99 | writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div), |
bf29c2ff RV |
100 | mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20); |
101 | ||
102 | if (state->enabled) { | |
103 | if (!pwm_is_enabled(pwm)) { | |
104 | /* | |
105 | * The clock was enabled above. Just enable | |
106 | * the channel in the control register. | |
107 | */ | |
108 | writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET); | |
109 | } | |
110 | } else { | |
111 | clk_disable_unprepare(mxs->clk); | |
112 | } | |
113 | return 0; | |
114 | } | |
115 | ||
4dce82c1 | 116 | static const struct pwm_ops mxs_pwm_ops = { |
bf29c2ff | 117 | .apply = mxs_pwm_apply, |
4dce82c1 SG |
118 | .owner = THIS_MODULE, |
119 | }; | |
120 | ||
121 | static int mxs_pwm_probe(struct platform_device *pdev) | |
122 | { | |
123 | struct device_node *np = pdev->dev.of_node; | |
124 | struct mxs_pwm_chip *mxs; | |
125 | int ret; | |
126 | ||
127 | mxs = devm_kzalloc(&pdev->dev, sizeof(*mxs), GFP_KERNEL); | |
128 | if (!mxs) | |
129 | return -ENOMEM; | |
130 | ||
a315614b | 131 | mxs->base = devm_platform_ioremap_resource(pdev, 0); |
6d4294d1 TR |
132 | if (IS_ERR(mxs->base)) |
133 | return PTR_ERR(mxs->base); | |
4dce82c1 | 134 | |
22d260bd SG |
135 | mxs->clk = devm_clk_get(&pdev->dev, NULL); |
136 | if (IS_ERR(mxs->clk)) | |
137 | return PTR_ERR(mxs->clk); | |
4dce82c1 SG |
138 | |
139 | mxs->chip.dev = &pdev->dev; | |
140 | mxs->chip.ops = &mxs_pwm_ops; | |
2cf0f6fe RV |
141 | mxs->chip.of_xlate = of_pwm_xlate_with_flags; |
142 | mxs->chip.of_pwm_n_cells = 3; | |
8c0216f3 | 143 | |
4dce82c1 SG |
144 | ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm); |
145 | if (ret < 0) { | |
146 | dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret); | |
22d260bd | 147 | return ret; |
4dce82c1 SG |
148 | } |
149 | ||
150 | ret = pwmchip_add(&mxs->chip); | |
151 | if (ret < 0) { | |
152 | dev_err(&pdev->dev, "failed to add pwm chip %d\n", ret); | |
22d260bd | 153 | return ret; |
4dce82c1 SG |
154 | } |
155 | ||
4dce82c1 SG |
156 | platform_set_drvdata(pdev, mxs); |
157 | ||
cfb9e4c4 FE |
158 | ret = stmp_reset_block(mxs->base); |
159 | if (ret) | |
160 | goto pwm_remove; | |
4dce82c1 SG |
161 | |
162 | return 0; | |
cfb9e4c4 FE |
163 | |
164 | pwm_remove: | |
165 | pwmchip_remove(&mxs->chip); | |
166 | return ret; | |
4dce82c1 SG |
167 | } |
168 | ||
77f37917 | 169 | static int mxs_pwm_remove(struct platform_device *pdev) |
4dce82c1 SG |
170 | { |
171 | struct mxs_pwm_chip *mxs = platform_get_drvdata(pdev); | |
172 | ||
457fd768 | 173 | return pwmchip_remove(&mxs->chip); |
4dce82c1 SG |
174 | } |
175 | ||
f1a8870a | 176 | static const struct of_device_id mxs_pwm_dt_ids[] = { |
071407ee | 177 | { .compatible = "fsl,imx23-pwm", }, |
4dce82c1 SG |
178 | { /* sentinel */ } |
179 | }; | |
180 | MODULE_DEVICE_TABLE(of, mxs_pwm_dt_ids); | |
181 | ||
182 | static struct platform_driver mxs_pwm_driver = { | |
183 | .driver = { | |
184 | .name = "mxs-pwm", | |
de02cb88 | 185 | .of_match_table = mxs_pwm_dt_ids, |
4dce82c1 SG |
186 | }, |
187 | .probe = mxs_pwm_probe, | |
fd109112 | 188 | .remove = mxs_pwm_remove, |
4dce82c1 SG |
189 | }; |
190 | module_platform_driver(mxs_pwm_driver); | |
191 | ||
192 | MODULE_ALIAS("platform:mxs-pwm"); | |
193 | MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); | |
194 | MODULE_DESCRIPTION("Freescale MXS PWM Driver"); | |
195 | MODULE_LICENSE("GPL v2"); |