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1802d0be | 1 | // SPDX-License-Identifier: GPL-2.0-only |
7e3b7dc7 YH |
2 | /* |
3 | * MediaTek display pulse-width-modulation controller driver. | |
4 | * Copyright (c) 2015 MediaTek Inc. | |
5 | * Author: YH Huang <yh.huang@mediatek.com> | |
7e3b7dc7 YH |
6 | */ |
7 | ||
8 | #include <linux/clk.h> | |
9 | #include <linux/err.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of.h> | |
cd4b45ac | 13 | #include <linux/of_device.h> |
7e3b7dc7 YH |
14 | #include <linux/platform_device.h> |
15 | #include <linux/pwm.h> | |
16 | #include <linux/slab.h> | |
17 | ||
18 | #define DISP_PWM_EN 0x00 | |
7e3b7dc7 | 19 | |
7e3b7dc7 YH |
20 | #define PWM_CLKDIV_SHIFT 16 |
21 | #define PWM_CLKDIV_MAX 0x3ff | |
22 | #define PWM_CLKDIV_MASK (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT) | |
23 | ||
7e3b7dc7 YH |
24 | #define PWM_PERIOD_BIT_WIDTH 12 |
25 | #define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1) | |
26 | ||
27 | #define PWM_HIGH_WIDTH_SHIFT 16 | |
28 | #define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT) | |
29 | ||
cd4b45ac WK |
30 | struct mtk_pwm_data { |
31 | u32 enable_mask; | |
32 | unsigned int con0; | |
33 | u32 con0_sel; | |
34 | unsigned int con1; | |
35 | ||
36 | bool has_commit; | |
37 | unsigned int commit; | |
38 | unsigned int commit_mask; | |
39 | ||
40 | unsigned int bls_debug; | |
41 | u32 bls_debug_mask; | |
42 | }; | |
43 | ||
7e3b7dc7 YH |
44 | struct mtk_disp_pwm { |
45 | struct pwm_chip chip; | |
cd4b45ac | 46 | const struct mtk_pwm_data *data; |
7e3b7dc7 YH |
47 | struct clk *clk_main; |
48 | struct clk *clk_mm; | |
49 | void __iomem *base; | |
50 | }; | |
51 | ||
52 | static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip) | |
53 | { | |
54 | return container_of(chip, struct mtk_disp_pwm, chip); | |
55 | } | |
56 | ||
57 | static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset, | |
58 | u32 mask, u32 data) | |
59 | { | |
60 | void __iomem *address = mdp->base + offset; | |
61 | u32 value; | |
62 | ||
63 | value = readl(address); | |
64 | value &= ~mask; | |
65 | value |= data; | |
66 | writel(value, address); | |
67 | } | |
68 | ||
69 | static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |
70 | int duty_ns, int period_ns) | |
71 | { | |
72 | struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); | |
73 | u32 clk_div, period, high_width, value; | |
74 | u64 div, rate; | |
75 | int err; | |
76 | ||
77 | /* | |
78 | * Find period, high_width and clk_div to suit duty_ns and period_ns. | |
79 | * Calculate proper div value to keep period value in the bound. | |
80 | * | |
81 | * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE | |
82 | * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE | |
83 | * | |
84 | * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1 | |
85 | * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) | |
86 | */ | |
87 | rate = clk_get_rate(mdp->clk_main); | |
88 | clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >> | |
89 | PWM_PERIOD_BIT_WIDTH; | |
90 | if (clk_div > PWM_CLKDIV_MAX) | |
91 | return -EINVAL; | |
92 | ||
93 | div = NSEC_PER_SEC * (clk_div + 1); | |
94 | period = div64_u64(rate * period_ns, div); | |
95 | if (period > 0) | |
96 | period--; | |
97 | ||
98 | high_width = div64_u64(rate * duty_ns, div); | |
99 | value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); | |
100 | ||
101 | err = clk_enable(mdp->clk_main); | |
102 | if (err < 0) | |
103 | return err; | |
104 | ||
105 | err = clk_enable(mdp->clk_mm); | |
106 | if (err < 0) { | |
107 | clk_disable(mdp->clk_main); | |
108 | return err; | |
109 | } | |
110 | ||
cd4b45ac WK |
111 | mtk_disp_pwm_update_bits(mdp, mdp->data->con0, |
112 | PWM_CLKDIV_MASK, | |
7e3b7dc7 | 113 | clk_div << PWM_CLKDIV_SHIFT); |
cd4b45ac WK |
114 | mtk_disp_pwm_update_bits(mdp, mdp->data->con1, |
115 | PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK, | |
116 | value); | |
117 | ||
118 | if (mdp->data->has_commit) { | |
119 | mtk_disp_pwm_update_bits(mdp, mdp->data->commit, | |
120 | mdp->data->commit_mask, | |
121 | mdp->data->commit_mask); | |
122 | mtk_disp_pwm_update_bits(mdp, mdp->data->commit, | |
123 | mdp->data->commit_mask, | |
124 | 0x0); | |
125 | } | |
7e3b7dc7 YH |
126 | |
127 | clk_disable(mdp->clk_mm); | |
128 | clk_disable(mdp->clk_main); | |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
133 | static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) | |
134 | { | |
135 | struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); | |
136 | int err; | |
137 | ||
138 | err = clk_enable(mdp->clk_main); | |
139 | if (err < 0) | |
140 | return err; | |
141 | ||
142 | err = clk_enable(mdp->clk_mm); | |
143 | if (err < 0) { | |
144 | clk_disable(mdp->clk_main); | |
145 | return err; | |
146 | } | |
147 | ||
cd4b45ac WK |
148 | mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, |
149 | mdp->data->enable_mask); | |
7e3b7dc7 YH |
150 | |
151 | return 0; | |
152 | } | |
153 | ||
154 | static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) | |
155 | { | |
156 | struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); | |
157 | ||
cd4b45ac WK |
158 | mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, |
159 | 0x0); | |
7e3b7dc7 YH |
160 | |
161 | clk_disable(mdp->clk_mm); | |
162 | clk_disable(mdp->clk_main); | |
163 | } | |
164 | ||
165 | static const struct pwm_ops mtk_disp_pwm_ops = { | |
166 | .config = mtk_disp_pwm_config, | |
167 | .enable = mtk_disp_pwm_enable, | |
168 | .disable = mtk_disp_pwm_disable, | |
169 | .owner = THIS_MODULE, | |
170 | }; | |
171 | ||
172 | static int mtk_disp_pwm_probe(struct platform_device *pdev) | |
173 | { | |
174 | struct mtk_disp_pwm *mdp; | |
7e3b7dc7 YH |
175 | int ret; |
176 | ||
177 | mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL); | |
178 | if (!mdp) | |
179 | return -ENOMEM; | |
180 | ||
cd4b45ac WK |
181 | mdp->data = of_device_get_match_data(&pdev->dev); |
182 | ||
6e0301e7 | 183 | mdp->base = devm_platform_ioremap_resource(pdev, 0); |
7e3b7dc7 YH |
184 | if (IS_ERR(mdp->base)) |
185 | return PTR_ERR(mdp->base); | |
186 | ||
187 | mdp->clk_main = devm_clk_get(&pdev->dev, "main"); | |
188 | if (IS_ERR(mdp->clk_main)) | |
189 | return PTR_ERR(mdp->clk_main); | |
190 | ||
191 | mdp->clk_mm = devm_clk_get(&pdev->dev, "mm"); | |
192 | if (IS_ERR(mdp->clk_mm)) | |
193 | return PTR_ERR(mdp->clk_mm); | |
194 | ||
195 | ret = clk_prepare(mdp->clk_main); | |
196 | if (ret < 0) | |
197 | return ret; | |
198 | ||
199 | ret = clk_prepare(mdp->clk_mm); | |
200 | if (ret < 0) | |
201 | goto disable_clk_main; | |
202 | ||
203 | mdp->chip.dev = &pdev->dev; | |
204 | mdp->chip.ops = &mtk_disp_pwm_ops; | |
7e3b7dc7 YH |
205 | mdp->chip.npwm = 1; |
206 | ||
207 | ret = pwmchip_add(&mdp->chip); | |
208 | if (ret < 0) { | |
209 | dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); | |
210 | goto disable_clk_mm; | |
211 | } | |
212 | ||
213 | platform_set_drvdata(pdev, mdp); | |
214 | ||
cd4b45ac WK |
215 | /* |
216 | * For MT2701, disable double buffer before writing register | |
217 | * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH. | |
218 | */ | |
219 | if (!mdp->data->has_commit) { | |
220 | mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, | |
221 | mdp->data->bls_debug_mask, | |
222 | mdp->data->bls_debug_mask); | |
223 | mtk_disp_pwm_update_bits(mdp, mdp->data->con0, | |
224 | mdp->data->con0_sel, | |
225 | mdp->data->con0_sel); | |
226 | } | |
227 | ||
7e3b7dc7 YH |
228 | return 0; |
229 | ||
230 | disable_clk_mm: | |
231 | clk_unprepare(mdp->clk_mm); | |
232 | disable_clk_main: | |
233 | clk_unprepare(mdp->clk_main); | |
234 | return ret; | |
235 | } | |
236 | ||
237 | static int mtk_disp_pwm_remove(struct platform_device *pdev) | |
238 | { | |
239 | struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev); | |
7e3b7dc7 | 240 | |
9b7b5736 | 241 | pwmchip_remove(&mdp->chip); |
7e3b7dc7 YH |
242 | clk_unprepare(mdp->clk_mm); |
243 | clk_unprepare(mdp->clk_main); | |
244 | ||
9b7b5736 | 245 | return 0; |
7e3b7dc7 YH |
246 | } |
247 | ||
cd4b45ac WK |
248 | static const struct mtk_pwm_data mt2701_pwm_data = { |
249 | .enable_mask = BIT(16), | |
250 | .con0 = 0xa8, | |
251 | .con0_sel = 0x2, | |
252 | .con1 = 0xac, | |
253 | .has_commit = false, | |
254 | .bls_debug = 0xb0, | |
255 | .bls_debug_mask = 0x3, | |
256 | }; | |
257 | ||
258 | static const struct mtk_pwm_data mt8173_pwm_data = { | |
259 | .enable_mask = BIT(0), | |
260 | .con0 = 0x10, | |
261 | .con0_sel = 0x0, | |
262 | .con1 = 0x14, | |
263 | .has_commit = true, | |
264 | .commit = 0x8, | |
265 | .commit_mask = 0x1, | |
266 | }; | |
267 | ||
a87b4061 JS |
268 | static const struct mtk_pwm_data mt8183_pwm_data = { |
269 | .enable_mask = BIT(0), | |
270 | .con0 = 0x18, | |
271 | .con0_sel = 0x0, | |
272 | .con1 = 0x1c, | |
273 | .has_commit = false, | |
274 | .bls_debug = 0x80, | |
275 | .bls_debug_mask = 0x3, | |
276 | }; | |
277 | ||
7e3b7dc7 | 278 | static const struct of_device_id mtk_disp_pwm_of_match[] = { |
cd4b45ac WK |
279 | { .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data}, |
280 | { .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data}, | |
281 | { .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data}, | |
a87b4061 | 282 | { .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data}, |
7e3b7dc7 YH |
283 | { } |
284 | }; | |
285 | MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match); | |
286 | ||
287 | static struct platform_driver mtk_disp_pwm_driver = { | |
288 | .driver = { | |
289 | .name = "mediatek-disp-pwm", | |
290 | .of_match_table = mtk_disp_pwm_of_match, | |
291 | }, | |
292 | .probe = mtk_disp_pwm_probe, | |
293 | .remove = mtk_disp_pwm_remove, | |
294 | }; | |
295 | module_platform_driver(mtk_disp_pwm_driver); | |
296 | ||
297 | MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>"); | |
298 | MODULE_DESCRIPTION("MediaTek SoC display PWM driver"); | |
299 | MODULE_LICENSE("GPL v2"); |