[linux-block.git] / drivers / pwm / pwm-mtk-disp.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * MediaTek display pulse-width-modulation controller driver.
 * Copyright (c) 2015 MediaTek Inc.
 * Author: YH Huang <yh.huang@mediatek.com>
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/slab.h>

#define DISP_PWM_EN		0x00

#define PWM_CLKDIV_SHIFT	16
#define PWM_CLKDIV_MAX		0x3ff
#define PWM_CLKDIV_MASK		(PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)

#define PWM_PERIOD_BIT_WIDTH	12
#define PWM_PERIOD_MASK		((1 << PWM_PERIOD_BIT_WIDTH) - 1)

#define PWM_HIGH_WIDTH_SHIFT	16
#define PWM_HIGH_WIDTH_MASK	(0x1fff << PWM_HIGH_WIDTH_SHIFT)

struct mtk_pwm_data {
	u32 enable_mask;
	unsigned int con0;
	u32 con0_sel;
	unsigned int con1;

	bool has_commit;
	unsigned int commit;
	unsigned int commit_mask;

	unsigned int bls_debug;
	u32 bls_debug_mask;
};

struct mtk_disp_pwm {
	struct pwm_chip chip;
	const struct mtk_pwm_data *data;
	struct clk *clk_main;
	struct clk *clk_mm;
	void __iomem *base;
};

static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
{
	return container_of(chip, struct mtk_disp_pwm, chip);
}

static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
				     u32 mask, u32 data)
{
	void __iomem *address = mdp->base + offset;
	u32 value;

	value = readl(address);
	value &= ~mask;
	value |= data;
	writel(value, address);
}

static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
			       int duty_ns, int period_ns)
{
	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	u32 clk_div, period, high_width, value;
	u64 div, rate;
	int err;

	err = clk_prepare_enable(mdp->clk_main);
	if (err < 0) {
		dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
		return err;
	}

	err = clk_prepare_enable(mdp->clk_mm);
	if (err < 0) {
		dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
		clk_disable_unprepare(mdp->clk_main);
		return err;
	}

	/*
	 * Find period, high_width and clk_div to suit duty_ns and period_ns.
	 * Calculate proper div value to keep period value in the bound.
	 *
	 * period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
	 * duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
	 *
	 * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
	 * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
	 */
	rate = clk_get_rate(mdp->clk_main);
	clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >>
			  PWM_PERIOD_BIT_WIDTH;
	if (clk_div > PWM_CLKDIV_MAX) {
		clk_disable_unprepare(mdp->clk_mm);
		clk_disable_unprepare(mdp->clk_main);
		return -EINVAL;
	}

	div = NSEC_PER_SEC * (clk_div + 1);
	period = div64_u64(rate * period_ns, div);
	if (period > 0)
		period--;

	high_width = div64_u64(rate * duty_ns, div);
	value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);

	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
				 PWM_CLKDIV_MASK,
				 clk_div << PWM_CLKDIV_SHIFT);
	mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
				 PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
				 value);

	if (mdp->data->has_commit) {
		mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
					 mdp->data->commit_mask,
					 mdp->data->commit_mask);
		mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
					 mdp->data->commit_mask,
					 0x0);
	} else {
		/*
		 * For MT2701, disable double buffer before writing register
		 * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
		 */
		mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
					 mdp->data->bls_debug_mask,
					 mdp->data->bls_debug_mask);
		mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
					 mdp->data->con0_sel,
					 mdp->data->con0_sel);
	}

	clk_disable_unprepare(mdp->clk_mm);
	clk_disable_unprepare(mdp->clk_main);

	return 0;
}

static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	int err;

	err = clk_prepare_enable(mdp->clk_main);
	if (err < 0) {
		dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
		return err;
	}

	err = clk_prepare_enable(mdp->clk_mm);
	if (err < 0) {
		dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
		clk_disable_unprepare(mdp->clk_main);
		return err;
	}

	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
				 mdp->data->enable_mask);

	return 0;
}

static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);

	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
				 0x0);

	clk_disable_unprepare(mdp->clk_mm);
	clk_disable_unprepare(mdp->clk_main);
}

static const struct pwm_ops mtk_disp_pwm_ops = {
	.config = mtk_disp_pwm_config,
	.enable = mtk_disp_pwm_enable,
	.disable = mtk_disp_pwm_disable,
	.owner = THIS_MODULE,
};

static int mtk_disp_pwm_probe(struct platform_device *pdev)
{
	struct mtk_disp_pwm *mdp;
	int ret;

	mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
	if (!mdp)
		return -ENOMEM;

	mdp->data = of_device_get_match_data(&pdev->dev);

	mdp->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(mdp->base))
		return PTR_ERR(mdp->base);

	mdp->clk_main = devm_clk_get(&pdev->dev, "main");
	if (IS_ERR(mdp->clk_main))
		return PTR_ERR(mdp->clk_main);

	mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
	if (IS_ERR(mdp->clk_mm))
		return PTR_ERR(mdp->clk_mm);

	mdp->chip.dev = &pdev->dev;
	mdp->chip.ops = &mtk_disp_pwm_ops;
	mdp->chip.npwm = 1;

	ret = pwmchip_add(&mdp->chip);
	if (ret < 0) {
		dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
		return ret;
	}

	platform_set_drvdata(pdev, mdp);

	return 0;
}

static int mtk_disp_pwm_remove(struct platform_device *pdev)
{
	struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);

	pwmchip_remove(&mdp->chip);

	return 0;
}

static const struct mtk_pwm_data mt2701_pwm_data = {
	.enable_mask = BIT(16),
	.con0 = 0xa8,
	.con0_sel = 0x2,
	.con1 = 0xac,
	.has_commit = false,
	.bls_debug = 0xb0,
	.bls_debug_mask = 0x3,
};

static const struct mtk_pwm_data mt8173_pwm_data = {
	.enable_mask = BIT(0),
	.con0 = 0x10,
	.con0_sel = 0x0,
	.con1 = 0x14,
	.has_commit = true,
	.commit = 0x8,
	.commit_mask = 0x1,
};

static const struct mtk_pwm_data mt8183_pwm_data = {
	.enable_mask = BIT(0),
	.con0 = 0x18,
	.con0_sel = 0x0,
	.con1 = 0x1c,
	.has_commit = false,
	.bls_debug = 0x80,
	.bls_debug_mask = 0x3,
};

static const struct of_device_id mtk_disp_pwm_of_match[] = {
	{ .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
	{ .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
	{ .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
	{ .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
	{ }
};
MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);

static struct platform_driver mtk_disp_pwm_driver = {
	.driver = {
		.name = "mediatek-disp-pwm",
		.of_match_table = mtk_disp_pwm_of_match,
	},
	.probe = mtk_disp_pwm_probe,
	.remove = mtk_disp_pwm_remove,
};
module_platform_driver(mtk_disp_pwm_driver);

MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
7e3b7dc7 YH	2	/*
	3	* MediaTek display pulse-width-modulation controller driver.
	4	* Copyright (c) 2015 MediaTek Inc.
	5	* Author: YH Huang <yh.huang@mediatek.com>
7e3b7dc7 YH	6	*/
	7
	8	#include <linux/clk.h>
	9	#include <linux/err.h>
	10	#include <linux/io.h>
	11	#include <linux/module.h>
	12	#include <linux/of.h>
cd4b45ac	13	#include <linux/of_device.h>
7e3b7dc7 YH	14	#include <linux/platform_device.h>
	15	#include <linux/pwm.h>
	16	#include <linux/slab.h>
	17
	18	#define DISP_PWM_EN 0x00
7e3b7dc7	19
7e3b7dc7 YH	20	#define PWM_CLKDIV_SHIFT 16
	21	#define PWM_CLKDIV_MAX 0x3ff
	22	#define PWM_CLKDIV_MASK (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
	23
7e3b7dc7 YH	24	#define PWM_PERIOD_BIT_WIDTH 12
	25	#define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
	26
	27	#define PWM_HIGH_WIDTH_SHIFT 16
	28	#define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT)
	29
cd4b45ac WK	30	struct mtk_pwm_data {
	31	u32 enable_mask;
	32	unsigned int con0;
	33	u32 con0_sel;
	34	unsigned int con1;
	35
	36	bool has_commit;
	37	unsigned int commit;
	38	unsigned int commit_mask;
	39
	40	unsigned int bls_debug;
	41	u32 bls_debug_mask;
	42	};
	43
7e3b7dc7 YH	44	struct mtk_disp_pwm {
7e3b7dc7 YH	45	struct pwm_chip chip;
cd4b45ac	46	const struct mtk_pwm_data *data;
7e3b7dc7 YH	47	struct clk *clk_main;
	48	struct clk *clk_mm;
	49	void __iomem *base;
	50	};
	51
	52	static inline struct mtk_disp_pwm to_mtk_disp_pwm(struct pwm_chip chip)
	53	{
	54	return container_of(chip, struct mtk_disp_pwm, chip);
	55	}
	56
	57	static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
	58	u32 mask, u32 data)
	59	{
	60	void __iomem *address = mdp->base + offset;
	61	u32 value;
	62
	63	value = readl(address);
	64	value &= ~mask;
	65	value \|= data;
	66	writel(value, address);
	67	}
	68
	69	static int mtk_disp_pwm_config(struct pwm_chip chip, struct pwm_device pwm,
	70	int duty_ns, int period_ns)
	71	{
	72	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	73	u32 clk_div, period, high_width, value;
	74	u64 div, rate;
	75	int err;
	76
d7a4e582 JS	77	err = clk_prepare_enable(mdp->clk_main);
	78	if (err < 0) {
	79	dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
	80	return err;
	81	}
	82
	83	err = clk_prepare_enable(mdp->clk_mm);
	84	if (err < 0) {
	85	dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
	86	clk_disable_unprepare(mdp->clk_main);
	87	return err;
	88	}
	89
7e3b7dc7 YH	90	/*
	91	* Find period, high_width and clk_div to suit duty_ns and period_ns.
	92	* Calculate proper div value to keep period value in the bound.
	93	*
	94	* period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
	95	* duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
	96	*
	97	* period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
	98	* high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
	99	*/
	100	rate = clk_get_rate(mdp->clk_main);
	101	clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >>
	102	PWM_PERIOD_BIT_WIDTH;
d7a4e582 JS	103	if (clk_div > PWM_CLKDIV_MAX) {
	104	clk_disable_unprepare(mdp->clk_mm);
	105	clk_disable_unprepare(mdp->clk_main);
7e3b7dc7	106	return -EINVAL;
d7a4e582	107	}
7e3b7dc7 YH	108
	109	div = NSEC_PER_SEC * (clk_div + 1);
	110	period = div64_u64(rate * period_ns, div);
	111	if (period > 0)
	112	period--;
	113
	114	high_width = div64_u64(rate * duty_ns, div);
	115	value = period \| (high_width << PWM_HIGH_WIDTH_SHIFT);
	116
cd4b45ac WK	117	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
cd4b45ac WK	118	PWM_CLKDIV_MASK,
7e3b7dc7	119	clk_div << PWM_CLKDIV_SHIFT);
cd4b45ac WK	120	mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
	121	PWM_PERIOD_MASK \| PWM_HIGH_WIDTH_MASK,
	122	value);
	123
	124	if (mdp->data->has_commit) {
	125	mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
	126	mdp->data->commit_mask,
	127	mdp->data->commit_mask);
	128	mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
	129	mdp->data->commit_mask,
	130	0x0);
d7a4e582 JS	131	} else {
	132	/*
	133	* For MT2701, disable double buffer before writing register
	134	* and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
	135	*/
	136	mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
	137	mdp->data->bls_debug_mask,
	138	mdp->data->bls_debug_mask);
	139	mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
	140	mdp->data->con0_sel,
	141	mdp->data->con0_sel);
cd4b45ac	142	}
7e3b7dc7	143
d7a4e582 JS	144	clk_disable_unprepare(mdp->clk_mm);
d7a4e582 JS	145	clk_disable_unprepare(mdp->clk_main);
7e3b7dc7 YH	146
	147	return 0;
	148	}
	149
	150	static int mtk_disp_pwm_enable(struct pwm_chip chip, struct pwm_device pwm)
	151	{
	152	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	153	int err;
	154
d7a4e582 JS	155	err = clk_prepare_enable(mdp->clk_main);
	156	if (err < 0) {
	157	dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err));
7e3b7dc7	158	return err;
d7a4e582	159	}
7e3b7dc7	160
d7a4e582	161	err = clk_prepare_enable(mdp->clk_mm);
7e3b7dc7	162	if (err < 0) {
d7a4e582 JS	163	dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err));
d7a4e582 JS	164	clk_disable_unprepare(mdp->clk_main);
7e3b7dc7 YH	165	return err;
	166	}
	167
cd4b45ac WK	168	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
cd4b45ac WK	169	mdp->data->enable_mask);
7e3b7dc7 YH	170
	171	return 0;
	172	}
	173
	174	static void mtk_disp_pwm_disable(struct pwm_chip chip, struct pwm_device pwm)
	175	{
	176	struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
	177
cd4b45ac WK	178	mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
cd4b45ac WK	179	0x0);
7e3b7dc7	180
d7a4e582 JS	181	clk_disable_unprepare(mdp->clk_mm);
d7a4e582 JS	182	clk_disable_unprepare(mdp->clk_main);
7e3b7dc7 YH	183	}
	184
	185	static const struct pwm_ops mtk_disp_pwm_ops = {
	186	.config = mtk_disp_pwm_config,
	187	.enable = mtk_disp_pwm_enable,
	188	.disable = mtk_disp_pwm_disable,
	189	.owner = THIS_MODULE,
	190	};
	191
	192	static int mtk_disp_pwm_probe(struct platform_device *pdev)
	193	{
	194	struct mtk_disp_pwm *mdp;
7e3b7dc7 YH	195	int ret;
	196
	197	mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
	198	if (!mdp)
	199	return -ENOMEM;
	200
cd4b45ac WK	201	mdp->data = of_device_get_match_data(&pdev->dev);
cd4b45ac WK	202
6e0301e7	203	mdp->base = devm_platform_ioremap_resource(pdev, 0);
7e3b7dc7 YH	204	if (IS_ERR(mdp->base))
	205	return PTR_ERR(mdp->base);
	206
	207	mdp->clk_main = devm_clk_get(&pdev->dev, "main");
	208	if (IS_ERR(mdp->clk_main))
	209	return PTR_ERR(mdp->clk_main);
	210
	211	mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
	212	if (IS_ERR(mdp->clk_mm))
	213	return PTR_ERR(mdp->clk_mm);
	214
7e3b7dc7 YH	215	mdp->chip.dev = &pdev->dev;
7e3b7dc7 YH	216	mdp->chip.ops = &mtk_disp_pwm_ops;
7e3b7dc7 YH	217	mdp->chip.npwm = 1;
	218
	219	ret = pwmchip_add(&mdp->chip);
	220	if (ret < 0) {
d7a4e582 JS	221	dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret));
d7a4e582 JS	222	return ret;
7e3b7dc7 YH	223	}
	224
	225	platform_set_drvdata(pdev, mdp);
	226
	227	return 0;
7e3b7dc7 YH	228	}
	229
	230	static int mtk_disp_pwm_remove(struct platform_device *pdev)
	231	{
	232	struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
7e3b7dc7	233
9b7b5736	234	pwmchip_remove(&mdp->chip);
7e3b7dc7	235
9b7b5736	236	return 0;
7e3b7dc7 YH	237	}
7e3b7dc7 YH	238
cd4b45ac WK	239	static const struct mtk_pwm_data mt2701_pwm_data = {
	240	.enable_mask = BIT(16),
	241	.con0 = 0xa8,
	242	.con0_sel = 0x2,
	243	.con1 = 0xac,
	244	.has_commit = false,
	245	.bls_debug = 0xb0,
	246	.bls_debug_mask = 0x3,
	247	};
	248
	249	static const struct mtk_pwm_data mt8173_pwm_data = {
	250	.enable_mask = BIT(0),
	251	.con0 = 0x10,
	252	.con0_sel = 0x0,
	253	.con1 = 0x14,
	254	.has_commit = true,
	255	.commit = 0x8,
	256	.commit_mask = 0x1,
	257	};
	258
a87b4061 JS	259	static const struct mtk_pwm_data mt8183_pwm_data = {
	260	.enable_mask = BIT(0),
	261	.con0 = 0x18,
	262	.con0_sel = 0x0,
	263	.con1 = 0x1c,
	264	.has_commit = false,
	265	.bls_debug = 0x80,
	266	.bls_debug_mask = 0x3,
	267	};
	268
7e3b7dc7	269	static const struct of_device_id mtk_disp_pwm_of_match[] = {
cd4b45ac WK	270	{ .compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
	271	{ .compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
	272	{ .compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
a87b4061	273	{ .compatible = "mediatek,mt8183-disp-pwm", .data = &mt8183_pwm_data},
7e3b7dc7 YH	274	{ }
	275	};
	276	MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
	277
	278	static struct platform_driver mtk_disp_pwm_driver = {
	279	.driver = {
	280	.name = "mediatek-disp-pwm",
	281	.of_match_table = mtk_disp_pwm_of_match,
	282	},
	283	.probe = mtk_disp_pwm_probe,
	284	.remove = mtk_disp_pwm_remove,
	285	};
	286	module_platform_driver(mtk_disp_pwm_driver);
	287
	288	MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
	289	MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
	290	MODULE_LICENSE("GPL v2");